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41. 发明授权

US09503091B2 Wordline decoder circuits for embedded charge trap multi-time-programmable-read-only-memory 有权
标题翻译：用于嵌入式电荷陷阱多时间可编程只读存储器的字线解码器电路
公开(公告)号：US09503091B2
公开(公告)日：2016-11-22
申请号：US14084641
申请日：2013-11-20
申请人： GLOBALFOUNDRIES INC.
发明人： Toshiaki Kirihata , Derek H. Leu , Ming Yin
IPC分类号： G11C11/56 , G11C16/08 , H03K19/0175 , G11C16/04 , G11C16/12 , G06F17/50
CPC分类号： H03K19/017509 , G06F17/5045 , G06F2217/78 , G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , Y02E60/76 , Y04S40/22
摘要： Wordline decoder circuits for an embedded Multi-Time-Read-Only-Memory that includes a plurality of NMOS memory cells coupled to a plurality of wordlines in each row. The wordline decoder circuits control the charge trap behavior of the target NMOS memory array by the mode-dependent wordline high voltage (VWLH) and wordline low voltage (VWLL) trapping the charge in a programming mode by applying an elevated wordline voltage (EWLH) to one of the plurality of WLs, while de-trapping the charge in a reset mode by applying a negative wordline voltage (NWLL) to the entire array. The mode dependent voltage control is realized by switching to couple EWLH to VWLH in a programming mode, otherwise VDD to VWLH, while coupling NWLL to VWLL in a reset mode, otherwise, GND to VWLL. The switch includes plural gated diodes from VWLH with the wordline high protection voltage of VWLH_PR generated by lowering VWLH determined by gated diodes times threshold voltage. The switch includes a series of gated diodes from VWLL with a wordline low protection voltage of VWLL_PR generated by raising VWLL determined by the gated diodes by the threshold voltage, resulting in controlling the WL swing using thin-oxide devices.
摘要翻译：用于嵌入式多时间只读存储器的字线解码器电路，其包括耦合到每行中的多个字线的多个NMOS存储器单元。字线解码器电路通过将升高的字线电压（EWLH）施加到编程模式中，通过模式相关字线高电压（VWLH）和字线低电压（VWLL）捕获电荷来控制目标NMOS存储器阵列的电荷陷阱行为多个WL中的一个，同时通过向整个阵列施加负的字线电压（NWLL）而以复位模式捕获电荷。通过在编程模式下将EWLH耦合到VWLH来切换模式相关的电压控制，否则将VDD置于VWLH，而在复位模式下将NWLL耦合到VWLL，否则将GND接地VWLL。该开关包括来自VWLH的多个门控二极管，通过降低由门控二极管确定的VWLH产生的VWLH_PR的字线高保护电压达到阈值电压。该开关包括一系列来自VWLL的门控二极管，通过将由门控二极管确定的VWLL提高阈值电压而产生的字线低VWLL_PR的保护电压，从而使用薄氧化物器件控制WL摆幅。

42. 发明申请

US20160336939A1 METHOD OF OPERATING A PULL-UP CIRCUIT 审中-公开
标题翻译：上拉电路的操作方法
公开(公告)号：US20160336939A1
公开(公告)日：2016-11-17
申请号：US15219599
申请日：2016-07-26
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Ming Hsien TSAI
IPC分类号： H03K19/0175
CPC分类号： H03K19/017509 , H03K5/003
摘要： A method of operating a pull-up circuit includes turning off a first transistor of the pull-up circuit during a failsafe period by a feedback signal, the feedback signal being received by way of a feedback circuit; isolating the first transistor from the feedback circuit during a pull-up period; and coupling or isolating a control terminal of the first transistor and a control terminal of a second transistor of the pull-up circuit during the pull-up period by a first switch.
摘要翻译：操作上拉电路的方法包括在故障安全期间通过反馈信号来关断上拉电路的第一晶体管，反馈信号通过反馈电路接收; 在上拉期间将第一晶体管与反馈电路隔离; 以及在上拉期间通过第一开关耦合或隔离所述第一晶体管的控制端和所述上拉电路的第二晶体管的控制端。

43. 发明授权

US09467146B2 Output circuit adapted for integrated circuit and associated control method 有权
标题翻译：输出电路适用于集成电路及相关控制方法
公开(公告)号：US09467146B2
公开(公告)日：2016-10-11
申请号：US14607167
申请日：2015-01-28
申请人： MStar Semiconductor, Inc.
发明人： Shun-Tien Chou
IPC分类号： H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018514 , H03K19/017509
摘要： An output circuit adapted for an integrated circuit is provided. The output circuit includes a driver, a pre-driver and a buffer circuit. The driver is electrically connected to two output nodes outside the integrated circuit to output signals. The pre-driver controls the driver, and includes a load and an input transistor connected in series. Between the load and the input transistor is a connection node for controlling the driver. The buffer circuit controls the load and the input transistor according to an internal signal. Before turning off the input transistor, the buffer circuit pre charges the connection node through the load.
摘要翻译：提供一种适用于集成电路的输出电路。输出电路包括驱动器，预驱动器和缓冲电路。驱动器电连接到集成电路外部的两个输出节点以输出信号。预驱动器控制驱动器，并包括串联连接的负载和输入晶体管。在负载和输入晶体管之间是用于控制驱动器的连接节点。缓冲电路根据内部信号控制负载和输入晶体管。在关闭输入晶体管之前，缓冲电路通过负载对连接节点进行预充电。

44. 发明申请

US20160268971A1 Current Driven Crystal Oscillator 有权
标题翻译：电流驱动晶体振荡器
公开(公告)号：US20160268971A1
公开(公告)日：2016-09-15
申请号：US15067280
申请日：2016-03-11
申请人： Dialog Semiconductor B.V.
发明人： Petrus Hendrikus Seesink
IPC分类号： H03B5/36 , H03K19/0175
CPC分类号： H03B5/364 , H03B5/06 , H03B5/12 , H03B5/30 , H03B5/32 , H03B2200/0094 , H03K19/017509
摘要： An oscillator circuit with an oscillator stage and a first current source arranged to drive the oscillator stage is presented. The oscillator stage has an oscillator stage input terminal, an oscillator stage output terminal, an oscillator arranged to provide an oscillating signal between the oscillator stage input terminal and the oscillator stage output terminal. The oscillator circuit has an operational amplifier with an inverting input, a non-inverting input and an operational amplifier output. The oscillator stage input terminal and the oscillator stage output terminal are coupled to the inverting input and non-inverting input. The operational amplifier output is coupled to the oscillator stage input terminal such that the oscillator stage input terminal and the oscillator stage output terminal are controlled to have a same DC voltage level.
摘要翻译：提出了具有振荡器级和布置成驱动振荡器级的第一电流源的振荡器电路。振荡器级具有振荡器级输入端子，振荡器级输出端子，振荡器，用于在振荡级输入端子和振荡级输出端子之间提供振荡信号。振荡器电路具有运算放大器，具有反相输入，非反相输入和运算放大器输出。振荡器级输入端子和振荡器级输出端子耦合到反相输入和非反相输入。运算放大器输出耦合到振荡器级输入端子，使得振荡器级输入端子和振荡器级输出端子被控制为具有相同的直流电压电平。

45. 发明授权

US09425793B2 Circuit for generating bias voltage for high speed input/output pad 有权
标题翻译：用于产生高速输入/输出板偏置电压的电路
公开(公告)号：US09425793B2
公开(公告)日：2016-08-23
申请号：US14653112
申请日：2012-12-17
申请人： SMARTPHY INC.
发明人： Jaewoo Park , Ook Kim
IPC分类号： H03K19/003 , H03K19/0185 , H03K19/0175
CPC分类号： H03K19/00361 , H03K19/017509 , H03K19/018507
摘要： The present invention provides a circuit for generating a bias voltage for a high speed input/output pad. To this end, a bias voltage generator according to an embodiment of the present invention is to supply at least one bias voltage to a buffer circuit connected to the pad, which includes: a bias generation part for generating a first bias voltage; and a reference voltage generation part for generating a voltage proportional to the pad voltage applied to the pad as a reference voltage, wherein the first bias voltage may be the sum of the reference voltage and a predetermined voltage.
摘要翻译：本发明提供一种用于产生用于高速输入/输出焊盘的偏置电压的电路。为此，根据本发明实施例的偏置电压发生器是将至少一个偏置电压提供给连接到该焊盘的缓冲电路，该缓冲电路包括：用于产生第一偏置电压的偏置产生部分; 以及参考电压产生部分，用于产生与施加到焊盘的焊盘电压成比例的电压作为参考电压，其中第一偏置电压可以是参考电压和预定电压之和。

46. 发明授权

US09423466B2 Semiconductor circuit and semiconductor device 有权
标题翻译：半导体电路和半导体器件
公开(公告)号：US09423466B2
公开(公告)日：2016-08-23
申请号：US13211463
申请日：2011-08-17
申请人： Yoshihiro Murakami
发明人： Yoshihiro Murakami
IPC分类号： H02J7/00 , G01R31/36 , H01M10/44 , H01M10/48 , H01M10/0525
CPC分类号： H01M10/482 , G01R31/362 , G01R31/3658 , H01M10/0525 , H01M10/441 , H01M2220/20 , H03K19/017509 , Y02T10/7011
摘要： In a semiconductor circuit, a high frequency level detecting unit detects a level of a high frequency component adjusted with a first adjusting unit, and a first control unit controls a first gain of the adjusting unit according to the level of the high frequency component thus detected. Further, a low frequency level detecting unit detects a level of a low frequency component adjusted with a second adjusting unit. A second control unit controls a second gain according to the level of the high frequency component and the level of the low frequency component thus adjusted, so that a difference between the level of the high frequency component adjusted with the first adjusting unit and the level of the low frequency component adjusted with the second adjusting unit becomes smaller than a specific level determined in advance.
摘要翻译：在半导体电路中，高频电平检测单元检测由第一调整单元调整的高频分量的电平，第一控制单元根据检测到的高频分量的电平来控制调整单元的第一增益。此外，低频电平检测单元检测由第二调整单元调整的低频分量的电平。第二控制单元根据高频分量的电平和由此调整的低频分量的电平来控制第二增益，使得由第一调整单元调整的高频分量的电平与第一调整单元的电平之间的差用第二调节单元调节的低频分量变得比预先确定的特定水平小。

47. 发明授权

US09419624B2 Power management system for integrated circuits 有权
标题翻译：集成电路电源管理系统
公开(公告)号：US09419624B2
公开(公告)日：2016-08-16
申请号：US14539697
申请日：2014-11-12
申请人： Xilinx, Inc.
发明人： Austin H. Lesea
IPC分类号： H03K19/173 , H03K19/177 , H03K19/0175
CPC分类号： H03K19/17772 , H03K19/00384 , H03K19/017509 , H03K19/17784
摘要： An apparatus includes a plurality of programmable hardware resources and an analog-to-digital converter (ADC) disposed on an IC die. The ADC is configured to quantize values of one or more analog parameters of the IC die. The apparatus also includes a configuration control circuit configured to program the programmable hardware resources in response to a set of configuration data. The programmable hardware resources are programmed to implement a set of circuits specified by the configuration data and to connect the ADC to respective nodes of the IC die for sampling the analog parameters. The apparatus also includes an interface circuit coupled to the ADC and configured to generate a control signal based on quantized values of the one or more analog parameters from the ADC. The interface circuit outputs the control signal to a power supply coupled to a power terminal of the IC die.
摘要翻译：一种装置包括多个可编程硬件资源和设置在IC芯片上的模数转换器（ADC）。 ADC被配置为量化IC芯片的一个或多个模拟参数的值。该装置还包括配置控制电路，配置为响应于一组配置数据对可编程硬件资源进行编程。可编程硬件资源被编程为实现由配置数据指定的一组电路，并将ADC连接到IC芯片的相应节点，以对模拟参数进行采样。该装置还包括耦合到ADC并被配置为基于来自ADC的一个或多个模拟参数的量化值产生控制信号的接口电路。接口电路将控制信号输出到耦合到IC芯片的电源端子的电源。

48. 发明申请

US20160211848A1 DRIVER CIRCUIT 有权
标题翻译：驱动电路
公开(公告)号：US20160211848A1
公开(公告)日：2016-07-21
申请号：US14600727
申请日：2015-01-20
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Ying-Yu HSU , Chien-Chun TSAI
IPC分类号： H03K19/0175
CPC分类号： H03K19/017509
摘要： A circuit comprises a voltage supply node, a reference voltage node, and a plurality of transistors coupled with the voltage supply node and the reference voltage node. The circuit also comprises a circuit input, a first delay element and a second delay element. The first delay element is coupled with the circuit input and one transistor of the plurality of transistors. The second delay element is coupled with the circuit input and a second transistor of the plurality of transistors. The circuit further comprises a circuit output coupled with the first transistor of the plurality of transistors and the second transistor of the plurality of transistors. The circuit additionally comprises a bias generator coupled with the circuit output, the first transistor of the plurality of transistors and the second transistor of the plurality of transistors.
摘要翻译：电路包括电压供应节点，参考电压节点和与电压供应节点和参考电压节点耦合的多个晶体管。电路还包括电路输入，第一延迟元件和第二延迟元件。第一延迟元件与电路输入和多个晶体管中的一个晶体管耦合。第二延迟元件与多个晶体管的电路输入端和第二晶体管耦合。电路还包括与多个晶体管中的第一晶体管和多个晶体管的第二晶体管耦合的电路输出。电路还包括与电路输出耦合的偏置发生器，多个晶体管中的第一晶体管和多个晶体管中的第二晶体管。

49. 发明申请

US20160197611A1 REFERENCE VOLTAGE TRAINING DEVICE AND METHOD THEREOF 有权
标题翻译：参考电压训练装置及其方法
公开(公告)号：US20160197611A1
公开(公告)日：2016-07-07
申请号：US14976716
申请日：2015-12-21
申请人： Samsung Electronics Co., Ltd.
发明人： Seok-Young KANG , Hun-Dae CHOI
IPC分类号： H03K19/0175 , G11C7/22
CPC分类号： H03K19/017509 , G11C5/147 , G11C7/062 , G11C7/1084 , G11C7/12 , G11C7/14 , G11C7/22 , G11C7/222 , G11C29/028 , G11C2207/2254
摘要： Provided are a reference voltage training device and a method thereof. The reference voltage training device includes a comparator configured to compare a toggle signal with a reference voltage and output a comparison signal, a duty cycle detector configured to check a duty ratio of the comparison signal, and a reference voltage level changing unit configured to fix the reference voltage when the duty ratio meets a predetermined condition and to change a level of the reference voltage when the duty ratio does not meet the predetermined condition. The comparator outputs a changed comparison signal using the changed reference voltage.
摘要翻译：提供了一种参考电压训练装置及其方法。参考电压训练装置包括：比较器，被配置为将触发信号与参考电压进行比较并输出比较信号;配置为检查比较信号的占空比的占空比检测器;以及参考电压电平改变单元，当占空比满足预定条件时的参考电压，并且当占空比不满足预定条件时改变参考电压的电平。比较器使用改变的参考电压输出改变的比较信号。

50. 发明申请

US20160191058A1 INTEGRATED CIRCUIT LAYOUT WIRING FOR MULTI-CORE CHIPS 审中-公开
公开(公告)号：US20160191058A1
公开(公告)日：2016-06-30
申请号：US14985887
申请日：2015-12-31
申请人： STMicroelectronics, Inc.
发明人： Chetan BISHT , Harry SCRIVENER, III
IPC分类号： H03K19/0175 , H01L23/50 , H01L27/02 , H01L23/528
CPC分类号： H03K19/017509 , G06F17/5072 , G06F17/5077 , H01L23/50 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.

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