专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20020142546A1 Two mask floating gate EEPROM and method of making 失效
标题翻译：两个掩模浮栅EEPROM及其制作方法
公开(公告)号：US20020142546A1
公开(公告)日：2002-10-03
申请号：US10066376
申请日：2002-02-05
申请人： MATRIX SEMICONDUCTOR, INC.
发明人： Igor G. Kouznetsov , Andrew J. Walker
IPC分类号： H01L021/336 , H01L021/8234
CPC分类号： H01L29/7926 , H01L27/0688 , H01L27/112 , H01L27/12 , H01L29/42324 , H01L29/7881 , H01L29/792 , H01L29/8616
摘要： There is provided a floating gate transistor, such as an EEPROM transistor, and method of making the transistor using two masking steps. The method of making a transistor includes patterning a floating gate layer using a first photoresist mask to form a floating gate rail and doping an active area using the floating gate rail as a mask to form source and drain regions in the active area. The method also includes patterning a control gate layer, a control gate dielectric layer, the floating gate rail, a tunnel dielectric layer and the active area using a second photoresist mask to form a control gate, a control gate dielectric, a floating gate, a tunnel dielectric and a channel island region.
摘要翻译：提供了诸如EEPROM晶体管的浮动栅极晶体管，以及使用两个掩模步骤制造晶体管的方法。制造晶体管的方法包括使用第一光致抗蚀剂掩模图案化浮栅，以形成浮栅，并且使用浮置栅极作为掩模掺杂有源区，以在有源区中形成源区和漏区。该方法还包括使用第二光致抗蚀剂掩模来形成控制栅极层，控制栅极介电层，浮动栅极轨道，隧道介电层和有源区域以形成控制栅极，控制栅极电介质，浮动栅极，隧道电介质和沟道岛区。

42. 发明申请

US20010026468A1 Electronic device and recording method using the same 失效
标题翻译：电子装置及使用其的记录方法
公开(公告)号：US20010026468A1
公开(公告)日：2001-10-04
申请号：US09801325
申请日：2001-03-07
申请人： NEC Corporation
发明人： Akio Tanikawa
IPC分类号： G11C011/21 , G11C013/02
CPC分类号： G11C13/025 , B82Y10/00 , G11C11/21 , G11C13/0011 , G11C2213/16 , H01L27/108 , H01L27/112 , H01L27/115 , H01L27/2463 , H01L29/8616 , H01L45/085 , H01L45/1206 , H01L45/1226 , H01L45/14 , Y10S977/744 , Y10S977/943
摘要： An electronic device of the present invention includes a memory core formed on an insulative substrate and implemented by a substance that performs, when a current flows therethrough, electromigration and varies in at least part of its shape or at least part of its element composition ratio. Two electrodes are directly bonded to opposite ends of the memory core. A sense electrode is spaced from the memory core by a thin insulative film in the vicinity of one of the two electrodes. A current flowing through the memory core causes a diffusion element to concentrate around either one of the two electrodes, whereby data is written in the memory core. Charge migration from the sense electrode caused by the migration of the diffusion element is sensed to thereby read the data out of the memory core.
摘要翻译：本发明的电子器件包括形成在绝缘衬底上并由电流实现的存储器芯，该物质在电流流经时进行电迁移，并在其形状的至少一部分或其元素组成比的至少一部分上变化。两个电极直接接合到存储器芯的相对端。感测电极通过在两个电极之一附近的薄绝缘膜与存储器芯间隔开。流过存储器芯的电流使得扩散元件集中在两个电极中的任一个上，从而将数据写入存储器芯中。感测由扩散元件的迁移引起的从感测电极的电荷迁移，从而从存储器芯中读出数据。

43. 发明授权

US6165851A Semiconductor nonvolatile storage and method of fabricating the same 失效
标题翻译：半导体非易失性存储器及其制造方法
公开(公告)号：US6165851A
公开(公告)日：2000-12-26
申请号：US328400
申请日：1999-06-09
申请人： Toshihiro Satoh
发明人： Toshihiro Satoh
IPC分类号： H01L21/28 , H01L29/861 , H01L21/8234
CPC分类号： H01L29/8616 , H01L21/28273
摘要： A semiconductor nonvolatile storage that is an inter-gate insulating film breakdown type memory is configured by providing a field oxide film on a semiconductor substrate 1, a gate electrode on the field oxide film and a mask oxide film on the surface of the gate electrode, forming an opening m the mask oxide film and forming a memory oxide film on the gate electrode exposed thereat, providing a memory gate electrode of a size extending from over the memory oxide film to over the mask oxide film, and making the thickness of the memory oxide film thinner than the thickness of the mask oxide film.
摘要翻译：作为栅极间绝缘膜击穿型存储器的半导体非易失性存储器通过在半导体基板1上设置场氧化膜，在场氧化膜上设置栅电极，在栅电极的表面设置掩模氧化膜，在掩模氧化膜上形成开口，并在其上露出的栅电极上形成记忆氧化膜，提供从存储氧化膜上方延伸到掩模氧化膜上方的尺寸的存储栅电极，并使存储器的厚度氧化膜比掩模氧化膜的厚度薄。

44. 发明授权

US4953928A MOS device for long-term learning 失效
标题翻译： MOS器件长期学习
公开(公告)号：US4953928A
公开(公告)日：1990-09-04
申请号：US363678
申请日：1989-06-09
申请人： Janeen D. W. Anderson , Carver A. Mead
发明人： Janeen D. W. Anderson , Carver A. Mead
IPC分类号： H01L29/788 , H01L29/861
CPC分类号： H01L29/7885 , H01L29/7887 , H01L29/8616
摘要： A semiconductor structure for long-term learning includes a p-type silicon substrate or well having first and second spaced apart n-type regions formed therein. A polysilicon floating gate is separated from the surface of the silicon substrate by a layer of gate oxide. One edge of the polysilicon floating gate is aligned with the edge of the first n-type region such that the polysilicon floating gate does not appreciably overly the n-type region. The second n-type region lies beyond the edge of the polysilicon floating gate. The first n-type region, the silicon substrate, and the second n-type region form the collector, base, and emitter, respectively, of a lateral bipolar transistor.An alternate embodiment of a semiconductor long-term learning structure includes an n-type silicon substrate having a p-well region formed therein. An n-type region is formed within the well region. A polysilicon floating gate is separated from the surface of the silicon substrate by a gate oxide and is positioned above the well region. One edge of the polysilicon floating gate is aligned with the edge of the n-type region within the well region such that the polysilicon floating gate does not appreciably overly the n-type region. The substrate, the well, and the n-type region, respectively, form the emitter, base, and collector of a bipolar transistor.
摘要翻译：用于长期学习的半导体结构包括在其中形成有第一和第二间隔开的n型区的p型硅衬底或阱。多晶硅浮栅通过一层栅极氧化物与硅衬底的表面分离。多晶硅浮动栅极的一个边缘与第一n型区域的边缘对准，使得多晶硅浮置栅极不明显地超过n型区域。第二n型区域位于多晶硅浮栅的边缘之上。第一n型区域，硅衬底和第二n型区域分别形成横向双极晶体管的集电极，基极和发射极。半导体长期学习结构的替代实施例包括其中形成有p阱区的n型硅衬底。在阱区内形成n型区域。多晶硅浮置栅极通过栅极氧化物与硅衬底的表面分离并且位于阱区域之上。多晶硅浮置栅极的一个边缘与阱区域内的n型区域的边缘对齐，使得多晶硅浮栅不明显地超过n型区域。衬底，阱和n型区域分别形成双极晶体管的发射极，基极和集电极。

45. 发明授权

US4432075A Electrically programmable non-volatile memory 失效
标题翻译：电可编程非易失性存储器
公开(公告)号：US4432075A
公开(公告)日：1984-02-14
申请号：US327474
申请日：1981-12-04
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： H01L27/112 , G11C16/04 , G11C16/30 , H01L21/8246 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L29/861 , G11C11/40
CPC分类号： G11C16/0416 , G11C16/30 , H01L29/7884 , H01L29/8616 , Y10S257/901
摘要： A memory array is disclosed which employs a plurality of floating gate EPROM or E.sup.2 PROM cells. Charge to program these cells is generated from charge generators, each shared by a plurality of cells. For example, one charge generator generates sufficient charge to allow selective programming of several hundred cells. The cells can be fabricated without the requirement to withstand high potentials, with less critical geometries and in some cases as two terminal devices.
摘要翻译：公开了一种采用多个浮栅EPROM或E2PROM单元的存储器阵列。对这些单元进行编程的电荷是从电荷发生器产生的，每个由多个单元共享。例如，一个充电发生器产生足够的电荷以允许对几百个电池的选择性编程。可以制造电池，而不需要承受高电位，具有较小关键几何形状，并且在某些情况下可以承受两个终端器件。

46. 发明授权

US4037243A Semi conductor memory cell utilizing sensing of variations in PN junction current conrolled by stored data 失效
标题翻译：半导体存储单元利用由存储数据控制的PN结电流变化的感测
公开(公告)号：US4037243A
公开(公告)日：1977-07-19
申请号：US716394
申请日：1976-08-23
申请人： Charles R. Hoffman , Michael W. Powell
发明人： Charles R. Hoffman , Michael W. Powell
IPC分类号： G11C11/34 , G11C11/39 , H01L27/07 , H01L27/10 , H01L29/861 , H01L29/78 , H01L27/02 , H01L29/34
CPC分类号： H01L27/105 , G11C11/34 , G11C11/39 , H01L27/0788 , H01L27/10 , H01L29/8616
摘要： Charge is stored on the gate of a gate controlled diode in a memory element to provide a junction breakdown memory cell. A quantity of charge representative of a logical 1 or a logical 0 may be dynamically stored in one embodiment. In another embodiment a composite silicon nitride/silicon dioxide dielectric is utilized to provide non-volatile storage of a logic state. Selection and sensing circuitry are coupled to an array of junction breakdown memory elements. Sensing circuitry detects the difference in reverse current of the gate controlled diode corresponding to a stored logical 1 and a stored logical 0, respectively.
摘要翻译：电荷存储在存储元件中的栅极控制二极管的栅极上以提供结击穿存储器单元。在一个实施例中，可以动态地存储表示逻辑1或逻辑0的电荷的数量。在另一个实施例中，复合氮化硅/二氧化硅电介质用于提供逻辑状态的非易失性存储。选择和感测电路耦合到结击穿存储元件的阵列。感测电路分别检测对应于存储的逻辑1和存储的逻辑0的门控二极管的反向电流的差异。

47. 发明授权

US4010482A Non-volatile Schottky barrier diode memory cell 失效
标题翻译：非挥发性肖特基二极管存储器单元
公开(公告)号：US4010482A
公开(公告)日：1977-03-01
申请号：US645767
申请日：1975-12-31
申请人： Shakir Ahmed Abbas , Narasipur Gundappa Anantha , Robert Charles Dockerty
发明人： Shakir Ahmed Abbas , Narasipur Gundappa Anantha , Robert Charles Dockerty
IPC分类号： H01L21/8247 , G11C11/36 , G11C16/04 , H01L27/07 , H01L27/102 , H01L29/51 , H01L29/788 , H01L29/792 , H01L29/861 , H01L29/872 , H01L29/94 , H01L29/48 , H01L29/56 , H01L29/64 , H01L29/78
CPC分类号： H01L27/0727 , G11C11/36 , G11C16/0466 , H01L27/1021 , H01L29/511 , H01L29/8616 , H01L29/872 , H01L29/94
摘要： A non-volatile memory cell that includes a Schottky barrier diode, located over a sub-diffused line or region formed within the substrate, acting as the control element. Information is stored in the device by introducing electrons into a nitride-oxide interface located at the perimeter of the Schottky barrier junction. Thus, the injected electrons are subject to trapping in the nitride-oxide layer, causing depletion in the epi region adjoining the diode interface, thereby influencing the current carrying state of the device.

48. 发明申请

US20150371987A1 Group III-V HEMT Having a Diode Controlled Substrate 审中-公开
标题翻译：具有二极管控制基板的III-V族HEMT
公开(公告)号：US20150371987A1
公开(公告)日：2015-12-24
申请号：US14728563
申请日：2015-06-02
申请人： International Rectifier Corporation
发明人： Yang Pan , Mohamed Imam
IPC分类号： H01L27/06 , H01L29/20 , H01L29/861 , H01L29/778
CPC分类号： H01L27/027 , H01L21/76898 , H01L21/8258 , H01L23/481 , H01L27/0248 , H01L27/0266 , H01L27/0617 , H01L27/0629 , H01L27/0694 , H01L27/0727 , H01L27/085 , H01L29/1075 , H01L29/2003 , H01L29/267 , H01L29/66666 , H01L29/7786 , H01L29/7827 , H01L29/8611 , H01L29/8616 , H01L2924/0002 , H03K17/063 , H03K17/6871 , H03K2017/6875 , H03K2217/0018 , H01L2924/00
摘要： There are disclosed herein various implementations of a group III-V high electron mobility transistor (HEMT) having a diode controlled substrate. Such a group III-V HEMT is situated over a substrate, and includes a diode having an anode provided by the substrate. The diode is configured to ground the substrate when the group III-V HEMT is in an off-state and to cause the substrate to float when the group III-V HEMT is in an on-state.
摘要翻译：在此公开了具有二极管控制的衬底的III-V族高电子迁移率晶体管（HEMT）的各种实现方式。这种III-V族HEMT位于衬底上，并且包括具有由衬底提供的阳极的二极管。当组III-V HEMT处于导通状态时，二极管被配置为使基板III-H HEMT处于断开状态并使衬底浮动。

49. 发明申请

US20150371986A1 Group III-V HEMT Having a Selectably Floating Substrate 有权
标题翻译：具有可选浮动基板的III-V族HEMT组
公开(公告)号：US20150371986A1
公开(公告)日：2015-12-24
申请号：US14728206
申请日：2015-06-02
申请人： International Rectifier Corporation
发明人： Yang Pan , Mohamed Imam
IPC分类号： H01L27/02 , H01L29/20 , H01L23/538 , H01L29/778 , H01L27/06
CPC分类号： H01L27/027 , H01L21/76898 , H01L21/8258 , H01L23/481 , H01L27/0248 , H01L27/0266 , H01L27/0617 , H01L27/0629 , H01L27/0694 , H01L27/0727 , H01L27/085 , H01L29/1075 , H01L29/2003 , H01L29/267 , H01L29/66666 , H01L29/7786 , H01L29/7827 , H01L29/8611 , H01L29/8616 , H01L2924/0002 , H03K17/063 , H03K17/6871 , H03K2017/6875 , H03K2217/0018 , H01L2924/00
摘要： There are disclosed herein various implementations of a group III-V high electron mobility transistor (HEMT) having a selectably floating substrate. Such a group III-V HEMT is situated over a substrate, and includes a transistor configured to selectably couple the substrate to ground and to selectably decouple the substrate from ground. The transistor is configured to ground the substrate when the group III-V HEMT is in an off-state and to cause the substrate to float when the group III-V HEMT is in an on-state.
摘要翻译：这里公开了具有可选择地浮置的衬底的III-V族高电子迁移率晶体管（HEMT）的各种实现。这种组III-V HEMT位于衬底上，并且包括被配置为可选地将衬底耦合到地并且可选择地将衬底与地分离的晶体管。当III-V族HEMT处于断开状态时，晶体管被配置为对衬底进行接地，并且当III-V族HEMT处于导通状态时，使衬底浮动。

50. 发明授权

US08907316B2 Memory cell access device having a pn-junction with polycrystalline and single crystal semiconductor regions 有权
标题翻译：具有与多晶和单晶半导体区域的pn结的存储单元访问装置
公开(公告)号：US08907316B2
公开(公告)日：2014-12-09
申请号：US12267453
申请日：2008-11-07
申请人： Hsiang-Lan Lung , Erh-Kun Lai , Yen-Hao Shih , Yi-Chou Chen , Shih-Hung Chen
发明人： Hsiang-Lan Lung , Erh-Kun Lai , Yen-Hao Shih , Yi-Chou Chen , Shih-Hung Chen
IPC分类号： H01L47/00 , H01L45/00 , H01L27/102 , H01L27/24 , H01L29/861 , H01L29/165 , H01L29/04 , G11C13/00
CPC分类号： H01L29/8616 , G11C13/0004 , G11C2213/72 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2472 , H01L29/04 , H01L29/165 , H01L29/861 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1675 , H01L45/1683
摘要： A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn-junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn-junction between the first and second regions.
摘要翻译：存储器件包括驱动器，其包括多层堆叠形式的pn结，其包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体区域，第一和第二掺杂半导体，其中限定其间的pn结，其中所述第一掺杂半导体区形成在单晶半导体中，并且所述第二掺杂半导体区包括多晶半导体。此外，制造存储器件的方法包括在半导体晶片上形成单晶半导体中的第一导电类型的第一掺杂半导体区域; 以及形成与所述第一导电类型相反的第二导电类型的第二掺杂多晶半导体区域，限定所述第一和第二区域之间的pn结。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式