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41. 发明授权

US08586993B2 Normally-off compound semiconductor tunnel transistor 有权
标题翻译：常规化合物半导体隧道晶体管
公开(公告)号：US08586993B2
公开(公告)日：2013-11-19
申请号：US13406568
申请日：2012-02-28
申请人： Gilberto Curatola , Oliver Häberlen
发明人： Gilberto Curatola , Oliver Häberlen
IPC分类号： H01L29/778
CPC分类号： H01L29/7788 , H01L21/0254 , H01L29/2003 , H01L29/267 , H01L29/401 , H01L29/66431 , H01L29/7391 , H01L29/7783 , H01L29/7786
摘要： Disclosed herein are embodiments of a normally-off compound semiconductor tunnel field effect transistor having a drive current above 100 mA per mm of gate length and a sub-threshold slope below 60 mV per decade at room temperature, and methods of manufacturing such a normally-off compound semiconductor tunnel transistor. The compound semiconductor tunnel field effect transistor is fast-switching and can be used for high voltage applications e.g. 30V up to 600V and higher.
摘要翻译：本文公开了常温化合物半导体隧道场效应晶体管的实施例，其具有每毫米栅极长度高于100mA的驱动电流和在室温下每十年低于60mV的次阈值斜率的制造方法，关闭复合半导体隧道晶体管。化合物半导体隧道场效应晶体管是快速切换的，并且可以用于高电压应用，例如 30V至600V及以上。

42. 发明授权

US08569831B2 Integrated circuit arrays and semiconductor constructions 有权
标题翻译：集成电路阵列和半导体结构
公开(公告)号：US08569831B2
公开(公告)日：2013-10-29
申请号：US13117408
申请日：2011-05-27
申请人： Lars P. Heineck , Shyam Surthi , Jaydip Guha
发明人： Lars P. Heineck , Shyam Surthi , Jaydip Guha
IPC分类号： H01L29/78
CPC分类号： H01L27/10802 , H01L21/28132 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L29/66666 , H01L29/7788 , H01L29/7827 , H01L29/7841
摘要： Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.
摘要翻译：一些实施例包括存储器阵列。存储器阵列可以在垂直取向的晶体管下面具有数字线，数字线将晶体管沿阵列的列互连。每个单独的晶体管可以直接在单个数字线上，单个数字线完全由一个或多个含金属材料组成。数字线可以在甲板上，电绝缘区域可以直接位于数字线和甲板之间。一些实施例包括形成存储器阵列的方法。可以形成多个含硅材料的线性段，以从含硅材料的基底向上延伸。基底可以被蚀刻以在线性段下面形成含硅基底，并且基脚可以被转换成金属硅化物。线性段可以被图案化成从金属硅化物基部向上延伸的多个垂直取向的晶体管基座。

43. 发明申请

US20130221434A1 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130221434A1
公开(公告)日：2013-08-29
申请号：US13884229
申请日：2011-10-05
申请人： Masaya Okada , Makoto Kiyama , Yu Saitoh , Seiji Yaegashi , Mitsunori Yokoyama , Kazutaka Inoue
发明人： Masaya Okada , Makoto Kiyama , Yu Saitoh , Seiji Yaegashi , Mitsunori Yokoyama , Kazutaka Inoue
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7827 , H01L29/2003 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/66462 , H01L29/66666 , H01L29/7788 , H01L29/7789
摘要： It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. The vertical semiconductor device includes a GaN-based stacked layer 15 having an opening 28 and the GaN-based stacked layer 15 includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. The vertical semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, and a gate electrode G located on the regrown layer. The gate electrode G covers a portion having a length corresponding to the thickness of the p-type GaN-based barrier layer and is terminated at a position on the wall surface, the position being away from the bottom portion of the opening.
摘要翻译：本发明的目的是提高具有开口的垂直半导体器件的击穿电压特性，并且在开口中包括由二维电子气形成的沟道。垂直半导体器件包括具有开口28的GaN基叠层15，GaN基叠层15包括n型GaN基漂移层4 / p型GaN基阻挡层6 / n型GaN- 垂直半导体器件包括覆盖开口的再生长层27，包含电子漂移层22和电子供给层26的再生长层27，源电极S和位于在再生长层上。栅电极G覆盖长度对应于p型GaN基阻挡层的厚度的部分，并且终止在壁表面上的位置，该位置远离开口的底部。

44. 发明授权

US08519438B2 Enhancement mode III-N HEMTs 有权
公开(公告)号：US08519438B2
公开(公告)日：2013-08-27
申请号：US12108449
申请日：2008-04-23
申请人： Umesh Mishra , Robert Coffie , Likun Shen , Ilan Ben-Yaacov , Primit Parikh
发明人： Umesh Mishra , Robert Coffie , Likun Shen , Ilan Ben-Yaacov , Primit Parikh
IPC分类号： H01L29/66
CPC分类号： H01L29/7784 , H01L21/0217 , H01L21/0254 , H01L29/0847 , H01L29/1033 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/365 , H01L29/4236 , H01L29/518 , H01L29/66431 , H01L29/66462 , H01L29/7783 , H01L29/7787 , H01L29/7788
摘要： A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

45. 发明申请

US20130181255A1 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130181255A1
公开(公告)日：2013-07-18
申请号：US13824043
申请日：2011-07-06
申请人： Makoto Kiyama , Yu Saitoh , Masaya Okada , Seiji Yaegashi , Kazutaka Inoue , Mitsunori Yokoyama
发明人： Makoto Kiyama , Yu Saitoh , Masaya Okada , Seiji Yaegashi , Kazutaka Inoue , Mitsunori Yokoyama
IPC分类号： H01L29/778 , H01L29/66
CPC分类号： H01L29/778 , H01L29/0696 , H01L29/155 , H01L29/2003 , H01L29/4236 , H01L29/66462 , H01L29/7788 , H01L29/7789
摘要： There is provided a vertical GaN-based semiconductor device in which the on-resistance can be decreased while the breakdown voltage characteristics are improved using a p-type GaN barrier layer. The semiconductor device includes a regrown layer 27 including a channel located on a wall surface of an opening 28, a p-type barrier layer 6 whose end face is covered, a source layer 7 that is in contact with the p-type barrier layer, a gate electrode G located on the regrown layer, and a source electrode S located around the opening. In the semiconductor device, the source layer has a superlattice structure that is constituted by a stacked layer including a first layer (a layer) having a lattice constant smaller than that of the p-type barrier layer and a second layer (b layer) having a lattice constant larger than that of the first layer.
摘要翻译：提供了一种垂直GaN基半导体器件，其中可以使用p型GaN势垒层改善导通电阻，同时提高击穿电压特性。半导体器件包括再生长层27，其包括位于开口28的壁表面上的沟道，其端面被覆盖的p型势垒层6，与p型势垒层接触的源极层7，位于再生长层上的栅电极G和位于开口周围的源电极S. 在半导体器件中，源极层具有超晶格结构，该超晶格结构由包括具有比p型势垒层的晶格常数小的晶格常数的第一层（层）的层叠层和具有比p型阻挡层的晶格常数小的第二层（b层）大于第一层的晶格常数。

46. 发明申请

US20130168739A1 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130168739A1
公开(公告)日：2013-07-04
申请号：US13824248
申请日：2011-07-06
申请人： Makoto Kiyama , Yu Saitoh , Masaya Okada , Masaki Ueno , Seiji Yaegashi , Kazutaka Inoue , Mitsunori Yokoyama
发明人： Makoto Kiyama , Yu Saitoh , Masaya Okada , Masaki Ueno , Seiji Yaegashi , Kazutaka Inoue , Mitsunori Yokoyama
IPC分类号： H01L29/778 , H01L29/66
CPC分类号： H01L29/778 , H01L29/2003 , H01L29/4236 , H01L29/66431 , H01L29/66462 , H01L29/7788 , H01L29/7789
摘要： A vertical semiconductor device in which pinch-off characteristics and breakdown voltage characteristics can be stably improved by fixing the electric potential of a p-type GaN barrier layer with certainty is provided. The semiconductor device includes a GaN-based stacked layer having an opening, a regrown layer including a channel located so as to cover a wall surface of the opening, an n+-type source layer that is in ohmic contact with the source electrode, a p-type GaN barrier layer, and a p+-type GaN-based supplementary layer located between the p-type GaN barrier layer and the n+-type source layer. The p+-type GaN-based supplementary layer and the n+-type source layer form a tunnel junction to fix the electric potential of the p-type GaN barrier layer at a source potential.
摘要翻译：提供了通过确定地固定p型GaN势垒层的电位可以稳定地提高夹断特性和击穿电压特性的垂直半导体器件。半导体器件包括具有开口的GaN基层叠层，包含覆盖开口壁面的沟道的再生长层，与源电极欧姆接触的n +型源极，p 位于p型GaN势垒层和n +型源极层之间的p +型GaN基辅助层。 p +型GaN基辅助层和n +型源极层形成隧道结，以将p型GaN阻挡层的电位固定在源极电位。

47. 发明申请

US20120299088A1 Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions 有权
标题翻译：存储阵列，半导体结构和形成半导体结构的方法
公开(公告)号：US20120299088A1
公开(公告)日：2012-11-29
申请号：US13117408
申请日：2011-05-27
申请人： Lars P. Heineck , Shyam Surthi , Jaydip Guha
发明人： Lars P. Heineck , Shyam Surthi , Jaydip Guha
IPC分类号： H01L29/78 , H01L21/22 , H01L21/336
CPC分类号： H01L27/10802 , H01L21/28132 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L29/66666 , H01L29/7788 , H01L29/7827 , H01L29/7841
摘要： Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.
摘要翻译：一些实施例包括存储器阵列。存储器阵列可以在垂直取向的晶体管下面具有数字线，数字线将晶体管沿阵列的列互连。每个单独的晶体管可以直接在单个数字线上，单个数字线完全由一个或多个含金属材料组成。数字线可以在甲板上，并且电绝缘区域可以直接位于数字线和甲板之间。一些实施例包括形成存储器阵列的方法。可以形成多个含硅材料的线性段，以从含硅材料的基底向上延伸。基底可以被蚀刻以在线性段下面形成含硅基底，并且基脚可以被转换成金属硅化物。线性段可以被图案化成从金属硅化物基部向上延伸的多个垂直取向的晶体管基座。

48. 发明申请

US20120225526A1 NANOWIRE AND LARGER GaN BASED HEMTS 有权
标题翻译： NANOWIRE和LARGER基于GaN的HEMTS
公开(公告)号：US20120225526A1
公开(公告)日：2012-09-06
申请号：US13461331
申请日：2012-05-01
申请人： Stephen D. Hersee , Xin Wang
发明人： Stephen D. Hersee , Xin Wang
IPC分类号： H01L21/335 , B82Y40/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/02389 , H01L21/02458 , H01L21/02513 , H01L21/0254 , H01L21/02603 , H01L21/0262 , H01L21/02639 , H01L21/8252 , H01L27/0605 , H01L29/2003 , H01L29/66462 , H01L29/7787 , H01L29/7788 , H01L29/7789
摘要： Nanowire and larger, post-based HEMTs, arrays of such HEMTs, and methods for their manufacture are provided. In one embodiment, a HEMT can include a III-N based core-shell structure including a core member (e.g., GaN), a shell member (e.g., AlGaN) surrounding a length of the core member and a two-dimensional electron gas (2-DEG) at the interface therebetween. The core member including a nanowire and/or a post can be disposed over a doped buffer layer and a gate material can be disposed around a portion of the shell member. Exemplary methods for making the nanowire HEMTs and arrays of nanowire HEMTs can include epitaxially forming nanowire(s) and epitaxially forming a shell member from each formed nanowire. Exemplary methods for making the post HEMTs and arrays of post HEMTs can include etching a III-N layer to form III-N post(s) followed by formation of the shell member(s).
摘要翻译：提供了纳米线和更大的后置HEMT，这样的HEMT的阵列及其制造方法。在一个实施例中，HEMT可以包括基于III-N的核 - 壳结构，其包括芯构件（例如，GaN），围绕芯构件的长度的壳构件（例如，AlGaN）和二维电子气 2-DEG）。包括纳米线和/或柱的芯构件可以设置在掺杂缓冲层上方，并且栅极材料可以围绕壳构件的一部分设置。用于制造纳米线HEMT和纳米线HEMT阵列的示例性方法可以包括外延形成纳米线并从每个形成的纳米线外延地形成壳部件。用于制造后HEMT和后HEMT阵列的示例性方法可以包括蚀刻III-N层以形成III-N柱，随后形成壳构件。

49. 发明申请

US20120208331A1 COMPOUND SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD 有权
标题翻译：复合半导体器件及其制造方法
公开(公告)号：US20120208331A1
公开(公告)日：2012-08-16
申请号：US13454349
申请日：2012-04-24
申请人： Toshihide KIKKAWA
发明人： Toshihide KIKKAWA
IPC分类号： H01L21/335
CPC分类号： H01L29/7783 , H01L29/0649 , H01L29/1029 , H01L29/2003 , H01L29/66462 , H01L29/7788
摘要： A vertical type GaN series field effect transistor having excellent pinch-off characteristics is provided. A compound semiconductor device includes a conductive semiconductor substrate, a drain electrode formed on a bottom surface of the conductive semiconductor substrate, a current blocking layer formed on a top surface of the conductive semiconductor substrate, made of high resistance compound semiconductor or insulator, and having openings, an active layer of compound semiconductor burying the openings and extending on an upper surface of the current blocking layer, a gate electrode formed above the openings and above the active layer, and a source electrode formed laterally spaced from the gate electrode and formed above the active layer.
摘要翻译：提供了具有优异的夹断特性的垂直型GaN系列场效应晶体管。化合物半导体器件包括导电半导体衬底，形成在导电半导体衬底的底表面上的漏电极，形成在导电半导体衬底的顶表面上的电流阻挡层，由高电阻化合物半导体或绝缘体制成，并具有开口，埋入开口并在电流阻挡层的上表面上延伸的化合物半导体的有源层，形成在开口上方和活性层上方的栅电极，以及与栅电极横向间隔开并形成在其上的源电极活动层。

50. 发明申请

US20120139008A1 COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：化合物半导体器件及其制造方法
公开(公告)号：US20120139008A1
公开(公告)日：2012-06-07
申请号：US13396899
申请日：2012-02-15
申请人： Tadahiro IMADA , Atsushi Yamada
发明人： Tadahiro IMADA , Atsushi Yamada
IPC分类号： H01L29/778 , H01L21/338
CPC分类号： H01L29/0619 , H01L29/0657 , H01L29/2003 , H01L29/34 , H01L29/518 , H01L29/66462 , H01L29/7787 , H01L29/7788 , H01L29/7832
摘要： An i-GaN layer (electron transit layer), an n-GaN layer (compound semiconductor layer) formed over the i-GaN layer (electron transit layer), and a source electrode, a drain electrode and a gate electrode formed over the n-GaN layer (compound semiconductor layer) are provided. A recess portion is formed inside an area between the source electrode and the drain electrode of the n-GaN layer (compound semiconductor layer) and at a portion separating from the gate electrode.
摘要翻译：在i-GaN层（电子传输层）上形成的i-GaN层（电子迁移层），n-GaN层（化合物半导体层）以及形成在n-GaN层上的源电极，漏电极和栅电极 -GaN层（化合物半导体层）。在n-GaN层（化合物半导体层）的源电极和漏电极之间的区域内以及与栅电极分离的部分的内部形成有凹部。

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