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41. 发明授权

US06225196B1 High electron mobility transistor and method of fabricating the same 失效
标题翻译：高电子迁移率晶体管及其制造方法
公开(公告)号：US06225196B1
公开(公告)日：2001-05-01
申请号：US09521781
申请日：2000-03-09
申请人： Takashi Yokoyama
发明人： Takashi Yokoyama
IPC分类号： H01L2120
CPC分类号： H01L29/66431 , H01L29/1604 , H01L29/7786
摘要： There is provided a field effect transistor including (a) an amorphous semiconductor layer made of amorphous silicon hydride containing impurities doped therein, (b) a semiconductor layer made of single crystal silicon having electron affinity greater than that of the amorphous silicon hydride, formed on the amorphous semiconductor layer, (c) a gate insulating film formed on the semiconductor layer, and (d) a gate electrode formed on the gate insulating film. The amorphous semiconductor layer and the semiconductor layer cooperate with each other to thereby form a potential well at a junction therebetween. The above mentioned field effect transistor utilizes a difference in electron affinity between the amorphous semiconductor layer and the semiconductor layer to thereby make it possible to operate at a higher speed because carriers are not influenced by scattering of doped ions. In addition, a structure of a single crystal silicon layer formed on an amorphous silicon layer, which would be difficult to fabricate by epitaxial growth, can be accomplished by means of ion implantation, and can be operated in accordance with the operation principle of an ordinary MOS transistor.
摘要翻译：提供了一种场效应晶体管，其包括（a）由非晶硅氢化物制成的非晶半导体层，其中掺杂有杂质，（b）由单晶硅制成的半导体层，其电子亲和力大于非晶硅氢化物的电子亲和力，形成在所述非晶半导体层，（c）形成在所述半导体层上的栅极绝缘膜，以及（d）形成在所述栅极绝缘膜上的栅电极。非晶半导体层和半导体层彼此配合，从而在它们之间的接合处形成势阱。上述场效应晶体管利用了非晶半导体层与半导体层之间的电子亲和力差，从而使得可以以更高的速度工作，因为载流子不受掺杂离子的散射的影响。此外，通过离子注入可以实现通过外延生长难以制造的在非晶硅层上形成的单晶硅层的结构，并且可以根据普通的操作原理来操作 MOS晶体管。

42. 发明授权

US5866930A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5866930A
公开(公告)日：1999-02-02
申请号：US697448
申请日：1996-08-23
申请人： Shigehiko Saida , Yoshio Ozawa
发明人： Shigehiko Saida , Yoshio Ozawa
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/16 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L21/28035 , H01L21/28273 , H01L27/105 , H01L27/11546 , H01L29/1604 , H01L29/42324 , H01L27/115
摘要： A semiconductor device comprises a first conducting layer, a first insulating layer formed on the first conducting layer, a second conducting layer formed on the first insulating layer and facing the first conducting layer, wherein, at least part of a peripheral portion of the region of at least one of the first and second conducting layers, in contact with the first insulating layer, includes an amorphous conducting layer made of a semiconductor, and the amorphous conducting layer contains at least one element selected from the group consisting of oxygen, nitrogen, carbon, argon, chlorine, and fluorine and a total concentration of the at least one element falls within the range from 0.1 atomic % to 20 atomic %.
摘要翻译：半导体器件包括第一导电层，形成在第一导电层上的第一绝缘层，形成在第一绝缘层上并面向第一导电层的第二导电层，其中，至少部分该区域的周边部分与第一绝缘层接触的第一和第二导电层中的至少一个包括由半导体制成的非晶导体层，并且非晶导体层含有选自氧，氮，碳的至少一种元素，氩，氯和氟，并且所述至少一种元素的总浓度在0.1原子％至20原子％的范围内。

43. 发明授权

US5831282A Method of producing an HSG structure using an amorphous silicon disorder layer as a substrate 失效
标题翻译：使用非晶硅无序层作为基材制造HSG结构的方法
公开(公告)号：US5831282A
公开(公告)日：1998-11-03
申请号：US926275
申请日：1997-09-05
申请人： Michael Nuttall
发明人： Michael Nuttall
IPC分类号： H01L21/02 , H01L29/16 , H01L29/04 , H01L31/036
CPC分类号： H01L28/84 , H01L29/16 , H01L29/1604
摘要： A method is provided for forming a hemispherical grain silicon structure on an integrated circuit semiconductor substrate in a processing reactor. The method includes the steps of forming a doped silicon layer upon the semiconductor substrate and forming an amorphous silicon layer upon the doped silicon layer. A hemispherical grain silicon layer is formed upon the amorphous silicon layer. The doped silicon layer is formed at a first deposition temperature and the amorphous silicon layer is formed at a second deposition temperature wherein the second deposition temperature is lower than the first deposition temperature. The first deposition temperature is, for example, in excess of approximately 590.degree. C. and is preferably approximately 625.degree. C. The second deposition temperature is less than approximately 560.degree. C. and is preferably approximately 555.degree. C. The various layers are deposited without removing the semiconductor substrate from the processing reactor. The depositions can be performed as a continuous deposition of silicon at varying temperatures. The doped polysilicon layer can be formed of doped polysilicon material or doped amorphous silicon and the amorphous silicon layer can be formed of an undoped material.
摘要翻译：提供了一种用于在处理反应器中在集成电路半导体衬底上形成半球形晶体硅结构的方法。该方法包括在半导体衬底上形成掺杂硅层并在掺杂硅层上形成非晶硅层的步骤。半非晶硅层形成在非晶硅层上。掺杂硅层在第一沉积温度下形成，并且非晶硅层在第二沉积温度下形成，其中第二沉积温度低于第一沉积温度。第一沉积温度例如超过约590℃，优选为约625℃。第二沉积温度小于约560℃，优选约555℃。各层沉积而不从处理反应器移除半导体衬底。沉积可以作为在不同温度下连续沉积硅来进行。掺杂多晶硅层可以由掺杂多晶硅材料或掺杂的非晶硅形成，并且非晶硅层可以由未掺杂的材料形成。

44. 发明授权

US4701572A Amorphous solar cell 失效
标题翻译：非晶太阳能电池
公开(公告)号：US4701572A
公开(公告)日：1987-10-20
申请号：US901131
申请日：1986-08-28
申请人： Kazuhiko Sato , Genshiro Nakamura , Takushi Itagaki
发明人： Kazuhiko Sato , Genshiro Nakamura , Takushi Itagaki
IPC分类号： H01L31/04 , H01L21/205 , H01L29/16 , H01L31/075 , H01L31/20 , H01L31/06 , H01L31/18
CPC分类号： H01L29/1604 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/0262 , H01L31/075 , H01L31/204 , Y02E10/548 , Y02P70/521
摘要： An amorphous solar cell including an amorphous SiGe film which is produced by a glow discharge method using a mixed gas obtained by mixing Si.sub.2 H.sub.6 and GeH.sub.4 or obtained by diluting Si.sub.2 H.sub.6 and GeH.sub.4 with a predetermined dilution gas such that the ratio of GeH.sub.4 to (Si.sub.2 H.sub.6 +GeH.sub.4) is 0.1 to 0.4.
摘要翻译：一种非晶体太阳能电池，其特征在于，使用通过混合Si 2 H 6和GeH 4而得到的混合气体，通过用规定的稀释气体稀释Si 2 H 6和GeH 4而得到的混合气体，通过辉光放电法，使GeH 4与（Si 2 H 6 + GeH4）为0.1〜0.4。

45. 发明申请

US20180226254A1 Systems and Methods for Bidirectional Device Fabrication 审中-公开
公开(公告)号：US20180226254A1
公开(公告)日：2018-08-09
申请号：US15794418
申请日：2017-10-26
申请人： Ideal Power Inc.
发明人： Richard A. Blanchard , William C. Alexander
IPC分类号： H01L21/265 , H03K17/66 , H01L29/08 , H01L21/225 , H01L21/283 , H01L29/739 , H01L29/737 , H01L29/732 , H01L29/66 , H01L29/16 , H01L21/18 , H01L29/06 , H01L21/78 , H01L21/683 , H01L21/324 , H01L21/306 , H01L21/304 , H01L29/423
CPC分类号： H01L21/265 , H01L21/187 , H01L21/2252 , H01L21/283 , H01L21/304 , H01L21/30625 , H01L21/324 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L29/0619 , H01L29/0821 , H01L29/1604 , H01L29/4236 , H01L29/66348 , H01L29/732 , H01L29/7375 , H01L29/7397 , H01L2221/68304 , H01L2221/68327 , H03K17/66
摘要： Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.

46. 发明申请

US20180197960A1 TFT array substrate, manufacturing method thereof, and liquid crystal display apparatus 审中-公开
公开(公告)号：US20180197960A1
公开(公告)日：2018-07-12
申请号：US15123776
申请日：2016-07-20
申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd.
发明人： Xiaowen LV
IPC分类号： H01L29/417 , H01L27/12 , H01L29/16 , H01L29/786 , H01L29/24 , G02F1/1368 , H01L29/66
CPC分类号： H01L29/41733 , G02F1/1368 , G02F2202/10 , G02F2202/103 , H01L21/77 , H01L27/12 , H01L27/1222 , H01L27/1225 , H01L27/127 , H01L29/1604 , H01L29/24 , H01L29/66765 , H01L29/66969 , H01L29/78618 , H01L29/78669 , H01L29/7869 , H01L29/78696
摘要： The present disclosure discloses a TFT array substrate, a manufacturing method thereof and a liquid crystal display apparatus. The TFT array substrate comprising: a substrate; and a TFT disposed on the substrate; the TFT comprises a semiconductor layer and both a source electrode and a drain electrode disposed on the semiconductor layer, and wherein a contact surface between the semiconductor layer and the source electrode and/or a contact surface between the semiconductor layer and the drain electrode are uneven structure. Through above manner, the present disclosure can reduce contact resistance between the semiconductor layer and the metal layer and can improve electrical characteristic of TFT apparatus.

47. 发明授权

US10008511B2 Dense arrays and charge storage devices 有权
公开(公告)号：US10008511B2
公开(公告)日：2018-06-26
申请号：US15368396
申请日：2016-12-02
申请人： SANDISK TECHNOLOGIES LLC
发明人： Thomas H. Lee
IPC分类号： H01L27/11582 , G11C16/34 , H01L21/822 , H01L27/06 , H01L27/112 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11556 , H01L27/11568 , H01L27/11578 , H01L29/423 , H01L29/66 , H01L29/788 , H01L29/792 , H01L29/861 , H01L27/11558 , H01L27/11526 , H01L27/11573 , H01L29/16 , G11C16/10 , G11C16/14 , G11C16/26 , H01L29/06 , H01L29/51 , G11C16/04 , H01L21/3105 , H01L21/768 , H01L23/528 , H01L23/532 , H01L27/11565 , H01L29/739 , H01L29/786 , H01L27/12 , H01L27/1158
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

48. 发明授权

US09972692B2 Integrated circuit device and method of manufacturing the same 有权
公开(公告)号：US09972692B2
公开(公告)日：2018-05-15
申请号：US14994167
申请日：2016-01-13
申请人： Jung-Hun Choi , Da-Il Eom , Sun-Jung Lee , Sung-Uk Jang
发明人： Jung-Hun Choi , Da-Il Eom , Sun-Jung Lee , Sung-Uk Jang
IPC分类号： H01L29/417 , H01L27/092 , H01L29/08 , H01L29/16 , H01L29/165 , H01L21/8238 , H01L21/768 , H01L21/8234 , H01L23/485 , H01L29/78
CPC分类号： H01L29/41791 , H01L21/76805 , H01L21/76846 , H01L21/823418 , H01L21/823425 , H01L21/823431 , H01L21/823475 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L27/0924 , H01L29/0847 , H01L29/1604 , H01L29/165 , H01L29/41783 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L2029/7858
摘要： An integrated circuit device includes a source/drain region having a recess in its top, a contact plug extending on the source/drain region from within the recess, and a metal silicide layer lining the recess and having a first portion covering a bottom of the contact plug and a second portion that is integral with the first portion and covers a lower part of sides of the contact plug. The second portion of the silicide layer may have a thickness different from a thickness of the first portion of the silicide layer. The silicide layer is formed at a relatively low temperature to offer an improved resistance characteristic as between the source/drain region and the contact plug.

49. 发明申请

US20180122953A1 LAMINATE STRUCTURE OF THIN FILM TRANSISTOR 有权
公开(公告)号：US20180122953A1
公开(公告)日：2018-05-03
申请号：US15445989
申请日：2017-03-01
申请人： Microcosm Technology Co., Ltd.
发明人： Po-Tsun Liu , Sung-Wei Hung , Bo-Hung Lai
IPC分类号： H01L29/786 , H01L27/12 , H01L23/31 , H01L23/29 , H01L29/49 , H01L29/51 , H01L29/24 , H01L29/16 , C08G73/22
CPC分类号： H01L29/78606 , C08G73/22 , H01L23/293 , H01L23/3171 , H01L27/1222 , H01L27/1225 , H01L29/1604 , H01L29/24 , H01L29/247 , H01L29/4908 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/78669 , H01L29/7869 , H01L29/78693
摘要： A laminate structure of a thin film transistor includes a thin film transistor array and a passivation layer. The thin film transistor array includes a gate, a channel layer formed on the gate, a gate insulating layer forming between the gate and the channel layer, and a source and a drain forming on both sides of the channel layer. The passivation layer is formed on the thin film transistor array, and the passivation layer has at least one contact hole exposing the source or the drain, wherein the passivation layer is an oxazole-containing photosensitive polyimide (PSPI) resin.

50. 发明申请

US20180083134A1 BULK TO SILICON ON INSULATOR DEVICE 审中-公开
公开(公告)号：US20180083134A1
公开(公告)日：2018-03-22
申请号：US15819306
申请日：2017-11-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Terence B. Hook , Joshua M. Rubin , Tenko Yamashita
IPC分类号： H01L29/78 , H01L21/84 , H01L29/08 , H01L27/12 , H01L29/06
CPC分类号： H01L29/0649 , H01L21/02642 , H01L21/76254 , H01L21/76256 , H01L21/76283 , H01L21/845 , H01L27/1211 , H01L29/0684 , H01L29/0847 , H01L29/1037 , H01L29/1604 , H01L29/1608 , H01L29/161 , H01L29/4966 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.

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