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41. 发明申请

US20070214203A1 Dividing method and apparatus 审中-公开
标题翻译：划分方法和装置
公开(公告)号：US20070214203A1
公开(公告)日：2007-09-13
申请号：US11707618
申请日：2007-02-16
申请人： Hyeong-Seok Yu , Jae-Kon Lee , Chang-Woo Seo , Hyun-Il Kang
发明人： Hyeong-Seok Yu , Jae-Kon Lee , Chang-Woo Seo , Hyun-Il Kang
IPC分类号： G06F17/14
CPC分类号： G06F7/535 , G06F7/5446
摘要： A dividing apparatus and method using coordinate rotation is disclosed. To this end, a plurality of rotation stages are sequentially performed until a divisor reaches a criterion and a rotation direction used in each of the plurality of stages is output. A division result acquired by performing rotation with respect to a dividend using the rotation direction for each of the plurality of stages is output.
摘要翻译：公开了一种使用坐标旋转的分割装置和方法。为此，顺序执行多个旋转台，直到除数达到标准，并且输出在多个级中的每一个中使用的旋转方向。输出通过使用针对多个级中的每一个的旋转方向执行关于分红的旋转获得的分割结果。

42. 发明授权

US07251673B2 Method for performing integer divisions 有权
标题翻译：执行整数除法的方法
公开(公告)号：US07251673B2
公开(公告)日：2007-07-31
申请号：US10400811
申请日：2003-03-27
申请人： William Orlando , Sophie Gabriele
发明人： William Orlando , Sophie Gabriele
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F2207/5354
摘要： A method of automatic calculation of several integer divisions by a same integer divider, of several successive integer dividends, separated from one another by a constant iteration step, smaller than or equal to the divider, including selecting, from a table of increments, according to an iteration index, a 0 or a 1 to be added to the operation result of the preceding iteration, the number of 0s in the table of increments being equal to the divider minus 1.
摘要翻译：一种通过相同的整数分频器自动计算几个整数除法的方法，该整数除数器通过恒定迭代步骤彼此分开的几个连续的整数除数，小于或等于分频器，包括从增量表中选择根据迭代索引，0或1被添加到前一次迭代的操作结果中，增量表中的0的数目等于分频器减1。

43. 发明申请

US20070083586A1 System and method for optimized reciprocal operations 审中-公开
标题翻译：用于优化互惠操作的系统和方法
公开(公告)号：US20070083586A1
公开(公告)日：2007-04-12
申请号：US11249655
申请日：2005-10-12
申请人： Jianjun Luo , David Chin
发明人： Jianjun Luo , David Chin
IPC分类号： H04L9/30 , G06F7/38 , H04L9/00 , H04K1/00
CPC分类号： G06F7/535 , G06F7/49942 , G06F7/721 , G06F2207/5355 , G06F2207/5356 , H04L9/302 , H04L2209/125 , H04L2209/20
摘要： A method and apparatus for calculating a reciprocal of an integer using a modified Newton Raphson method using one's complements instead of two's complements. The method includes determining a required precision; determining a number of iterations T responsive to the required precision; normalizing N into d; obtaining initial approximation of 1/d=R[0]; refining reciprocal approximation by the modified Newton Raphson operation using ones complements; truncating final iteration result R[T] responsive to the required precision; denormalizing R[T]; and outputting the reciprocal R.
摘要翻译：一种使用改进的牛顿拉夫逊方法来计算整数的倒数的方法和装置，其使用补全而不是二的补码。该方法包括确定所需精度; 确定响应所需精度的迭代次数T; 将N归一化为d; 获得1 / d = R [0]的初始近似值; 通过修正的牛顿拉夫逊运算，使用补码来提炼相互近似; 截断最终迭代结果R [T]响应所需精度; 非正规化R [T]; 并输出倒数R.

44. 发明授权

US07174357B2 Circuitry for carrying out division and/or square root operations requiring a plurality of iterations 有权
标题翻译：用于执行需要多次迭代的划分和/或平方根操作的电路
公开(公告)号：US07174357B2
公开(公告)日：2007-02-06
申请号：US10291850
申请日：2002-11-08
申请人： Tariq Kurd
发明人： Tariq Kurd
IPC分类号： G06F7/52 , G06F7/38
CPC分类号： G06F7/535 , G06F7/483 , G06F7/4873 , G06F7/5375 , G06F7/5525 , G06F2207/5528
摘要： Circuitry for carrying out an arithmetic operation requiring a plurality of iterations, such as division or square root operations, utilizes N sets of iteration circuitry arranged one after the other so that at least one of the sets of iteration circuitry receives an output from a preceding one of the sets of iteration circuitry. Each of the sets of iteration circuitry includes at least one adder part, wherein a full adder is provided by at least one part in one of the sets of iteration circuitry and a second part in a succeeding one of the sets of iteration circuitry.
摘要翻译：用于执行需要多次迭代（诸如除法或平方根操作）的算术运算的电路利用一个接一个地布置的N组迭代电路，使得迭代电路组中的至少一个接收来自前一个的输出的迭代电路组。迭代电路集合中的每一个包括至少一个加法器部分，其中全加器由迭代电路组之一中的至少一个部分提供，并且迭代电路组中的后一组中的第二部分。

45. 发明授权

US07167891B2 Narrow data path for very high radix division 失效
标题翻译：狭窄的数据路径，用于非常高的基数
公开(公告)号：US07167891B2
公开(公告)日：2007-01-23
申请号：US10394952
申请日：2003-03-21
申请人： Ping T. Tang , Warren E. Ferguson
发明人： Ping T. Tang , Warren E. Ferguson
IPC分类号： G06F7/535
CPC分类号： G06F7/535
摘要： Methods, machines, and systems are provided for very high radix division using narrow data paths. A numerator and denominator are received for a very high radix division calculation. An approximate reciprocal of the denominator is obtained from a data structure. The numerator and denominator are pre-scaled by the reciprocal. The denominator is decomposed to an equivalent expression that results in a number of leading insignificant values. Next, modifying a current remainder by forming a first product and subtracting the equivalent expression iteratively assembles a quotient.
摘要翻译：提供了使用窄数据路径进行非常高的基数分割的方法，机器和系统。接收到一个非常高的基数分数计算的分子和分母。从数据结构获得分母的近似倒数。分子和分母通过倒数进行预缩放。分母被分解成等效的表达式，导致许多领先的无关紧要的值。接下来，通过形成第一乘积来修改当前的余数并减去等价表达式迭代地组合商。

46. 发明授权

US07155472B2 Fixed-point quantizer for video coding 有权
标题翻译：用于视频编码的定点量化器
公开(公告)号：US07155472B2
公开(公告)日：2006-12-26
申请号：US10364636
申请日：2003-02-11
申请人： Ngai-Man Cheung , Ho-Cheon Wey , Yuji Itoh
发明人： Ngai-Man Cheung , Ho-Cheon Wey , Yuji Itoh
IPC分类号： G06F7/38
CPC分类号： G06F7/535 , G06F7/49947 , G06F2207/5356 , G06T9/005
摘要： A quantizer employs a scaled integral inverse ratio division for quantization of an input T by a quantization step Q. The quantizer forms an integral approximation q of 2r/Q by either trunc(2r/Q) or round(2r/Q). A multiplier multiplies the absolute value of T by the q. An adjustment factor is added alternatively to the absolute value of T prior to multiplication or to the product after multiplication. This adjustment factor minimizes errors near transition points in the quantization. This invention is applicable to both trunc(T/Q) and round(T/Q).
摘要翻译：量化器采用缩放的积分逆比除法，用于通过量化步长Q对输入T进行量化。量化器通过trunc（2＆lt; r＆lt; / SUP> / Q）或圆（2 / Q）。乘数将T的绝对值乘以q。调整因子与乘法前的T的绝对值或乘法后的乘积相加。该调整因子使量化中的转变点附近的误差最小化。本发明适用于trunc（T / Q）和round（T / Q）。

47. 发明授权

US07093105B2 Method and apparatus for determining availability of a queue to which a program step is issued out of program order 有权
标题翻译：用于确定从程序顺序发出程序步骤的队列的可用性的方法和装置
公开(公告)号：US07093105B2
公开(公告)日：2006-08-15
申请号：US10779503
申请日：2004-02-13
申请人： David Arthur James Webb, Jr. , James Keller , Derrick R. Meyer
发明人： David Arthur James Webb, Jr. , James Keller , Derrick R. Meyer
IPC分类号： G06F9/30
CPC分类号： G06F7/76 , G06F7/4824 , G06F7/508 , G06F7/535 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F2207/5352
摘要： A method and apparatus to allow program steps in an issue queue to be sent to the execution queue in a non program order provides reduced stall by allowing out of program order steps to be executed as needed resources become available. The method uses a modulus operation to preassign locations in the execution queues, and keep the entries in proper program order. The method employs an additional bit to represent the modules result (value) and may also utilize a load store number mapping memory to increase execution speed. With such an arrangement a computer system may decrease the lost performance due to waiting for required resource (i.e., memory or bus) availability for the current instruction, by issuing instructions for which the memory or bus resource is available even though the instruction is not the next one in the original program order. Thus the present invention allows memory reference instructions to issue as resources are available.
摘要翻译：允许以非程序顺序将发布队列中的程序步骤发送到执行队列的方法和装置通过允许在需要的资源变得可用时执行程序顺序步骤来减少停止。该方法使用模数运算来对执行队列中的位置进行预分配，并使条目保持正确的程序顺序。该方法使用附加位来表示模块结果（值），并且还可以利用加载存储器号映射存储器来增加执行速度。通过这样的布置，由于等待当前指令的所需资源（即，存储器或总线）可用性，计算机系统可以通过发出存储器或总线资源可用的指令来减少丢失的性能，即使该指令不是下一个在原程序中。因此，本发明允许存储器参考指令在资源可用时发布。

48. 发明申请

US20060095494A1 Method and apparatus for efficient software-based integer division 审中-公开
标题翻译：高效的基于软件的整数除法的方法和装置
公开(公告)号：US20060095494A1
公开(公告)日：2006-05-04
申请号：US10975319
申请日：2004-10-28
申请人： Alok Kumar
发明人： Alok Kumar
IPC分类号： G06F7/38
CPC分类号： G06F7/535 , G06F2207/5356
摘要： A method and apparatus to perform efficient software-based integer division. The equivalent of a hardware-based integer division operation is enabled via a reciprocal multiplication operation that is facilitated by a minimum combination of multiplication (and/or add) and shift operations. Properties and equations are derived for determining minimum multiplication and shift instructions to perform an integer division of a variable dividend and constant divisor using reciprocal multiplication. Computer functions are disclosed for determining parameters from which the minimum multiplication and shift instructions can be derived. Software/firmware is then coded employing the minimum multiplication and shift instructions to perform software-based integer division operations via reciprocal multiplication. In one embodiment, the integer division operations are employed to determine a minimum number of cells required to store the data in a packet or frame that is processed by a network processor.
摘要翻译：一种执行高效的基于软件的整数除法的方法和装置。相当于基于硬件的整数除法运算通过相乘乘法运算来实现，该乘法运算由乘法（和/或加法）和移位运算的最小组合促成。导出属性和方程，用于确定最小乘法和移位指令，以使用相乘乘法执行可变除数和常数除数的整数除法。公开了计算机功能，用于确定可以从其导出最小乘法和移位指令的参数。然后使用最小乘法和移位指令对软件/固件进行编码，以通过相互乘法执行基于软件的整数除法运算。在一个实施例中，采用整数除法运算来确定将数据存储在由网络处理器处理的分组或帧中所需的最小单元数。

49. 发明申请

US20050278407A1 Addressing type of asynchronous divider 审中-公开
标题翻译：寻址类型的异步分频器
公开(公告)号：US20050278407A1
公开(公告)日：2005-12-15
申请号：US11139647
申请日：2005-05-31
申请人： Di Tang
发明人： Di Tang
IPC分类号： G06F7/52 , G06F7/535 , G06F7/57
CPC分类号： G06F7/57 , G06F7/535 , G06F2207/3864
摘要： The present invention relates to an addressing type of asynchronous divider that uses addressing system, which enables an external circuit to receive a divisor and a dividend. Through the process of addressing type of asynchronous divider, the calculated quotient and remainder are transferred to the external circuit using addressing system. The addressing system of transferring can effectively make use of a memory and economize the design of a circuit, which can enhance the integration of a circuit.
摘要翻译：本发明涉及使用寻址系统的寻址类型的异步分频器，其使得外部电路能够接收除数和除数。通过寻址异步分频器的过程，计算的商和余数将使用寻址系统传送到外部电路。传输寻址系统可以有效利用存储器，节省电路设计，从而提高电路的集成度。

50. 发明申请

US20050216543A1 Reverse division process 有权
标题翻译：逆分割过程
公开(公告)号：US20050216543A1
公开(公告)日：2005-09-29
申请号：US10809998
申请日：2004-03-26
申请人： Pierre Laurent
发明人： Pierre Laurent
IPC分类号： G06F7/44 , G06F7/535
CPC分类号： G06F7/535
摘要： Described herein is a method that includes storing partial quotients of a continued fraction in a first set of counters, initializing a second sets of counters with counter values, decrementing a target counter in the second set of counters to obtain a decremented counter value, and outputting a value that corresponds to a partial quotient in a first counter in the first set of counters. The value is based on the decremented counter value.
摘要翻译：这里描述了一种方法，包括在第一组计数器中存储连续分数的部分商，用计数器值初始化第二组计数器，递减第二组计数器中的目标计数器以获得递减的计数器值，并输出对应于第一组计数器中的第一计数器中的部分商的值。该值基于递减的计数器值。

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