专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US08312218B2 Cache controller and cache control method 有权
标题翻译：缓存控制器和缓存控制方法
公开(公告)号：US08312218B2
公开(公告)日：2012-11-13
申请号：US12230244
申请日：2008-08-26
申请人： Masaki Ukai
发明人： Masaki Ukai
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0844 , G06F12/0857 , G06F12/0859 , G06F2212/1016 , G06F2212/1056
摘要： A cache controller that writes data to a cache memory, includes a first buffer unit that retains data flowing in via an external bus, a second buffer unit that retrieves a piece of the data to be written to the cache memory, and a write controlling unit that controls writing of the piece of the data retrieved by the second buffer unit to the cache memory.
摘要翻译：一种将数据写入高速缓冲存储器的高速缓存控制器，包括保持经由外部总线流入的数据的第一缓冲单元，检索要写入高速缓冲存储器的一段数据的第二缓冲单元，以及写入控制单元其控制将由第二缓冲单元检索的数据片段写入缓存存储器。

42. 发明申请

US20120198205A1 TRANSACTIONAL MEMORY 有权
标题翻译：交易记忆
公开(公告)号：US20120198205A1
公开(公告)日：2012-08-02
申请号：US13015396
申请日：2011-01-27
申请人： Sean Eilert
发明人： Sean Eilert
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F11/1456 , G06F11/302 , G06F11/3037 , G06F11/3055 , G06F2212/1056 , G06F2212/206 , G06F2212/261
摘要： Subject matter disclosed herein relates to techniques to perform transactions using a memory device.
摘要翻译：本文公开的主题涉及使用存储器件执行事务的技术。

43. 发明授权

US08219988B2 Partition adjunct for data processing system 有权
标题翻译：分区辅助数据处理系统
公开(公告)号：US08219988B2
公开(公告)日：2012-07-10
申请号：US12110923
申请日：2008-04-28
申请人： William J. Armstrong , Orran Y. Krieger , Michal Ostrowski , Randal C. Swanberg
发明人： William J. Armstrong , Orran Y. Krieger , Michal Ostrowski , Randal C. Swanberg
IPC分类号： G06F9/455 , G06F12/00 , G06F13/00 , G06F13/28 , G06F9/46
CPC分类号： G06F12/1475 , G06F9/45558 , G06F12/1491 , G06F2009/45579 , G06F2212/1056
摘要： A partition adjunct is provided for a logical partition running above a hypervisor of a data processing system. The partition adjunct, which is a separate dispatchable partition from an instantiating logical partition, provides one or more services to the logical partition. A service request received from the logical partition is processed by the partition adjunct utilizing virtual address space donated to the partition adjunct from the logical partition. The partition adjunct and the logical partition share a common virtual address to real address page table, and context switching the current state machine from the logical partition to the partition adjunct occurs without invalidating or modifying state data of selected memory management and address translation hardware of the data processing system. In a hardware multithreaded system, the partition adjunct is dispatched on a single thread, while another thread continues to run in the logical partition initiating the service request.
摘要翻译：为在数据处理系统的管理程序之上运行的逻辑分区提供分区附件。分区附件是与实例化逻辑分区相分离的可分派分区，为逻辑分区提供一个或多个服务。从逻辑分区接收到的服务请求由分区附件利用从逻辑分区捐赠给分区附件的虚拟地址空间来处理。分区附件和逻辑分区将共同的虚拟地址共享到实际地址页表，并且将当前状态机从逻辑分区切换到分区附件，而不会使所选择的存储器管理和地址转换硬件的状态数据无效或修改数据处理系统。在硬件多线程系统中，分区附件在单个线程上调度，而另一个线程继续在启动服务请求的逻辑分区中运行。

44. 发明授权

US08010763B2 Hypervisor-enforced isolation of entities within a single logical partition's virtual address space 有权
标题翻译：管理程序强制隔离单个逻辑分区的虚拟地址空间内的实体
公开(公告)号：US08010763B2
公开(公告)日：2011-08-30
申请号：US12111041
申请日：2008-04-28
申请人： William J. Armstrong , Orran Y. Krieger , Cathy May , Michal Ostrowski , Randal C. Swanberg
发明人： William J. Armstrong , Orran Y. Krieger , Cathy May , Michal Ostrowski , Randal C. Swanberg
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/455
CPC分类号： G06F12/1475 , G06F9/45558 , G06F12/1491 , G06F2009/45583 , G06F2009/45587 , G06F2212/1056
摘要： Access control to shared virtual address space within a single logical partition is provided. The access control includes: associating, by a hypervisor of the data processing system, a memory protection key with a portion of a single logical partition's virtual address space being shared by multiple entities, the key preventing access by one of the multiple entities to that portion of the virtual address space, and allowing access by another of the entities to that portion of the virtual address space; and locking by the hypervisor the memory protection key from modification by the one entity, wherein the locking prevents the one entity from modifying the key and thereby gaining access to the portion of the single logical partition's virtual address space with the associated memory protection key. In one embodiment, the one entity is the single logical partition itself, and the another entity is a partition adjunct.
摘要翻译：提供对单个逻辑分区内的共享虚拟地址空间的访问控制。访问控制包括：通过数据处理系统的管理程序将存储器保护密钥与多个实体共享的单个逻辑分区的虚拟地址空间的一部分相关联，该密钥阻止多个实体之一对该部分的访问的虚拟地址空间，并允许另一个实体访问该虚拟地址空间的该部分; 以及由所述管理程序锁定所述存储器保护密钥以免由所述一个实体修改，其中所述锁定防止所述一个实体修改所述密钥，从而利用所述相关联的存储器保护密钥访问所述单个逻辑分区的虚拟地址空间的所述部分。在一个实施例中，一个实体是单个逻辑分区本身，另一实体是分区附件。

45. 发明授权

US07913193B2 Determining relative amount of usage of data retaining device based on potential of charge storing device 有权
标题翻译：基于电荷存储装置的潜力确定数据保存装置的相对使用量
公开(公告)号：US07913193B2
公开(公告)日：2011-03-22
申请号：US11924935
申请日：2007-10-26
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G06F17/50
CPC分类号： G06F12/121 , G06F2212/1056 , G11C7/1006
摘要： An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a charge storing device coupled to the data retaining device such that a use of the data retaining device triggers a charging of the charge storing device by a charge source; and means for measuring a potential of the charge storing device, the measuring means being communicatively coupled to a calculating mean which determines a relative amount of usage of the data retaining device based on the measured potential.
摘要翻译：公开了集成电路和设计结构。集成电路可以包括：数据保持装置; 电荷存储装置，其耦合到数据保持装置，使得数据保持装置的使用触发电荷源对电荷存储装置的充电; 以及用于测量电荷存储装置的电位的装置，所述测量装置通信地耦合到基于所测量的电位确定数据保持装置的相对使用量的计算平均值。

46. 发明申请

US20100064107A1 MICROPROCESSOR CACHE LINE EVICT ARRAY 有权
公开(公告)号：US20100064107A1
公开(公告)日：2010-03-11
申请号：US12207261
申请日：2008-09-09
申请人： Colin Eddy , Rodney E. Hooker
发明人： Colin Eddy , Rodney E. Hooker
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0804 , G06F12/0831 , G06F12/0859 , G06F2212/1056
摘要： An apparatus for ensuring data coherency within a cache memory hierarchy of a microprocessor during an eviction of a cache line from a lower-level memory to a higher-level memory in the hierarchy includes an eviction engine and an array of storage elements. The eviction engine is configured to move the cache line from the lower-level memory to the higher-level memory. The array of storage elements are coupled to the eviction engine. Each storage element is configured to store an indication for a corresponding cache line stored in the lower-level memory. The indication indicates whether or not the eviction engine is currently moving the cache line from the lower-level memory to the higher-level memory.
摘要翻译：一种用于确保在从低级存储器到层级级的高级存储器的高速缓存线的驱逐期间在微处理器的高速缓冲存储器层级内的数据一致性的装置包括驱逐引擎和存储元件阵列。驱逐引擎被配置为将高速缓存行从低级存储器移动到更高级别的存储器。存储元件的阵列耦合到驱逐引擎。每个存储元件被配置为存储存储在下级存储器中的相应高速缓存行的指示。该指示表示驱逐引擎当前是否将高速缓存行从低级存储器移动到较高级存储器。

47. 发明授权

US12079498B2 Allowing access to a partially replicated dataset 有权
公开(公告)号：US12079498B2
公开(公告)日：2024-09-03
申请号：US17823968
申请日：2022-09-01
申请人： PURE STORAGE, INC.
发明人： Ethan L. Miller , John Colgrove , Christopher Golden , Steve Hodgson , Malcolm Sharpe
IPC分类号： G06F12/00 , G06F3/06 , G06F11/20 , G06F12/02 , G06F12/1009
CPC分类号： G06F3/064 , G06F3/0604 , G06F3/065 , G06F3/0683 , G06F3/0688 , G06F11/2094 , G06F12/0246 , G06F12/1009 , G06F2212/1056 , G06F2212/214 , G06F2212/7201
摘要： A system, apparatus, and product for allowing access to a partially replicated dataset, including: detecting, by a target storage system, that a dataset will be replicated from a source storage system to the target storage system; exposing, by the target storage system, the dataset for user operations prior to receiving the entire dataset; receiving, by the target storage system, a request to read a portion of the dataset that has not been received by the target storage system; and retrieving, by the target storage system, the portion of the dataset.

48. 发明授权

US12050914B2 Cache management operations using streaming engine 有权
公开(公告)号：US12050914B2
公开(公告)日：2024-07-30
申请号：US17472877
申请日：2021-09-13
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Joseph Raymond Michael Zbiciak , Timothy David Anderson , Jonathan (Son) Hung Tran , Kai Chirca , Daniel Wu , Abhijeet Ashok Chachad , David M. Thompson
IPC分类号： G06F11/00 , G06F9/30 , G06F9/32 , G06F9/345 , G06F9/38 , G06F11/10 , G06F12/0831 , G06F12/0875 , G06F12/0897 , G06F12/1027 , G06F16/215 , G06F12/02 , G06F12/0862
CPC分类号： G06F9/3016 , G06F9/30014 , G06F9/30036 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/383 , G06F9/3867 , G06F11/00 , G06F11/1048 , G06F12/0831 , G06F12/0835 , G06F12/0875 , G06F12/0897 , G06F12/1027 , G06F9/3822 , G06F11/10 , G06F12/0207 , G06F12/0862 , G06F2212/1056 , G06F2212/452 , G06F2212/60 , G06F2212/6022 , G06F2212/6028 , G06F2212/657 , G06F2212/681
摘要： A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache management operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

49. 发明授权

US12038838B2 Distributed processor memory chip with multi-port processor subunits 有权
公开(公告)号：US12038838B2
公开(公告)日：2024-07-16
申请号：US17669649
申请日：2022-02-11
申请人： NeuroBlade Ltd.
发明人： Elad Sity , Eliad Hillel
IPC分类号： G06F13/36 , G06F12/06 , G06F12/0802 , G06F12/14 , G06F13/16 , G06F15/78
CPC分类号： G06F12/0802 , G06F12/0646 , G06F12/1458 , G06F13/1657 , G06F13/1668 , G06F15/786 , G06F2212/1056 , G06F2212/60 , G06F2212/7202
摘要： In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.

50. 发明公开

US20240086326A1 Cache Write Overlap Handling 审中-公开
公开(公告)号：US20240086326A1
公开(公告)日：2024-03-14
申请号：US18515932
申请日：2023-11-21
申请人： Western Digital Technologies, Inc.
发明人： Shay BENISTY
IPC分类号： G06F12/0815 , G06F3/06 , G06F12/0804 , G06F12/0855 , G06F12/0868 , G06F12/0871
CPC分类号： G06F12/0815 , G06F3/061 , G06F3/0656 , G06F3/0679 , G06F12/0804 , G06F12/0855 , G06F12/0868 , G06F12/0871 , G06F2212/1024 , G06F2212/1032 , G06F2212/1056 , G06F2212/214 , G06F2212/312 , G06F2212/7203
摘要： Embodiments of the present disclosure generally relate to a target device handling overlap write commands. In one embodiment, a target device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a random accumulated buffer, a sequential accumulated buffer, and an overlap accumulated buffer. The controller is configured to receive a new write command, classify the new write command, and write data associated with the new write command to one of the random accumulated buffer, the sequential accumulated buffer, or the overlap accumulated buffer. Once the overlap accumulated buffer becomes available, the controller first flushes to the non-volatile memory the data in the random accumulated buffer and the sequential accumulated buffer that was received prior in sequence to the data in the overlap accumulated buffer. The controller then flushes the available overlap accumulated buffer, ensuring that new write commands override prior write commands.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式