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41. 发明申请

US20040022337A1 Signal sampling with clock recovery 审中-公开
标题翻译：信号采样与时钟恢复
公开(公告)号：US20040022337A1
公开(公告)日：2004-02-05
申请号：US10461216
申请日：2003-06-13
申请人： Agilent Technologies, Inc.
发明人： Joachim Moll
IPC分类号： H04L007/00
CPC分类号： G01R31/3171 , G01R31/31908 , G01R31/3191
摘要： A signal-sampling unit for sampling a digital test signal comprises a sampling path receiving the test signal and comprising a first comparator for comparing the test signal against a first threshold value and providing a first comparison signal as result of the comparison. The sampling path further comprises a sampling device for receiving as input the first comparison signal together with a timing signal comprising a plurality of successive timing marks. The sampling device is adapted to derive a value of the first comparison signal for one or more of the timing marks. A clock recovery unit further receives the test signal and derives therefrom the timing signal.
摘要翻译：用于对数字测试信号进行采样的信号采样单元包括接收测试信号的采样路径，并且包括用于将测试信号与第一阈值进行比较的第一比较器，并且作为比较结果提供第一比较信号。采样路径还包括采样装置，用于接收第一比较信号作为输入以及包括多个连续时序标记的定时信号。采样装置适于为一个或多个定时标记导出第一比较信号的值。时钟恢复单元还接收测试信号并从中导出定时信号。

42. 发明授权

US06625771B2 Tool to reconfigure pin connections between a DUT and a tester 失效
公开(公告)号：US06625771B2
公开(公告)日：2003-09-23
申请号：US09816647
申请日：2001-03-22
申请人： Adam Wright
发明人： Adam Wright
IPC分类号： G01R3128
CPC分类号： G01R31/31908 , G01R31/31926
摘要： An improved method of simulating the testing of integrated circuits is provided. A database of desired connections between a tester unit and a DUT for different downbonds is accessed by a multiplexer which sets up the desired connections. The system automatically makes the correct connection for each downbond without manual intervention from the user as was required in traditional simulator systems.

43. 发明授权

US06484116B1 Program executing system for semiconductor testing equipment 失效
标题翻译：半导体测试设备程序执行系统
公开(公告)号：US06484116B1
公开(公告)日：2002-11-19
申请号：US09574727
申请日：2000-05-18
申请人： Masaru Yokoyama
发明人： Masaru Yokoyama
IPC分类号： G01R2728
CPC分类号： G01R31/31908 , G01R31/31907
摘要： The present invention discloses a program executing system for semiconductor testing equipment that, at the time of compiling and executing the two device test programs including a common program specification command, executes the common program based on an intermediate code inserted at a position corresponding to this program specification command independently of the two device test programs.
摘要翻译：本发明公开了一种用于半导体测试设备的程序执行系统，在编译和执行包括公共程序指令命令的两个设备测试程序时，基于插入到与该程序相对应的位置的中间代码来执行公共程序规范命令独立于两个设备测试程序。

44. 发明申请

US20020070725A1 Integrated circuit tester with multi-port testing functionality 失效
标题翻译：具有多端口测试功能的集成电路测试仪
公开(公告)号：US20020070725A1
公开(公告)日：2002-06-13
申请号：US09870955
申请日：2001-05-30
发明人： Klaus-Dieter Hilliges
IPC分类号： G01R001/00
CPC分类号： G01R31/31907 , G01R31/31908 , G01R31/31926
摘要： Disclosed is an automated test equipmentnullATEnull(200) having a tester-per-pin architecture with a plurality of individual decentralized per-pin testing units (700), wherein each per-pin testing unit (700i) being adapted for testing a respective DUT-pin (di) of a device under testnullDUTnull(600) by emitting stimulus response signals to the respective DUT-pin and/or receiving stimulus response signals from the respective DUT-pin. For testing the DUT, the following steps are executed: definingnullfor a testing sequencenullthe DUT into one or more DUT-cores representing one or more functional units of the DUT and covering one or more DUT-pins of the DUT, and assigningnullduring the testing sequencenullone or more of the per-pin testing units (700i) to one or more ATE-ports (210-240), whereby each ATE-port comprises one or more of the per-pin testing units (700i) and represents an independent functional testing unit for testing one or more of the DUT-cores during the testing sequence.
摘要翻译：公开了一种自动测试设备-ATE-（200），其具有每个针脚结构测试器，其具有多个单独的分散式每针测试单元（700），其中每个针脚测试单元（700i）适于测试通过向相应的DUT引脚发射刺激响应信号和/或从相应的DUT引脚接收刺激响应信号来测试待测器件（DUT）的相应的DUT引脚（di）。为了测试DUT，执行以下步骤：将测试序列定义为将DUT置于表示DUT的一个或多个功能单元并覆盖DUT的一个或多个DUT引脚的一个或多个DUT核心中，并分配在测试序列中 - 一个或多个每引脚测试单元（700i）到一个或多个ATE端口（210-240），由此每个ATE端口包括一个或多个每引脚测试单元（700i ），并且表示用于在测试序列期间测试一个或多个DUT核的独立功能测试单元。

45. 发明申请

US20010035766A1 IC test device and method 审中-公开
标题翻译： IC测试装置及方法
公开(公告)号：US20010035766A1
公开(公告)日：2001-11-01
申请号：US09842131
申请日：2001-04-26
发明人： Minoru Nakajima
IPC分类号： G01R031/26
CPC分类号： G01R31/31711 , G01R31/2851 , G01R31/31901 , G01R31/31908 , G01R31/3191 , G01R31/31937
摘要： An IC test device and method are provided which can display the results of a SHMOO plot accurately by performing decisions only for the necessary portions thereof, thus shortening the time required for performing data acquisition. A test point separation section groups the test points within the testing range for the SHMOO plot into blocks. A control section performs pass/fail decisions via a testing section for test points at the vertices of the blocks, and, from the patterns of decision results, picks out those blocks for which the test results for adjacent vertices are different, and picks out as complete testing blocks for which is to be tested at all the test points included in them, those blocks which have in common an edge region which includes vertices for which the test results differ. The testing section performs pass/fail decisions for all the test points within the complete testing blocks.
摘要翻译：提供一种IC测试装置和方法，其可以通过仅对其必要部分执行决定来精确地显示SHMOO图的结果，从而缩短执行数据采集所需的时间。测试点分离部分将SHMOO图的测试范围内的测试点组合成块。控制部分通过测试部分对块的顶点处的测试点执行通过/失败判定，并且从判定结果的模式中选出相邻顶点的测试结果不同的那些块，并且选择为要在其中包括的所有测试点对其进行测试的完整测试块，这些块具有包含测试结果不同的顶点的边缘区域。测试部分对完整测试块内的所有测试点执行通过/失败决策。

46. 发明授权

US06282682B1 Automatic test equipment using sigma delta modulation to create reference levels 有权
标题翻译：自动测试设备使用Σ-Δ调制来创建参考水平
公开(公告)号：US06282682B1
公开(公告)日：2001-08-28
申请号：US09245223
申请日：1999-02-05
申请人： Ernest P. Walker , Ronald A. Sartschev , Allan M. Ryan, Jr. , Eric D. Blom
发明人： Ernest P. Walker , Ronald A. Sartschev , Allan M. Ryan, Jr. , Eric D. Blom
IPC分类号： G01R3128
CPC分类号： G01R31/31908 , G01R31/31924
摘要： Pin slice circuitry used in automatic test equipment is disclosed. The pin slice circuitry includes a portion implemented using CMOS technology and a portion implemented using bipolar technology. The CMOS portion includes a plurality of timing generator circuits and sigma delta modulator circuitry, which is used to generate digital bit streams representative of analog reference levels. The bipolar portion includes driver/receiver channels, a parametric measurement unit, and decoder circuitry, which produces the analog reference levels from the digital bit streams generated by the modulator circuitry. The analog reference levels are used by the driver/receiver channels and the parametric measurement unit. The disclosed pin slice circuitry has the advantages of reduced size and cost as compared with conventional pin slice circuitry.
摘要翻译：公开了用于自动测试设备的引脚片电路。引脚片电路包括使用CMOS技术实现的部分和使用双极技术实现的部分。 CMOS部分包括多个定时发生器电路和Σ-Δ调制器电路，其用于产生表示模拟参考电平的数字位流。双极部分包括驱动器/接收器通道，参数测量单元和解码器电路，其从调制器电路产生的数字位流产生模拟参考电平。模拟参考电平由驱动器/接收器通道和参数测量单元使用。与传统的引脚片电路相比，所公开的引脚片电路具有减小尺寸和成本的优点。

47. 发明授权

US6081771A Apparatus checking method and apparatus to which the same is applied 失效
标题翻译：装置检查方法及其相同的装置
公开(公告)号：US6081771A
公开(公告)日：2000-06-27
申请号：US149773
申请日：1998-09-08
申请人： Ryo Urabe
发明人： Ryo Urabe
IPC分类号： G01R31/319 , G06F11/22 , G06F11/267 , G06F11/00
CPC分类号： G06F11/2215 , G06F11/2273 , G01R31/31908
摘要： In a method of checking an apparatus, failure time intervals of sections of an apparatus are divided into a plurality of failure time interval groups, each of which is indicated by a specific failure time interval. A plurality of check programs are classified into a plurality of groups corresponding to the plurality of failure time interval groups based on the failure time interval of the section corresponding to each of the plurality of check programs. A group execution time interval of each of the plurality of groups is determined based on the specific failure time interval. Then, each of the plurality of groups is executed based on the group execution time interval.
摘要翻译：在检查装置的方法中，装置的部分的故障时间间隔被划分为多个故障时间间隔组，每组故障时间间隔组由特定的故障时间间隔指示。基于与多个检查程序中的每一个对应的部分的故障时间间隔，将多个检查程序分类为与多个故障时间间隔组对应的多个组。基于特定的故障时间间隔来确定多个组中的每个组的组执行时间间隔。然后，基于组执行时间间隔来执行多个组中的每一个。

48. 发明授权

US6052807A Multiple probe test equipment with channel identification 失效
标题翻译：具有通道识别功能的多探头测试设备
公开(公告)号：US6052807A
公开(公告)日：2000-04-18
申请号：US996979
申请日：1997-12-23
申请人： Richard A. Nygaard, Jr.
发明人： Richard A. Nygaard, Jr.
IPC分类号： G01R1/073 , G01R31/3177 , G01R31/319 , G01R31/28
CPC分类号： G01R1/073 , G01R31/3177 , G01R31/318385 , G01R31/31908
摘要： Multi-channel measurement equipment identifies probe-to-channel correspondence by providing an identification (ID) terminal that can be touched by a probe whose channel correspondence is sought. A ID signal identifiable by its uncommon properties is present at the ID terminal. The uncommon ID signal is generated by a suitable circuit, which may be similar to pseudo random sequence generator. Each channel is equipped with a recognition circuit that recognizes the presence of the uncommon ID signal. The recognition circuits each receive a copy of the uncommon ID signal, and the task of recognition is performed by pattern matching over time. To discover a probe's channel identity the operator touches the probe to the ID terminal. After a suitable but brief period of time the recognition circuit for that probe produces an output that indicates recognition. The measurement equipment may display a message on a screen to the effect that the system has noticed that the probe for channel "X" is on the ID terminal.
摘要翻译：多通道测量设备通过提供可以被寻找通道对应的探头触摸的识别（ID）终端来识别探测到通道对应。身份识别码终端上存在可被其不常见属性识别的ID信号。不常见的ID信号由合适的电路产生，其可以类似于伪随机序列发生器。每个通道配备有识别不常见的ID信号的识别电路。识别电路各自接收不常见ID信号的副本，并且通过随时间的模式匹配来执行识别任务。为了发现探头的通道标识，操作者将探头连接至ID终端。在适当但短暂的时间段之后，该探头的识别电路产生指示识别的输出。测量设备可能会在屏幕上显示一条消息，表示系统已经注意到通道“X”的探头位于ID终端上。

49. 发明授权

US5951705A Integrated circuit tester having pattern generator controlled data bus 失效
标题翻译：具有模式发生器控制数据总线的集成电路测试仪
公开(公告)号：US5951705A
公开(公告)日：1999-09-14
申请号：US962419
申请日：1997-10-31
申请人： Brian J. Arkin , David Scott , Ha Nguyen
发明人： Brian J. Arkin , David Scott , Ha Nguyen
IPC分类号： G01R31/28 , G01R31/30 , G01R31/3183 , G01R31/319 , G06F11/00
CPC分类号： G01R31/31921 , G01R31/31907 , G01R31/31908 , G01R31/31926 , G01R31/31928 , G01R31/3004 , G01R31/31922
摘要： An integrated circuit tester includes a host computer, a pattern generator and a set of tester circuits. The tester circuits perform test activities on an integrated circuit in response to sequences of test control data arriving via a set of data lines. The host computer may write parameter control data into the tester circuits via a bus telling the tester circuits how to adjust various parameters of test activities to be performed in response to a next arriving sequence of test control data. The host computer is also linked to the pattern generator via that same bus and writes pattern control data into the pattern generator via the bus. The pattern control data tells the pattern generator to generate alternating sequences of test control data and pattern control data. As it is generated, each test control data sequence is delivered to the tester circuits via the data lines to tell the tester circuits how to carry out a sequence of test activities. As each parameter control data sequence is generated, the parameter control data is written into the tester circuits via the bus to set the test parameters for a next sequence of test activities to be performed. Thus once programmed with pattern control data from the host, the pattern generator can cause the tester circuits to carry out a sequence of tests and to appropriately adjust their test parameters before each test without further assistance from the host computer.
摘要翻译：集成电路测试仪包括主计算机，模式发生器和一组测试器电路。测试器电路响应于经由一组数据线到达的测试控制数据的序列，在集成电路上执行测试活动。主计算机可以通过总线将参数控制数据写入测试仪电路，告知测试电路如何调整响应于下一个到达的测试控制数据序列来执行的测试活动的各种参数。主计算机也通过同一总线连接到模式发生器，并通过总线将模式控制数据写入模式发生器。模式控制数据告诉模式发生器产生测试控制数据和模式控制数据的交替序列。随着产生，每个测试控制数据序列通过数据线传送到测试仪电路，告诉测试仪电路如何执行一系列测试活动。随着每个参数控制数据序列的生成，参数控制数据通过总线写入测试仪电路，为要执行的下一个测试活动序列设置测试参数。因此，一旦编程了来自主机的模式控制数据，模式发生器可以使测试器电路执行一系列测试，并且在每次测试之前适当地调整它们的测试参数，而无需主计算机的进一步帮助。

50. 发明授权

US5909450A Tool to reconfigure pin connections between a dut and a tester 失效
标题翻译：重新配置dut和测试仪之间的引脚连接的工具
公开(公告)号：US5909450A
公开(公告)日：1999-06-01
申请号：US970696
申请日：1997-11-14
申请人： Adam Wright
发明人： Adam Wright
IPC分类号： G01R31/319 , G06F11/60
CPC分类号： G01R31/31908 , G01R31/31926
摘要： An improved method of simulating the testing of integrated circuits is provided. A database of desired connections between a tester unit and a DUT for different downbonds is accessed by a multiplexer which sets up the desired connections. The system automatically makes the correct connection for each downbond without manual intervention from the user as was required in traditional simulator systems.
摘要翻译：提供了一种模拟集成电路测试的改进方法。用于不同下限的测试器单元和DUT之间的期望连接的数据库由设置所需连接的多路复用器访问。在传统的模拟器系统中，系统会自动对每个向下悬置进行正确的连接，无需用户进行手动干预。

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