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41. 发明申请

US20100080421A1 Apparatus and method for eye margin calculating, and computer-readable recording medium recording program therefof 有权
标题翻译：记录介质记录程序的装置和方法
公开(公告)号：US20100080421A1
公开(公告)日：2010-04-01
申请号：US12591843
申请日：2009-12-02
申请人： Daita Tsubamoto , Masaki Tosaka , Shogo Fujimori
发明人： Daita Tsubamoto , Masaki Tosaka , Shogo Fujimori
IPC分类号： G06K9/00
CPC分类号： G01R31/31711 , G01R31/31708
摘要： A center location of an eye pattern generated by superimposing waveform signal pieces cut out from a waveform signal generated by a simulator is calculated, and an arrangement of a mask as a quality evaluation criterion of the eye pattern on the center location is envisaged to calculate time coordinate values and voltage coordinate values of feature points included in the mask. First feature points not on a time axis is set as processing objects, and a margin in the voltage axis direction is calculated based on the voltage coordinate values of the first feature points and the voltage coordinate values of waveform signal piece parts associated with the first feature points. Second feature points on the time axis is set as processing objects, and a margin in the time axis direction is calculated based on the time coordinate values of the second feature points and the time coordinate values of waveform signal piece parts associated with the second feature points.
摘要翻译：计算通过叠加由模拟器产生的波形信号切出的波形信号片而生成的眼图的中心位置，并且设想将作为眼图的质量评估准则的掩模作为中心位置的布置来计算时间掩模中包含的特征点的坐标值和电压坐标值。将不在时间轴上的第一特征点设置为处理对象，并且基于第一特征点的电压坐标值和与第一特征相关联的波形信号片部分的电压坐标值计算电压轴方向上的余量积分将时间轴上的第二特征点设置为处理对象，并且基于第二特征点的时间坐标值和与第二特征点相关联的波形信号片段的时间坐标值来计算时间轴方向上的余量。

42. 发明申请

US20100020861A1 DFE Margin Test Methods and Circuits that Decouple Sample and Feedback Timing 审中-公开
标题翻译： DFE边距测试方法和电路，分离样品和反馈时序
公开(公告)号：US20100020861A1
公开(公告)日：2010-01-28
申请号：US12558133
申请日：2009-09-11
申请人： Brian S. Leibowitz , Bruno W. Garlepp
发明人： Brian S. Leibowitz , Bruno W. Garlepp
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , G01R31/31709 , G01R31/31711 , H04J11/0023 , H04L1/20 , H04L1/241 , H04L1/242 , H04L1/244 , H04L5/006 , H04L7/033 , H04L25/03146
摘要： Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.
摘要翻译：描述了数字接收机边缘测试的方法和电路。这些方法和电路可以防止误差响应于错误接收的数据而崩溃，并且因此可以用于采用历史数据的接收机来减少符号间干扰（ISI）。一些实施例允许独立于采样定时来调整反馈定时以测量某些形式的相位未对准和抖动的影响。

43. 发明授权

US07617065B2 Methodology for estimating statistical distribution characteristics of physical parameters of semiconductor device 失效
标题翻译：估算半导体器件物理参数统计分布特征的方法
公开(公告)号：US07617065B2
公开(公告)日：2009-11-10
申请号：US11698690
申请日：2007-01-26
申请人： Dae-Wook Kim , Sang-Hoon Lee , Ji-Seong Doh , Moon-Hyun Yoo , Jong-Bae Lee
发明人： Dae-Wook Kim , Sang-Hoon Lee , Ji-Seong Doh , Moon-Hyun Yoo , Jong-Bae Lee
IPC分类号： G06F17/00
CPC分类号： G06F17/5009 , G01R31/31711 , G01R31/318314 , G06F2217/10 , G06F2217/78
摘要： A method for estimating statistical distribution characteristics of physical parameters of a semiconductor device includes manufacturing a plurality of semiconductor device chips, each having a plurality of transistors, preparing electrical characteristic data by measuring electrical characteristics of the plurality of transistors included in the plurality of chips, extracting an inter-chip distribution characteristic and an intra-chip distribution characteristic of the electrical characteristics by analyzing the electrical characteristic data, generating random number data satisfying the extracted inter-chip and intra-chip distribution characteristics, and performing a simulation for extracting statistical distribution characteristic data of the physical parameters of the chips, based on the random number data.
摘要翻译：一种用于估计半导体器件的物理参数的统计分布特性的方法包括制造多个半导体器件芯片，每个半导体器件芯片具有多个晶体管，通过测量包括在多个芯片中的多个晶体管的电特性来制备电特性数据，通过分析电特性数据，产生满足提取的芯片间和片内分布特性的随机数数据，提取电特性的片间分布特性和芯片内分布特性，并执行用于提取统计分布的模拟基于随机数数据的芯片的物理参数的特征数据。

44. 发明申请

US20080192814A1 System and Method for Physical-Layer Testing of High-Speed Serial Links in their Mission Environments 审中-公开
标题翻译：其任务环境中高速串行链路物理层测试的系统和方法
公开(公告)号：US20080192814A1
公开(公告)日：2008-08-14
申请号：US12028577
申请日：2008-02-08
申请人： Mohamed M. Hafed , Donald Dansereau , Geoffrey Duerden , Sebastien Laberge , Yvon Nazon , Clarence Kar Lun Tam
发明人： Mohamed M. Hafed , Donald Dansereau , Geoffrey Duerden , Sebastien Laberge , Yvon Nazon , Clarence Kar Lun Tam
IPC分类号： H04B3/46
CPC分类号： G01R31/31711 , G01R31/31901 , H04L43/50
摘要： A physical-layer tester for testing a high-speed serial link between a mission-environment transmitter and a mission-environment receiver. The tester includes a data path and a measurement path. The data path allows a data signal transmitted from the mission-environment transmitter to be passed through the tester to the mission-environment receiver. The measurement path includes circuitry for use in analyzing characteristics of the high-speed serial data traffic on the high-speed serial link. The tester is placed in the high-speed serial link and allows the link to be tested while live, mission-environment data is present on the link. Methods for implementing in-link testing are also disclosed.
摘要翻译：用于测试任务环境发射机和任务环境接收机之间的高速串行链路的物理层测试仪。测试仪包括数据路径和测量路径。数据路径允许从任务环境发射机发送的数据信号通过测试仪传递到任务环境接收器。测量路径包括用于分析高速串行数据业务在高速串行链路上的特性的电路。测试仪放置在高速串行链路中，并允许测试链路，同时实时，任务环境数据存在于链路上。还公开了实现链路测试的方法。

45. 发明申请

US20080159369A1 METHOD OF GENERATING AN EYE DIAGRAM OF INTEGRATED CIRCUIT TRANSMITTED SIGNALS 审中-公开
标题翻译：生成集成电路传输信号的眼图的方法
公开(公告)号：US20080159369A1
公开(公告)日：2008-07-03
申请号：US12049325
申请日：2008-03-15
申请人： Hayden C. Cranford , Fadi H. Gebara , Jeremy D. Schaub
发明人： Hayden C. Cranford , Fadi H. Gebara , Jeremy D. Schaub
IPC分类号： G06K9/68
CPC分类号： G01R31/31711 , H04L1/205 , H04L1/24
摘要： A sequence of K voltage samples of a transmitted data signal is generated by sampling, digitizing, and storing voltage samples of the data signal with an imbedded sample clock on an IC having an unknown period TS. The K voltage samples are plotted against a time base of K sequential times TB[K] normalized so all samples fall within one cycle of the data clock used to generate the data signal or a unit time of 1. The time base is generated by estimating the sample clock period TSE to be some multiple of 1/P where P is greater than K. Eye diagrams are analyzed for time jitter wherein only the minimum value of jitter is saved. TSE is incremented by 1/P until TS is greater than one half the data clock period. The eye diagram at the TSE with the minimum time jitter is used to analyze the data channels.
摘要翻译：通过在具有未知周期TS的IC上以嵌入的采样时钟采样，数字化和存储数据信号的电压采样来生成发送数据信号的K个电压样本的序列。 K电压样本相对于K次顺序TB [K]的时基绘制，归一化，所以所有采样都落在用于生成数据信号的数据时钟或单位时间为1的一个周期内。时基是通过估计采样时钟周期TSE为1 / P的某个倍数，其中P大于K.眼图分析时间抖动，其中只保存抖动的最小值。 TSE递增1 / P，直到TS大于数据时钟周期的一半。 TSE具有最小时间抖动的眼图用于分析数据通道。

46. 发明授权

US07222274B2 Testing and repair methodology for memories having redundancy 有权
标题翻译：具有冗余性的存储器的测试和修复方法
公开(公告)号：US07222274B2
公开(公告)日：2007-05-22
申请号：US10708342
申请日：2004-02-25
申请人： Michael L. Combs , Dale B. Grosch , Toshiharu Saitoh , Guy M. Vanzo
发明人： Michael L. Combs , Dale B. Grosch , Toshiharu Saitoh , Guy M. Vanzo
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G01R31/31711
摘要： A method of testing and repairing an integrated circuit having a total number of fuses for effecting repair of the integrated circuit. The method including: testing a memory array with a set of tests and reserving a first number of the total number of fuses for use in repairing the memory array based on results of the first set of tests; and shmoo testing the memory array by incrementing, decrementing or incrementing and decrementing values of a test parameter until a minimum or maximum value of the test parameter is reached that utilizes a second number of the total number of fuses for use in repairing the memory array to operate at the minimum or maximum value of the test parameter.
摘要翻译：一种用于测试和修复具有总数量的保险丝以用于实现集成电路的修复的集成电路的方法。该方法包括：利用一组测试来测试存储器阵列，并且基于第一组测试的结果预留用于修复存储器阵列的熔丝总数的第一数量; 并且shmoo通过递增，递减或递增和递减测试参数的值来测试存储器阵列，直到达到测试参数的最小或最大值，该测试参数使用用于修复存储器阵列的第二数量的保险丝以测试参数的最小值或最大值运行。

47. 发明授权

US07197435B1 Method and apparatus for using clustering method to analyze semiconductor devices 有权
标题翻译：使用聚类方法分析半导体器件的方法和装置
公开(公告)号：US07197435B1
公开(公告)日：2007-03-27
申请号：US10817300
申请日：2004-04-02
申请人： Jeffrey P. Erhardt , Shivananda S. Shetty
发明人： Jeffrey P. Erhardt , Shivananda S. Shetty
IPC分类号： G06F15/00
CPC分类号： G01R31/31711
摘要： A method for analyzing a semiconductor device tests a semiconductor device to produce first and second data. A clustering method is applied to the first data, creating a clustered first data. The clustered first data is then correlated with the second data to determine analyzed data.
摘要翻译：用于分析半导体器件的方法测试半导体器件以产生第一和第二数据。聚类方法应用于第一个数据，创建一个聚簇的第一个数据。然后将聚集的第一数据与第二数据相关以确定分析的数据。

48. 发明申请

US20060227912A1 DFE margin test methods and circuits that decouple sample and feedback timing 有权
公开(公告)号：US20060227912A1
公开(公告)日：2006-10-12
申请号：US11413584
申请日：2006-04-28
申请人： Brian Leibowitz , Bruno Garlepp
发明人： Brian Leibowitz , Bruno Garlepp
IPC分类号： H04B1/10 , H04L7/00
CPC分类号： H04L25/03057 , G01R31/31709 , G01R31/31711 , H04J11/0023 , H04L1/20 , H04L1/241 , H04L1/242 , H04L1/244 , H04L5/006 , H04L7/033 , H04L25/03146
摘要： Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.

49. 发明申请

US20060139033A1 Apparatus and method for performing eye scan 有权
标题翻译：用于进行眼睛扫描的装置和方法
公开(公告)号：US20060139033A1
公开(公告)日：2006-06-29
申请号：US11151132
申请日：2005-06-13
申请人： Simon Forey , Andrew Pickering , Robert Simpson , Tom Leslie
发明人： Simon Forey , Andrew Pickering , Robert Simpson , Tom Leslie
IPC分类号： G01R27/04
CPC分类号： G01R13/0254 , G01R31/31711
摘要： There is provided a method and apparatus for performing an eye scan. Said apparatus comprises: a receiver for receiving input signals; an equaliser for processing said input signals; a data sampler for sampling said processed input signals at certain sampling points to produce a data output, said data sampler being controlled by a clock signal; an edge sampler for detecting the edges of the processed input signal; an early/late voter for deciding whether a current sampling point needs to be advanced or retarded. The early/late voter passes an Up/Down signal to an interpolator for maintaining said clock signal, said interpolator acting on said Up/Down signal to adjust the clock signal by stepping it forward or backward according to control need, so that said sampling point can be advanced or retarded.
摘要翻译：提供了一种执行眼睛扫描的方法和装置。所述装置包括：接收器，用于接收输入信号; 用于处理所述输入信号的均衡器; 数据采样器，用于在某些采样点采样所述经处理的输入信号以产生数据输出，所述数据采样器由时钟信号控制; 用于检测经处理的输入信号的边缘的边缘采样器; 一个早/晚的选民，用于决定当前的抽样点是否需要提前或延迟。早/晚选民通过一个向上/向下信号到内插器，用于维持所述时钟信号，所述内插器作用于所述上/下信号，以根据控制需要向前或向后逐步调整时钟信号，使得所述采样点可以先进或延缓。

50. 发明申请

US20040230392A1 System and method for generating a SHMOO plot by varying the resolution thereof 失效
标题翻译：通过改变其分辨率来产生SHMOO图的系统和方法
公开(公告)号：US20040230392A1
公开(公告)日：2004-11-18
申请号：US10870772
申请日：2004-06-17
发明人： Christopher Todd Weller
IPC分类号： G06F019/00
CPC分类号： G01R31/31711 , G01R31/31901 , G01R31/31908 , G01R31/3191 , G01R31/31937
摘要： A scheme for testing an electrical device to determine a range of combinations of values of N parametric variables, i.e., a SHMOO plot, for which the device functions properly. In one embodiment, the method comprises defining an N-dimensional plot region comprising a plurality of operating points each corresponding to a particular combination of values of the N parametric variables. The plot region is successively subdivided into smaller sub-regions, based on determining whether the electrical device passes or fails upon testing at each operating point of a predetermined subset of operating points of the plot region or one of the smaller sub-regions, until a minimum resolution is achieved.
摘要翻译：一种用于测试电气设备以确定设备正常工作的N个参数变量（即，SHMOO图）的值的组合的范围的方案。在一个实施例中，该方法包括定义包括多个操作点的N维绘图区域，每个操作点对应于N个参数变量的值的特定组合。基于确定电子设备在绘图区域的预定子集的操作点或较小子区域中的一个的每个操作点的每个操作点上是否通过或失败，依次细分为更小的子区域，直到达到最低分辨率。

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