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41. 发明申请

US20140284545A1 In-Situ Nitride Initiation Layer For RRAM Metal Oxide Switching Material 审中-公开
标题翻译：用于RRAM金属氧化物开关材料的现场氮化物起始层
公开(公告)号：US20140284545A1
公开(公告)日：2014-09-25
申请号：US14259343
申请日：2014-04-23
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Albert Sanghyup Lee
IPC分类号： H01L45/00
CPC分类号： H01L45/145 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1616
摘要： A resistive memory device having an in-situ nitride initiation layer is disclosed. The nitride initiation layer is formed above the first electrode, and the metal oxide switching layer is formed above the nitride initiation layer to prevent oxidation of the first electrode. The nitride initiation layer may be a metal nitride layer that is formed by atomic layer deposition in the same chamber in which the metal oxide switching layer is formed. The nitride initiation layer and metal oxide switching layer may alternatively be formed in a chemical vapor deposition (CVD) chamber or a physical vapor deposition (PVD) chamber.
摘要翻译：公开了一种具有原位氮化物引发层的电阻式存储器件。氮化物引发层形成在第一电极的上方，金属氧化物开关层形成在氮化物引发层的上方，以防止第一电极的氧化。氮化物引发层可以是在形成有金属氧化物开关层的同一室中通过原子层沉积而形成的金属氮化物层。氮化物引发层和金属氧化物开关层可以替代地在化学气相沉积（CVD）室或物理气相沉积（PVD）室中形成。

42. 发明授权

US08835892B2 Electronic devices including carbon nano-tube films having boron nitride-based liners, and methods of forming the same 有权
标题翻译：包括具有氮化硼基衬垫的碳纳米管膜的电子器件及其形成方法
公开(公告)号：US08835892B2
公开(公告)日：2014-09-16
申请号：US12608592
申请日：2009-10-29
申请人： Wipul Pemsiri Jayasekara
发明人： Wipul Pemsiri Jayasekara
IPC分类号： H01L47/00 , H01L45/00 , H01L27/24 , B82Y10/00 , H01L51/05 , H01L51/00 , G11C13/02
CPC分类号： H01L45/04 , B82Y10/00 , G11C13/025 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/12 , H01L45/1233 , H01L45/149 , H01L45/1608 , H01L45/1616 , H01L45/1675 , H01L51/0048 , H01L51/0591
摘要： Methods in accordance with this invention form a microelectronic structure by forming a carbon nano-tube (“CNT”) layer, and forming a boron nitride layer (“BN liner”) above the CNT layer, wherein the BN liner comprises: (1) a first portion disposed above and in contact with the CNT layer; and/or (2) a second portion disposed in and/or around one or more carbon nano-tubes in the CNT layer. Numerous other aspects are provided.
摘要翻译：根据本发明的方法通过形成碳纳米管（“CNT”）层并在CNT层上形成氮化硼层（“BN衬垫”）形成微电子结构，其中BN衬垫包括：（1）设置在所述CNT层上方并与所述CNT层接触的第一部分; 和/或（2）设置在CNT层中的一个或多个碳纳米管中和/或周围的第二部分。提供了许多其他方面。

43. 发明申请

US20140250260A1 ASYNCHRONOUS FIFO BUFFER FOR MEMORY ACCESS 有权
标题翻译：用于存储器访问的异步FIFO缓冲器
公开(公告)号：US20140250260A1
公开(公告)日：2014-09-04
申请号：US14193917
申请日：2014-02-28
申请人： SanDisk 3D LLC
发明人： Kian-Chin Alex Yap
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0246 , G06F12/0862 , G11C7/1039 , G11C7/1057 , G11C7/106 , G11C7/1066 , G11C7/222 , G11C16/26 , G11C16/32 , G11C2207/2272 , G11C2207/2281
摘要： An asynchronous FIFO buffer that provides data in response to requests to read a memory array is disclosed. The asynchronous FIFO buffer provides the data output within a latency tolerance. The asynchronous FIFO has a read clock input and a write clock input. The read clock input receives a read enable signal that defines how data should be clocked out. The write clock input receives a write clock that is asynchronous from the read enable signal. The asynchronous FIFO inputs data from the memory array in accordance with the write clock signal. The asynchronous FIFO outputs data in accordance with the read enable signal. Control logic may pre-fetch data from the memory array into the asynchronous FIFO prior to the read enable signal first being received.
摘要翻译：公开了一种响应于读取存储器阵列的请求而提供数据的异步FIFO缓冲器。异步FIFO缓冲器在延迟容差内提供数据输出。异步FIFO具有读时钟输入和写时钟输入。读时钟输入接收一个读使能信号，该信号定义数据应如何计时。写时钟输入接收与读使能信号异步的写时钟。异步FIFO根据写时钟信号从存储器阵列输入数据。异步FIFO根据读使能信号输出数据。在首先接收到读使能信号之前，控制逻辑可以将数据从存储器阵列预取入异步FIFO。

44. 发明授权

US08816315B2 Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same 有权
标题翻译：采用选择性生长的可逆电阻切换元件的存储单元及其形成方法
公开(公告)号：US08816315B2
公开(公告)日：2014-08-26
申请号：US13764065
申请日：2013-02-11
申请人： SanDisk 3D LLC
发明人： April D. Schricker , Brad Herner , Mark H. Clark
IPC分类号： H01L29/02
CPC分类号： H01L45/146 , H01L27/24
摘要： A memory cell is provided that includes a reversible resistance-switching element above a substrate. The reversible resistance-switching element includes an etched material layer that includes an oxidized layer of the etched material layer above a non-oxidized layer of the etched material layer. Numerous other aspects are provided.
摘要翻译：提供了一种存储单元，其包括在基板上方的可逆电阻切换元件。可逆电阻切换元件包括蚀刻材料层，该蚀刻材料层包括在蚀刻材料层的未氧化层之上的蚀刻材料层的氧化层。提供了许多其他方面。

45. 发明申请

US20140235029A1 Bipolar Multistate Nonvolatile Memory 有权
标题翻译：双极多态非易失性存储器
公开(公告)号：US20140235029A1
公开(公告)日：2014-08-21
申请号：US14259411
申请日：2014-04-23
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Tony P. Chiang
IPC分类号： H01L45/00
CPC分类号： H01L45/1608 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1616
摘要： Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states. Each variable resistance layer may have an associated high resistance state and an associated low resistance state. As the resistance of each variable resistance layer determines the digital data bit that is stored, the multiple variable resistance layers per memory element allows for additional data storage without the need to further increase the density of nonvolatile memory devices. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.
摘要翻译：实施例通常包括形成非易失性存储器件的方法，该非易失性存储器件包含通过使用多层可变电阻层而具有改进的器件开关容量的电阻式开关存储器元件。在一个实施例中，电阻式开关元件包括至少三层可变电阻材料以增加逻辑状态的数量。每个可变电阻层可以具有相关联的高电阻状态和相关联的低电阻状态。由于每个可变电阻层的电阻决定了存储的数字数据位，每个存储元件的多个可变电阻层允许额外的数据存储，而不需要进一步增加非易失性存储器件的密度。通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。

46. 发明授权

US08809114B2 Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same 有权
标题翻译：使用选择性生长的可逆电阻切换元件的存储单元及其形成方法
公开(公告)号：US08809114B2
公开(公告)日：2014-08-19
申请号：US13964157
申请日：2013-08-12
申请人： SanDisk 3D LLC
发明人： April D. Schricker , S. Brad Herner , Mark H. Clark
IPC分类号： H01L29/02
CPC分类号： H01L45/1641 , G11C13/0007 , G11C2213/31 , G11C2213/33 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1633 , H01L45/1675
摘要： A method of forming a memory cell is provided that includes forming a steering element above a substrate, forming a material layer on the substrate, patterning and etching the material layer, and oxidizing the patterned and etched material layer to form a reversible resistance-switching material. Numerous other aspects are provided.
摘要翻译：提供一种形成存储单元的方法，其包括在基板上形成操纵元件，在基板上形成材料层，图案化和蚀刻材料层，以及氧化图案化和蚀刻的材料层以形成可逆电阻切换材料。提供了许多其他方面。

47. 发明申请

US20140225057A1 Resistance-Switching Memory Cell With Multiple Electrodes 有权
标题翻译：具有多个电极的电阻切换存储单元
公开(公告)号：US20140225057A1
公开(公告)日：2014-08-14
申请号：US13767663
申请日：2013-02-14
申请人： SanDisk 3D LLC
发明人： George Matamis , James K. Kai , Vinod R. Purayath , Yuan Zhang , Henry Chien
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/1273 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/16 , H01L45/1675
摘要： A reversible resistance-switching memory cell has multiple narrow, spaced apart bottom electrode structures. The raised structures can be formed by coating a bottom electrode layer with nano-particles and etching the bottom electrode layer. The raised structures can be independent or joined to one another at a bottom of the bottom electrode layer. A resistance-switching material is provided between and above the bottom electrode structure, followed by a top electrode layer. Or, insulation is provided between and above the bottom electrode structures, and the resistance-switching material and top electrode layer are above the insulation. Less than one-third of a cross-sectional area of each resistance-switching memory cell is consumed by the one or more raised structures. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower.
摘要翻译：可逆电阻切换存储单元具有多个窄间隔开的底部电极结构。凸起结构可以通过用纳米颗粒涂覆底部电极层并蚀刻底部电极层来形成。凸起结构可以在底部电极层的底部是独立的或彼此连接的。电阻切换材料设置在底部电极结构之间和之上，随后是顶部电极层。或者，在底部电极结构之间和之上提供绝缘，并且电阻切换材料和顶部电极层在绝缘体之上。每个电阻切换存储单元的横截面积的不到三分之一被一个或多个凸起结构所消耗。当切换存储单元的电阻状态时，电流路径的底部电极的面积越小，开关电阻越高，开关电流越低。

48. 发明授权

US08802492B2 Method for forming resistive switching memory elements 有权
标题翻译：用于形成电阻式开关存储元件的方法
公开(公告)号：US08802492B2
公开(公告)日：2014-08-12
申请号：US13219806
申请日：2011-08-29
申请人： Jinhong Tong , Randall Higuchi , Imran Hashim , Vidyut Gopal
发明人： Jinhong Tong , Randall Higuchi , Imran Hashim , Vidyut Gopal
IPC分类号： H01L21/00 , H01L21/16
CPC分类号： H01L45/1608 , H01L45/04 , H01L45/146 , H01L45/1616 , H01L45/1633 , H01L45/1658
摘要： Methods for producing RRAM resistive switching elements having reduced forming voltage include doping to create oxygen deficiencies in the dielectric film. Oxygen deficiencies in a dielectric film promote formation of conductive pathways.
摘要翻译：制造具有降低的成形电压的RRAM电阻式开关元件的方法包括掺杂以在电介质膜中产生氧缺陷。电介质膜中的氧缺乏促进导电通路的形成。

49. 发明申请

US20140217348A1 Transition Metal Oxide Bilayers 有权
标题翻译：过渡金属氧化物双层
公开(公告)号：US20140217348A1
公开(公告)日：2014-08-07
申请号：US14252285
申请日：2014-04-14
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Hieu Pham , Vidyut Gopal , Imran Hashim , Tim Minvielle , Yun Wang , Takeshi Yamaguchi , Hong Sheng Yang
IPC分类号： H01L45/00
CPC分类号： H01L45/08 , H01L27/2409 , H01L27/2463 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1616 , H01L45/1625 , H01L45/1641
摘要： Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 Å and about 100 Å, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.
摘要翻译：本发明的实施例包括非易失性存储器元件和包括非易失性存储元件的存储器件。还公开了形成非易失性存储元件的方法。非易失性存储元件包括第一电极层，第二电极层和设置在第一和第二电极层之间的多个氧化物层。氧化物层中的一个具有线性电阻和亚化学计量组成，另一个氧化物层具有双稳态电阻和近化学计量组成。优选地，两个氧化物层厚度的总和在约和之间，并且具有双稳态电阻的氧化物层具有在总厚度的约25％至约75％之间的厚度。在一个实施例中，氧化物层在具有受控的氩气和氧气的气氛中使用反应溅射形成。

50. 发明授权

US08780605B2 Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture 有权
标题翻译：具有垂直位线和单面字线结构的可重新编程的非易失性存储元件的三维阵列
公开(公告)号：US08780605B2
公开(公告)日：2014-07-15
申请号：US13735983
申请日：2013-01-07
申请人： SanDisk 3D LLC
发明人： Tianhong Yan , George Samachisa
IPC分类号： G11C11/00 , G11C11/06
CPC分类号： G11C13/0007 , B82Y10/00 , G11C11/06035 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C13/025 , G11C16/10 , G11C2013/0045 , G11C2013/0088 , G11C2213/19 , G11C2213/32 , G11C2213/34 , G11C2213/55 , G11C2213/71 , G11C2213/75 , G11C2213/78 , H01L23/528 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/148 , H01L45/149
摘要： A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.
摘要翻译：特别适用于响应于在其上施加电压差而可逆地改变电导水平的存储元件的三维阵列。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件连接到的位线的二维阵列从衬底垂直定向并穿过多个平面。单面字线架构为每行存储器元件专门提供字线，而不是在两行存储器元件之间共享一个字线，从而避免跨越字线跨越阵列链接存储元件。虽然存储器元件行也被对应的局部位线行访问，但是在局部位线的相邻行之间没有扩展耦合，因此没有扩展超出字线的漏电流。

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