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41. 发明申请

US20080209167A1 APPARATUS AND METHOD FOR ADAPTIVE MULTIMEDIA RECEPTION AND TRANSMISSION IN COMMUNICATION ENVIRONMENTS 失效
标题翻译：自适应多媒体接收和通信环境传输的装置和方法
公开(公告)号：US20080209167A1
公开(公告)日：2008-08-28
申请号：US12116604
申请日：2008-05-07
申请人： Paul L. MASTER , Bohumir UVACEK
发明人： Paul L. MASTER , Bohumir UVACEK
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： H04W88/06 , H04W48/12
摘要： The present invention provides a method and apparatus for configuration of adaptive integrated circuitry, to provide one or more operating modes or other functionality in a communication device, such as a cellular telephone, a GSM telephone, another type of mobile telephone or mobile station, or any other type of media communication device, including video, voice or radio, or other forms of multimedia. The adaptive integrated circuitry is configured and reconfigured for multiple tasks, such as channel acquisition, voice transmission, or multimedia and other data processing. In the preferred embodiment, the configuration and reconfiguration occurs to adaptively optimize the performance of the particular activity over time, such as to increase the speed of channel acquisition, increase throughput rates, increase perceived voice and media quality, and decrease the rate of dropped communication sessions.
摘要翻译：本发明提供了一种用于配置自适应集成电路的方法和装置，以在诸如蜂窝电话，GSM电话，另一类型的移动电话或移动台之类的通信设备中提供一个或多个操作模式或其它功能，或任何其他类型的媒体通信设备，包括视频，语音或无线电，或其他形式的多媒体。自适应集成电路被配置和重新配置用于多个任务，例如信道获取，语音传输或多媒体和其他数据处理。在优选实施例中，发生配置和重新配置以随时间自适应地优化特定活动的性能，例如增加频道获取的速度，增加吞吐率，增加感知语音和媒体质量，以及降低丢弃通信的速率会话

42. 发明授权

US08769214B2 External memory controller node 有权
标题翻译：外部存储器控制器节点
公开(公告)号：US08769214B2
公开(公告)日：2014-07-01
申请号：US13609949
申请日：2012-09-11
申请人： Frederick Curtis Furtek , Paul L. Master
发明人： Frederick Curtis Furtek , Paul L. Master
IPC分类号： G06F12/00 , G06F13/00 , G06F13/16
CPC分类号： G06F15/167 , G06F3/0626 , G06F3/0661 , G06F3/0679 , G06F13/1657 , G11C7/1072 , H04L67/32
摘要： A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.
摘要翻译：提供了一种在自适应计算引擎中提供存储器访问服务的存储器控制器。控制器包括：被配置为从可编程网络接收存储器请求的网络接口; 以及存储器接口，被配置为访问存储器以满足来自可编程网络的存储器请求，其中存储器接口接收并向网络接口提供存储器请求的数据，网络接口被配置为向可编程网络发送数据并从可编程网络。

43. 发明授权

US08767804B2 Method and system for reconfigurable channel coding 有权
标题翻译：可重构信道编码的方法和系统
公开(公告)号：US08767804B2
公开(公告)日：2014-07-01
申请号：US13589656
申请日：2012-08-20
申请人： W. James Scheuermann
发明人： W. James Scheuermann
IPC分类号： H04B1/38
CPC分类号： H04L1/0043 , H04B1/40 , H04L1/0054 , H04L1/0059 , H04L65/601
摘要： Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.
摘要翻译：描述了用于在无线通信设备中提供信道编码的可重新配置系统的方面。这些方面包括用于执行信道编码操作的多个计算元件和用于存储用于指示多个计算元素中的每一个的程序的存储器。控制器控制多个计算元件和存储的程序，以实现根据多个无线通信标准的信道编码操作。多个计算元件包括数据重排序元件，线性反馈移位寄存器（LFSR）元件，卷积编码器元件和维特比解码器元件。

44. 发明申请

US20130013872A1 External Memory Controller Node 有权
公开(公告)号：US20130013872A1
公开(公告)日：2013-01-10
申请号：US13609949
申请日：2012-09-11
申请人： Frederick Curtis Furtek , Paul L. Master
发明人： Frederick Curtis Furtek , Paul L. Master
IPC分类号： G06F12/08
CPC分类号： G06F15/167 , G06F3/0626 , G06F3/0661 , G06F3/0679 , G06F13/1657 , G11C7/1072 , H04L67/32
摘要： A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.

45. 发明申请

US20120265914A1 ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS 有权
标题翻译：具有固定的特定计算元素的多变量和自适应计算单元的异构和可重构矩阵的自适应集成电路
公开(公告)号：US20120265914A1
公开(公告)日：2012-10-18
申请号：US13353687
申请日：2012-01-19
申请人： Paul L. Master , Eugene Hogenauer , Walter James Scheuermann
发明人： Paul L. Master , Eugene Hogenauer , Walter James Scheuermann
IPC分类号： G06F13/14
CPC分类号： G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.
摘要翻译：本发明涉及一种新类型的集成电路和用于自适应或可重新配置计算的新方法。优选的IC实施例包括耦合到互连网络的多个异构计算元件。多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。响应于配置信息，互连网络可实时操作以配置和重新配置用于多种不同功能模式的多个异构计算元件，包括线性算法运算，非线性算法运算，有限状态机操作，存储器操作和位级操作。选择各种固定架构以相对最小化功率消耗并增加自适应计算集成电路的性能，特别适用于移动，手持或其他电池供电的计算应用。

46. 发明申请

US20120222038A1 TASK DEFINITION FOR SPECIFYING RESOURCE REQUIREMENTS 审中-公开
标题翻译：用于指定资源需求的任务定义
公开(公告)号：US20120222038A1
公开(公告)日：2012-08-30
申请号：US13336953
申请日：2011-12-23
申请人： Ramana KATRAGADDA , Paul SPOLTORE , Ric HOWARD
发明人： Ramana KATRAGADDA , Paul SPOLTORE , Ric HOWARD
IPC分类号： G06F9/50
CPC分类号： G06F9/5044
摘要： Task definitions are used by a task scheduler and prioritizer to allocate task operations to a plurality of processing units. The task definition is an electronic record that specifies resources needed by, and other characteristics of, a task to be executed. Resources include types of processing nodes desired to execute the task, needed amount or rate of processing cycles, amount of memory capacity, number of registers, input/output ports, buffer sizes, etc. Characteristics of a task in clued maximum latency time, frequency of execution of a task, communication ports, and other characteristics. An examplary task definition language and syntax is described that uses constructs including order of attempted scheduling operations, percentage or amount of resources desired by different operations, handling of multiple executable images or modules, overlays, port aliases and other features.
摘要翻译：任务定义由任务调度器和优先级分配器用于将任务操作分配给多个处理单元。任务定义是指定要执行的任务所需的资源和其他特征的电子记录。资源包括执行任务所需的处理节点的类型，所需的处理周期数量或速率，存储器容量，寄存器数量，输入/输出端口，缓冲区大小等。在最大延迟时间，频率上的任务特征执行任务，通信端口等特性。描述了使用包括尝试调度操作的顺序，不同操作所需的资源的百分比或数量，多个可执行映像或模块的处理，覆盖，端口别名和其他特征的构造的示例性任务定义语言和语法。

47. 发明授权

US08249135B2 Method and system for reconfigurable channel coding 有权
标题翻译：可重构信道编码的方法和系统
公开(公告)号：US08249135B2
公开(公告)日：2012-08-21
申请号：US12860772
申请日：2010-08-20
申请人： W. James Scheuermann
发明人： W. James Scheuermann
IPC分类号： H04B1/38
CPC分类号： H04L1/0043 , H04B1/40 , H04L1/0054 , H04L1/0059 , H04L65/601
摘要： Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder clement.
摘要翻译：描述了用于在无线通信设备中提供信道编码的可重新配置系统的方面。这些方面包括用于执行信道编码操作的多个计算元件和用于存储用于指示多个计算元素中的每一个的程序的存储器。控制器控制多个计算元件和存储的程序，以实现根据多个无线通信标准的信道编码操作。多个计算元件包括数据重排序元件，线性反馈移位寄存器（LFSR）元件，卷积编码器元件和维特比解码器元件。

48. 发明授权

US08225073B2 Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements 有权
标题翻译：用于配置具有异构计算元件的自适应集成电路的装置，系统和方法
公开(公告)号：US08225073B2
公开(公告)日：2012-07-17
申请号：US12399671
申请日：2009-03-06
申请人： Paul L. Master , Stephen J. Smith , John Watson
发明人： Paul L. Master , Stephen J. Smith , John Watson
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/7867 , G06F13/40 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： The present invention concerns configuration of a new category of integrated circuitry for adaptive or reconfigurable computing. The preferred adaptive computing engine (ACE) IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, controller operations, memory operations, and bit-level manipulations. The preferred system embodiment includes an ACE integrated circuit coupled with the configuration information needed to provide an operating mode. Preferred methodologies include various means to generate and provide configuration information for various operating modes.
摘要翻译：本发明涉及用于自适应或可重新配置计算的新类别的集成电路的配置。优选的自适应计算引擎（ACE）IC包括耦合到互连网络的多个异构计算元件。多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。响应于配置信息，互连网络可操作以配置和重新配置用于多种不同功能模式的多个异构计算元件，包括线性算法运算，非线性算法运算，有限状态机操作，控制器操作，存储器操作和位级操作。优选的系统实施例包括耦合到提供操作模式所需的配置信息的ACE集成电路。优选的方法包括生成和提供各种操作模式的配置信息的各种手段。

49. 发明授权

US07984247B2 External memory controller node 有权
公开(公告)号：US07984247B2
公开(公告)日：2011-07-19
申请号：US12251871
申请日：2008-10-15
申请人： Fredrick Curtis Furtek , Paul L. Master
发明人： Fredrick Curtis Furtek , Paul L. Master
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F15/167 , G06F3/0626 , G06F3/0661 , G06F3/0679 , G06F13/1657 , G11C7/1072 , H04L67/32
摘要： A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.

50. 发明授权

US07937538B2 External memory controller node 有权
公开(公告)号：US07937538B2
公开(公告)日：2011-05-03
申请号：US12437303
申请日：2009-05-07
申请人： Frederick Curtis Furtek , Paul L. Master
发明人： Frederick Curtis Furtek , Paul L. Master
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F15/167 , G06F3/0626 , G06F3/0661 , G06F3/0679 , G06F13/1657 , G11C7/1072 , H04L67/32
摘要： A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.

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