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41. 发明授权

US07620097B2 Communications module, device, and method for implementing a system acquisition function 有权
标题翻译：用于实现系统采集功能的通信模块，设备和方法
公开(公告)号：US07620097B2
公开(公告)日：2009-11-17
申请号：US12343333
申请日：2008-12-23
申请人： Ghobad Heidari , Kuor-Hsin Chang , Paul L. Master , Eugene B. Hogenauer , Walter James Scheuermann
发明人： Ghobad Heidari , Kuor-Hsin Chang , Paul L. Master , Eugene B. Hogenauer , Walter James Scheuermann
IPC分类号： H04B1/707
CPC分类号： G06F15/7867 , H04B1/708 , H04B2201/70711
摘要： A communications module, device and corresponding method for facilitating PN code searching. The module and device have a PN sequence generator configurable to generate a plurality of PN sequences. The module and device also include computational units configurable to correlate received signal samples of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences—the number depending upon availability of the plurality of computational units from providing the other hardware resources. According to a preferred embodiment, a plurality of configurable computational units are selectively configurable to implement the PN sequence generator.
摘要翻译：一种用于促进PN码搜索的通信模块，设备和相应的方法。模块和设备具有PN序列发生器，其可配置以产生多个PN序列。模块和设备还包括可配置为将多个接收信号采样的接收信号采样与多个PN序列中的对应PN序列相关联的计算单元，并且还可配置为提供其他硬件资源。来自多个计算单元的多个计算单元被选择性地配置为将接收到的信号采样与PN序列相关联 - 取决于多个计算单元的可用性从提供其他硬件资源的数量。根据优选实施例，多个可配置的计算单元被选择性地配置以实现PN序列发生器。

42. 发明申请

US20090037673A1 External Memory Controller Node 有权
公开(公告)号：US20090037673A1
公开(公告)日：2009-02-05
申请号：US12251905
申请日：2008-10-15
申请人： Frederick Curtis Furtek , Paul L. Master
发明人： Frederick Curtis Furtek , Paul L. Master
IPC分类号： G06F12/00
CPC分类号： G06F15/167 , G06F3/0626 , G06F3/0661 , G06F3/0679 , G06F13/1657 , G11C7/1072 , H04L67/32
摘要： A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.

43. 发明申请

US20080134108A1 Method and system for creating and programming an adaptive computing engine 有权
公开(公告)号：US20080134108A1
公开(公告)日：2008-06-05
申请号：US12011340
申请日：2008-01-25
申请人： Paul L. Master
发明人： Paul L. Master
IPC分类号： G06F17/50
CPC分类号： G06F15/7867 , G06F17/5027 , Y02D10/12 , Y02D10/13
摘要： A system for creating an adaptive computing engine (ACE) includes algorithmic elements adaptable for use in the ACE and configured to provide algorithmic operations, and provides mapping of the algorithmic operations to heterogeneous nodes. The mapping is for initially configuring the heterogeneous nodes to provide appropriate hardware circuit functions that perform algorithmic operations. A reconfigurable interconnection network interconnects the heterogeneous nodes. The mapping includes selecting a combination of ACE building blocks from the ACE building block types for the appropriate hardware circuit functions. The system and corresponding method also includes utilizing the algorithmic operations for optimally configuring the heterogeneous nodes to provide the appropriate hardware circuit function. The utilizing includes the simulating of the performance of the ACE with the combination of ACE building blocks and altering the combination until predetermined performance standards that determine the efficiency of the ACE are met while simulating performance of the ACE.

44. 发明授权

US07328414B1 Method and system for creating and programming an adaptive computing engine 有权
标题翻译：用于创建和编程自适应计算引擎的方法和系统
公开(公告)号：US07328414B1
公开(公告)日：2008-02-05
申请号：US10437800
申请日：2003-05-13
申请人： Paul L. Master
发明人： Paul L. Master
IPC分类号： G06F17/50
CPC分类号： G06F15/7867 , G06F17/5027 , Y02D10/12 , Y02D10/13
摘要： A system for creating an adaptive computing engine (ACE) includes algorithmic elements adaptable for use in the ACE and configured to provide algorithmic operations, and provides mapping of the algorithmic operations to heterogeneous nodes. The mapping is for initially configuring the heterogeneous nodes to provide appropriate hardware circuit functions that perform algorithmic operations. A reconfigurable interconnection network interconnects the heterogeneous nodes. The mapping includes selecting a combination of ACE building blocks from the ACE building block types for the appropriate hardware circuit functions. The system and corresponding method also includes utilizing the algorithmic operations for optimally configuring the heterogeneous nodes to provide the appropriate hardware circuit function. The utilizing includes the simulating of the performance of the ACE with the combination of ACE building blocks and altering the combination until predetermined performance standards that determine the efficiency of the ACE are met while simulating performance of the ACE.
摘要翻译：用于创建自适应计算引擎（ACE）的系统包括适于在ACE中使用并被配置为提供算法操作并且提供算法操作到异构节点的映射的算法元件。该映射用于初始配置异构节点以提供执行算法操作的适当的硬件电路功能。可重构互连网络将异构节点互连。该映射包括从ACE构建块类型中选择ACE构建块的组合以获得适当的硬件电路功能。该系统和相应的方法还包括利用算法操作来优化配置异构节点以提供适当的硬件电路功能。利用包括通过ACE构建块的组合模拟ACE的性能，并改变组合，直到在模拟ACE的性能的同时满足确定ACE效率的预定性能标准。

45. 发明授权

US07155613B2 Apparatus, method and system for generating a unique hardware adaptation inseparable from correspondingly unique content 有权
公开(公告)号：US07155613B2
公开(公告)日：2006-12-26
申请号：US11282460
申请日：2005-11-19
申请人： Paul L. Master , John Watson
发明人： Paul L. Master , John Watson
IPC分类号： G66F1/24
CPC分类号： G06F21/73 , G06F21/10 , G06F21/72 , H04L9/0866 , H04L2209/12 , H04L2209/605 , H04L2209/80
摘要： The present invention includes an apparatus, method and system for generating a configuration of an adaptive circuit which is inseparable from selected content. Either the adaptive circuit or encrypted, selected content has a unique identifier. In one of the preferred method and system embodiments in which the adaptive circuit has the unique identifier, a request for the selected content is received, along with the unique identifier, such as by a network server. The selected content is then encrypted, based upon the unique identifier, to form encrypted content. Configuration information for the adaptive circuit, corresponding to the unique identifier and the encrypted content, is generated to form corresponding configuration information. A service provider, such as through a network server, transfers the encrypted content and the corresponding configuration information to the adaptive circuit having the unique identifier, which may then be configured for use of the selected content. As a consequence, the present invention creates adaptive hardware configurations which are uniquely coupled to the selected content.

46. 发明授权

US08442096B2 Low I/O bandwidth method and system for implementing detection and identification of scrambling codes 有权
公开(公告)号：US08442096B2
公开(公告)日：2013-05-14
申请号：US12499756
申请日：2009-07-08
申请人： Sharad Sambhwani , Ghobad Heidari
发明人： Sharad Sambhwani , Ghobad Heidari
IPC分类号： H04B1/707 , H04L27/06
CPC分类号： H04B1/70735 , H04B1/70752 , H04B1/708 , H04B1/7083 , H04B1/7095
摘要： A system for detecting and identifying the identity of a base station or cell which transmits a scrambling code is provided. According to one aspect of the system, the system is used to perform scrambling code detection of eight (8) primary cells (each scrambling code's X-component being spaced sixteen (16) chips apart) in a group. According to another aspect of the system, a single scrambling code generator is used to generate a master scrambling code. The master scrambling code is then used to create individual scrambling codes which are used in correlation with received signals to detect in parallel which one of the eight (8) possible primary cells in the group transmitted the received signals. According to yet another aspect of the system, each of the correlators maintains a corresponding X-component segment of the master scrambling code. For every sixteen (16) chips, a new X-component segment of the master scrambling code is introduced into one of the correlators, a X-component segment of the master scrambling code is dropped from another correlator, and X-component segments of the master scrambling code are sequentially shifted or propagated through the remaining correlators; and concurrent correlations are performed by the correlators using their respective corresponding X-component segments of the master scrambling code and newly received signals.

47. 发明授权

US08356161B2 Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements 失效
标题翻译：自适应处理器，用于以简单和复杂的单元执行操作，每个单元包括可配置互连的异构元素
公开(公告)号：US08356161B2
公开(公告)日：2013-01-15
申请号：US12251946
申请日：2008-10-15
申请人： Paul L. Master , Eugene Hogenauer , Walter James Scheuermann
发明人： Paul L. Master , Eugene Hogenauer , Walter James Scheuermann
IPC分类号： G06F15/80 , G06F17/10
CPC分类号： G06F15/7867 , G06F13/4027 , Y02D10/12 , Y02D10/13
摘要： The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.
摘要翻译：本发明涉及一种新类型的集成电路和用于自适应或可重新配置计算的新方法。优选的IC实施例包括耦合到互连网络的多个异构计算元件。多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。响应于配置信息，互连网络可实时操作以配置和重新配置用于多种不同功能模式的多个异构计算元件，包括线性算法运算，非线性算法运算，有限状态机操作，存储器操作和位级操作。选择各种固定架构以相对最小化功率消耗并增加自适应计算集成电路的性能，特别适用于移动，手持或其他电池供电的计算应用。

48. 发明申请

US20120317397A1 APPARATUS, METHOD, SYSTEM AND EXECUTABLE MODULE FOR CONFIGURATION AND OPERATION OF ADAPTIVE INTEGRATED CIRCUITRY HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS 有权
标题翻译：具有固定的自适应集成电路的配置和运行的装置，方法，系统和可执行模块，应用特定计算单元
公开(公告)号：US20120317397A1
公开(公告)日：2012-12-13
申请号：US13589583
申请日：2012-08-20
申请人： Paul L. Master , Stephen J. Smith , John Watson
发明人： Paul L. Master , Stephen J. Smith , John Watson
IPC分类号： G06F15/76
CPC分类号： G06F15/80 , G06F7/57 , G06F9/44505 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes.
摘要翻译：本发明涉及用于自适应计算的新类别的集成电路的配置。各种实施例提供用于自适应计算引擎（ACE）集成电路的可执行信息模块，并且可以包括配置信息，操作数数据，并且还可以包括路由和功率控制信息。 ACE IC包括耦合到互连网络的多个异构计算元件。多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。响应于配置信息，互连网络用于为多个不同的功能模式配置多个异构计算元件。

49. 发明授权

US08276135B2 Profiling of software and circuit designs utilizing data operation analyses 失效
标题翻译：利用数据操作分析对软件和电路设计进行分析
公开(公告)号：US08276135B2
公开(公告)日：2012-09-25
申请号：US10289640
申请日：2002-11-07
申请人： Paul L. Master
发明人： Paul L. Master
IPC分类号： G06F9/45
CPC分类号： G06F17/5022
摘要： The present invention is a method, system, software and data structure for profiling programs, other code, and adaptive computing integrated circuit architectures, using a plurality of data parameters such as data type, input and output data size, data source and destination locations, data pipeline length, locality of reference, distance of data movement, speed of data movement, data access frequency, number of data load/stores, memory usage, and data persistence. The profiler of the invention accepts a data set as input, and profiles a plurality of functions by measuring a plurality of data parameters for each function, during operation of the plurality of functions with the input data set, to form a plurality of measured data parameters. From the plurality of measured data parameters, the profiler generates a plurality of data parameter comparative results corresponding to the plurality of functions and the input data set. Based upon the measured data parameters, portions of the profiled code are selected for embodiment as computational elements in an adaptive computing IC architecture.
摘要翻译：本发明是使用诸如数据类型，输入和输出数据大小，数据源和目的地位置等多种数据参数的分析程序，其他代码和自适应计算集成电路架构的方法，系统，软件和数据结构，数据流水线长度，参考位置，数据移动距离，数据移动速度，数据访问频率，数据加载/存储数量，内存使用情况和数据持久性。本发明的分析器接受数据集作为输入，并且在使用输入数据集的多个功能的操作期间，通过测量每个功能的多个数据参数来分析多个功能，以形成多个测量数据参数。从多个测量数据参数中，轮廓仪产生对应于多个功能和输入数据组的多个数据参数比较结果。基于所测量的数据参数，在自适应计算IC体系结构中，为了实施例而将分布代码的部分选择为计算元件。

50. 发明申请

US20110161535A1 ADAPTABLE DATAPATH FOR A DIGITAL PROCESSING SYSTEM 有权
标题翻译：适用于数字处理系统的数据
公开(公告)号：US20110161535A1
公开(公告)日：2011-06-30
申请号：US13042391
申请日：2011-03-07
申请人： Amit RAMCHANDRAN
发明人： Amit RAMCHANDRAN
IPC分类号： G06F13/00
CPC分类号： G06F13/287 , G06F9/30014 , G06F9/3012 , G06F9/3824 , G06F9/3826 , G06F9/383 , G06F9/3867 , G06F9/3885 , G06F13/16
摘要： The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided.
摘要翻译：本发明包括具有若干特征的适应性高性能节点（RXN），使其能够提供高性能以及适应性。 RXN的优选实施例包括运行时可配置数据路径和控制路径。 RXN支持包括8,16,24和32位代码的多精度算术。可以重新配置数据流，以最小化不同操作的寄存器访问。例如，通过重新配置数据路径，可以通过最小或不存在寄存器存储来执行乘法累加操作。可以在建立阶段期间配置预定的内核，使得RXN可以有效地执行例如离散余弦变换（DCT），快速傅里叶变换（FFT）和其他操作。提供其他功能。

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