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1. 发明授权

US07904603B2 Adaptable datapath for a digital processing system 有权
标题翻译：适用于数字处理系统的数据路径
公开(公告)号：US07904603B2
公开(公告)日：2011-03-08
申请号：US12556894
申请日：2009-09-10
申请人： Amit Ramchandran
发明人： Amit Ramchandran
IPC分类号： G06F3/00
CPC分类号： G06F13/287 , G06F9/30014 , G06F9/3012 , G06F9/3824 , G06F9/3826 , G06F9/383 , G06F9/3867 , G06F9/3885 , G06F13/16
摘要： The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided.
摘要翻译：本发明包括具有若干特征的适应性高性能节点（RXN），使其能够提供高性能以及适应性。 RXN的优选实施例包括运行时可配置数据路径和控制路径。 RXN支持包括8,16,24和32位代码的多精度算术。可以重新配置数据流，以最小化不同操作的寄存器访问。例如，通过重新配置数据路径，可以通过最小或不存在寄存器存储来执行乘法累加操作。可以在建立阶段期间配置预定的内核，使得RXN可以有效地执行例如离散余弦变换（DCT），快速傅里叶变换（FFT）和其他操作。提供其他功能。

2. 发明申请

US20070150656A1 CACHE FOR INSTRUCTION SET ARCHITECTURE USING INDEXES TO ACHIEVE COMPRESSION 有权
标题翻译：使用索引进行压缩的指令设置架构的缓存
公开(公告)号：US20070150656A1
公开(公告)日：2007-06-28
申请号：US11683026
申请日：2007-03-07
申请人： Amit Ramchandran
发明人： Amit Ramchandran
IPC分类号： G06F12/00
CPC分类号： G06F13/287 , G06F9/30014 , G06F9/3012 , G06F9/3824 , G06F9/3826 , G06F9/383 , G06F9/3867 , G06F9/3885 , G06F13/16
摘要： A method for compressing a set of instructions in an adaptive computing machine includes identifying frequently executed instructions, inserting an explicit caching instruction associating the identified instructions with an index value in the set of instructions before the identified instructions and replacing at least one instance of the frequently executed instructions subsequent to the explicit caching instruction with a compressed instruction referencing the index value. One or more instructions can be identified for compression, including groups of consecutive or non-consecutive instructions. The explicit caching instruction directs a node in an adaptive computing machine to store instructions in an instruction storage unit in association with an index value. Instructions stored in the storage unit are retrievable with reference to the index value. The compressed instruction may include one or more references to index values, and can include a sequence of index values indicating the sequence of execution of the associated instructions.
摘要翻译：一种用于在自适应计算机器中压缩一组指令的方法包括识别频繁执行的指令，将识别出的指令与所识别的指令之前的指令集中的索引值相关联的显式高速缓存指令，并将所述指令的至少一个实例在显式高速缓存指令之后的执行指令具有引用索引值的压缩指令。可以识别一个或多个指令用于压缩，包括连续或非连续指令的组。显式高速缓存指令引导自适应计算机中的节点将指令存储在与索引值相关联的指令存储单元中。存储在存储单元中的指令可以参考索引值进行检索。压缩指令可以包括对索引值的一个或多个引用，并且可以包括指示相关联指令的执行顺序的索引值序列。

3. 发明授权

US08380884B2 Adaptable datapath for a digital processing system 有权
公开(公告)号：US08380884B2
公开(公告)日：2013-02-19
申请号：US13042391
申请日：2011-03-07
申请人： Amit Ramchandran
发明人： Amit Ramchandran
IPC分类号： G06F3/00
CPC分类号： G06F13/287 , G06F9/30014 , G06F9/3012 , G06F9/3824 , G06F9/3826 , G06F9/383 , G06F9/3867 , G06F9/3885 , G06F13/16
摘要： The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided.

4. 发明申请

US20110131393A1 Programmable processor architecture 有权
标题翻译：可编程处理器架构
公开(公告)号：US20110131393A1
公开(公告)日：2011-06-02
申请号：US12782431
申请日：2010-05-18
申请人： Amit Ramchandran , John Reid Hauser, JR.
发明人： Amit Ramchandran , John Reid Hauser, JR.
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/3877 , G06F1/3203 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/3824 , G06F9/3828 , G06F9/3885 , G06F9/3895 , G06F15/781 , G06F15/7842 , G06F15/7867 , G06F15/8053
摘要： One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.
摘要翻译：本发明的一个实施例包括具有能够并行处理W比特的至少一个W型子处理器的异构高性能可扩展处理器，W是整数值，至少一个N型子处理器能够并行处理N位，N是小于W的整数值2。所述处理器还包括耦合所述至少一个W型子处理器的共享总线和耦合到所述至少一个W型子处理器和所述至少一个N-型子处理器的至少一个N型子处理器和存储器，型子处理器，其中W型子处理器重新排列存储器以适应允许快速操作的应用的执行。

5. 发明授权

US07568086B2 Cache for instruction set architecture using indexes to achieve compression 有权
标题翻译：缓存指令集架构使用索引来实现压缩
公开(公告)号：US07568086B2
公开(公告)日：2009-07-28
申请号：US11683026
申请日：2007-03-07
申请人： Amit Ramchandran
发明人： Amit Ramchandran
IPC分类号： G06F9/06
CPC分类号： G06F13/287 , G06F9/30014 , G06F9/3012 , G06F9/3824 , G06F9/3826 , G06F9/383 , G06F9/3867 , G06F9/3885 , G06F13/16
摘要： A method for compressing a set of instructions in an adaptive computing machine includes identifying frequently executed instructions, inserting an explicit caching instruction associating the identified instructions with an index value in the set of instructions before the identified instructions and replacing at least one instance of the frequently executed instructions subsequent to the explicit caching instruction with a compressed instruction referencing the index value. One or more instructions can be identified for compression, including groups of consecutive or non-consecutive instructions. The explicit caching instruction directs a node in an adaptive computing machine to store instructions in an instruction storage unit in association with an index value. Instructions stored in the storage unit are retrievable with reference to the index value. The compressed instruction may include one or more references to index values, and can include a sequence of index values indicating the sequence of execution of the associated instructions.
摘要翻译：一种用于在自适应计算机器中压缩一组指令的方法包括识别频繁执行的指令，将识别出的指令与所识别的指令之前的指令集中的索引值相关联的显式高速缓存指令，并将所述指令的至少一个实例在显式高速缓存指令之后的执行指令具有引用索引值的压缩指令。可以识别一个或多个指令用于压缩，包括连续或非连续指令的组。显式高速缓存指令引导自适应计算机中的节点将指令存储在与索引值相关联的指令存储单元中。存储在存储单元中的指令可以参考索引值进行检索。压缩指令可以包括对索引值的一个或多个引用，并且可以包括指示相关联指令的执行顺序的索引值序列。

6. 发明申请

US20070198901A1 CONFIGURABLE INTERFACE FOR CONNECTING VARIOUS CHIPSETS FOR WIRELESS COMMUNICATION TO A PROGRAMMABLE (MULTI-)PROCESSOR 审中-公开
标题翻译：用于将无线通信的各种连接器连接到可编程（多）处理器的可配置接口
公开(公告)号：US20070198901A1
公开(公告)日：2007-08-23
申请号：US11733707
申请日：2007-04-10
申请人： Amit Ramchandran , John Hauser , Adam Lins
发明人： Amit Ramchandran , John Hauser , Adam Lins
IPC分类号： H03M13/00
CPC分类号： G06F7/724 , G06F9/30032 , G06F9/30036 , G06F9/3877 , G06F9/3885 , H03M13/00 , H03M13/158 , H03M13/27 , H03M13/2957 , H03M13/6508 , H03M13/6569
摘要： Among the embodiments of the present invention, one of the embodiment thereof includes a heterogeneous, high-performance, scalable processor including at least one W-type sub-processor capable of processing W bits, or more, in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than W, a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor; and at least one Galois Field (GF) MAC coupled to communicate with the W-type sub-processor and the N-type sub-processor, wherein the W-type sub-processor rearranges bytes in transit to or from memory to accommodate execution of applications allowing for fast operations.
摘要翻译：在本发明的实施例中，其一个实施例包括异构的，高性能的，可扩展的处理器，包括至少一个能够处理W位或更多并行的W型子处理器，W是整数值至少一个能并行处理N个比特的N型子处理器，N是一个整数值，其中小于W，耦合至少一个W型子处理器的共享总线和至少一个N型子处理器以及耦合到与W型子处理器和N型子处理器通信的至少一个伽罗瓦域（GF）MAC，其中W型子处理器重新排列到存储器或从存储器传输的字节，以适应允许快速操作的应用程序。

7. 发明授权

US07194605B2 Cache for instruction set architecture using indexes to achieve compression 有权
标题翻译：缓存指令集架构使用索引来实现压缩
公开(公告)号：US07194605B2
公开(公告)日：2007-03-20
申请号：US10628083
申请日：2003-07-24
申请人： Amit Ramchandran
发明人： Amit Ramchandran
IPC分类号： G06F9/312
CPC分类号： G06F13/287 , G06F9/30014 , G06F9/3012 , G06F9/3824 , G06F9/3826 , G06F9/383 , G06F9/3867 , G06F9/3885 , G06F13/16
摘要： A method for compressing a set of instructions in an adaptive computing machine includes identifying frequently executed instructions, inserting an explicit caching instruction associating the identified instructions with an index value in the set of instructions before the identified instructions and replacing at least one instance of the frequently executed instructions subsequent to the explicit caching instruction with a compressed instruction referencing the index value. One or more instructions can be identified for compression, including groups of consecutive or non-consecutive instructions. The explicit caching instruction directs a node in an adaptive computing machine to store instructions in an instruction storage unit in association with an index value. Instructions stored in the storage unit are retrievable with reference to the index value. The compressed instruction may include one or more references to index values, and can include a sequence of index values indicating the sequence of execution of the associated instructions.
摘要翻译：一种用于在自适应计算机器中压缩一组指令的方法包括识别频繁执行的指令，将识别出的指令与所识别的指令之前的指令集中的索引值相关联的显式高速缓存指令，并将所述指令的至少一个实例在显式高速缓存指令之后的执行指令具有引用索引值的压缩指令。可以识别一个或多个指令用于压缩，包括连续或非连续指令的组。显式高速缓存指令引导自适应计算机中的节点将指令存储在与索引值相关联的指令存储单元中。存储在存储单元中的指令可以参考索引值进行检索。压缩指令可以包括对索引值的一个或多个引用，并且可以包括指示相关联指令的执行顺序的索引值序列。

8. 发明申请

US20060026578A1 Programmable processor architecture hirarchical compilation 审中-公开
标题翻译：可编程处理器架构编译
公开(公告)号：US20060026578A1
公开(公告)日：2006-02-02
申请号：US11195429
申请日：2005-08-02
申请人： Amit Ramchandran , John Hauser
发明人： Amit Ramchandran , John Hauser
IPC分类号： G06F9/45
CPC分类号： G06F9/3877 , G06F1/3203 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/3824 , G06F9/3828 , G06F9/3885 , G06F9/3895 , G06F15/781 , G06F15/7842 , G06F15/7867 , G06F15/8053
摘要： One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits or greater in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than W. A scenario compiler is included in a hierarchical flow of compilation and used with other compilation and assembler blocks to generate binary code based on different types of codes to allow for efficient processing based on the sub-processors while maintaining low power consumption when the binary code is executed.
摘要翻译：本发明的一个实施例包括具有至少一个能够并行处理W位或更大的W型子处理器的异质，高性能，可扩展的处理器，W是整数值，至少一个N型子处理器能够并行处理N位，N是小于W的整数值。场景编译器包含在编译的分级流中，并与其他编译和汇编程序块一起使用，以根据不同类型的代码生成二进制代码，以允许用于基于子处理器的有效处理，同时在执行二进制代码时保持低功耗。

9. 发明申请

US20140236810A1 METHOD AND SYSTEM FOR DETERMINING MOST REWARDING CHOICE OF PAYMENT AT A POINT-OF-SALE 审中-公开
标题翻译：确定销售点付款最重要选择的方法和系统
公开(公告)号：US20140236810A1
公开(公告)日：2014-08-21
申请号：US14124466
申请日：2012-06-16
申请人： Amit Ramchandran , Amir Masoud Zarkesh , Saeid Ghafouri
发明人： Amit Ramchandran , Amir Masoud Zarkesh , Saeid Ghafouri
IPC分类号： G06Q20/22
CPC分类号： G06Q20/227 , G06Q20/12 , G06Q20/20 , G06Q20/22
摘要： A system, method and computer program product for processing payments, including a server in an electronic device and/or a server in a remote location; a database in the electronic device and/or a database in a remote location coupled to the respective server; and an electronic device of a consumer coupled to the server over a communications network, wherein the server is configured to determine a payment option most advantageous to the consumer based on information stored in the database regarding a plurality of payment options available to the consumer, and the server is configured to display the most advantageous payment option to the consumer on the electronic device of the consumer.
摘要翻译：一种用于处理支付的系统，方法和计算机程序产品，包括电子设备中的服务器和/或远程位置的服务器; 电子设备中的数据库和/或耦合到相应服务器的远程位置的数据库; 以及通过通信网络耦合到所述服务器的消费者的电子设备，其中所述服务器被配置为基于存储在所述数据库中的关于消费者可用的多个支付选项的信息来确定对所述消费者最有利的支付选项，以及服务器被配置为在消费者的电子设备上向消费者显示最有利的支付选项。

10. 发明授权

US08386751B2 Low power, high performance, heterogeneous, scalable processor architecture 有权
标题翻译：低功耗，高性能，异构，可扩展的处理器架构
公开(公告)号：US08386751B2
公开(公告)日：2013-02-26
申请号：US12782431
申请日：2010-05-18
申请人： Amit Ramchandran , John Reid Hauser, Jr.
发明人： Amit Ramchandran , John Reid Hauser, Jr.
IPC分类号： G06F15/76
CPC分类号： G06F9/3877 , G06F1/3203 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/3824 , G06F9/3828 , G06F9/3885 , G06F9/3895 , G06F15/781 , G06F15/7842 , G06F15/7867 , G06F15/8053
摘要： One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.
摘要翻译：本发明的一个实施例包括具有能够并行处理W比特的至少一个W型子处理器的异构高性能可扩展处理器，W是整数值，至少一个N型子处理器能够并行处理N位，N为小于W的整数值2倍。所述处理器还包括耦合所述至少一个W型子处理器的共享总线和耦合到所述至少一个W型子处理器和所述至少一个N-型子处理器的至少一个N型子处理器和存储器，型子处理器，其中W型子处理器重新排列存储器以适应允许快速操作的应用的执行。

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