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41. 发明申请

US20020053692A1 DRAM cell having storage capacitor contact self-aligned to bit lines and word lines 失效
公开(公告)号：US20020053692A1
公开(公告)日：2002-05-09
申请号：US10007110
申请日：2001-12-03
申请人： Alliance Semiconductor Corporation
发明人： Ritu Shrivastava , Chitranjan N. Reddy
IPC分类号： H01L029/76 , H01L029/94 , H01L031/119 , H01L021/8242
CPC分类号： H01L27/10852
摘要： A DRAM cell (10) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines (24) and bit lines (28) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer (46) that extends over a source region (18). A first interlayer dielectric (ILD) (48) insulates the word lines (24) from the bit lines (28) and a second ILD (60) insulates the bit lines from a cell capacitor. A capacitor contact hole (34), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs (48 and 60) to expose the etch barrier layer (46) over the source region (18). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures. The exposed etch barrier layer (46) over the source region (18) is cleared and a storage capacitor is formed having a contact that extends into the contact hole to make contact with the source region (18).

42. 发明授权

US6141236A Interleaved stitch using segmented word lines 有权
标题翻译：使用分段字线的交错针迹
公开(公告)号：US6141236A
公开(公告)日：2000-10-31
申请号：US266175
申请日：1999-03-10
申请人： Subramani Kengeri
发明人： Subramani Kengeri
IPC分类号： G11C8/14 , G11C11/408 , G11C11/4097 , G11C5/06
CPC分类号： G11C8/14 , G11C11/408 , G11C11/4097
摘要： A word line stitch mechanism to be used in high-density DRAMs is presented herein. The word line stitch mechanism of the present invention eliminates the problem caused by using the conventional word line stitch methods of the prior art in the high-density DRAMs. In the present invention, the word lines are segmented with an space between the two adjacent word line segments. Thereafter, the contacts between the word line segments and the associated metal layers are established such that the contact overlap areas are completely adjacent to all or a portion of the spaces between the word line segments of the adjacent word lines.
摘要翻译：本文提出了用于高密度DRAM的字线缝合机构。本发明的字线缝合机构消除了在高密度DRAM中使用现有技术的常规字线缝合方法所引起的问题。在本发明中，字线被划分成两个相邻字线段之间的空间。此后，字线段和相关联的金属层之间的接触被建立成使得接触重叠区域完全邻近相邻字线的字线段之间的空间的全部或一部分。

43. 发明授权

US5747868A Laser fusible link structure for semiconductor devices 失效
标题翻译：用于半导体器件的激光熔丝连接结构
公开(公告)号：US5747868A
公开(公告)日：1998-05-05
申请号：US494890
申请日：1995-06-26
申请人： Chitranjan N. Reddy , Ajit K. Medhekar
发明人： Chitranjan N. Reddy , Ajit K. Medhekar
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5258 , H01L2924/0002
摘要： An improved laser fusible link structure for semiconductor devices (200) and method of manufacturing thereof (10) is disclosed. A first conductive layer is patterned to create a laser fuse (202) and then covered with a first dielectric layer (212). An etch mask layer, in the preferred embodiment a second layer of polysilicon, is deposited and patterned to form a fuse etch mask (214) directly over the laser fuse (202). The fuse etch mask (214) has a width that is smaller than a minimum laser spot size, but large enough to protect the laser fuse (202) from fuse window over-etch, taking into account any potential misalignment between the laser fuse (202) and the fuse etch mask (214).
摘要翻译：公开了一种用于半导体器件（200）的改进的激光熔丝连接结构及其制造方法（10）。图案化第一导电层以产生激光熔丝（202），然后用第一介电层（212）覆盖。在优选实施例中，蚀刻掩模层被沉积并图案化以在激光熔丝（202）的正上方形成熔丝蚀刻掩模（214）。保险丝蚀刻掩模（214）具有小于最小激光光斑尺寸的宽度，但足够大以保护激光熔丝（202）免受熔丝窗口过蚀刻，考虑到激光熔丝（202）之间的任何潜在的未对准）和熔丝蚀刻掩模（214）。

44. 发明授权

US5672535A Method of fabricating DRAM cell with self-aligned contact 失效
标题翻译：制造具有自对准接触的DRAM单元的方法
公开(公告)号：US5672535A
公开(公告)日：1997-09-30
申请号：US654615
申请日：1996-05-29
申请人： Ritu Shrivastava , C. N. Reddy
发明人： Ritu Shrivastava , C. N. Reddy
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10808 , Y10S438/979
摘要： A structure and method are provided for reducing DRAM cell area by eliminating the contact-to-gate spacing requirement while increasing the capacitor area by designing the capacitor to extend inside the contact, without sacrificing the sidewall capacitance. The new structure uses a self-aligned contact where the contact can overlap the gate region in the layout.
摘要翻译：提供了一种结构和方法，用于通过在不牺牲侧壁电容的情况下将电容器设计成在触点内延伸而增加电容器面积来消除接触栅极间隔要求而减小DRAM单元面积。新结构使用自对准触点，触点可以与布局中的栅极区域重叠。

45. 发明授权

US5633832A Reduced area word line driving circuit for random access memory 失效
标题翻译：用于随机存取存储器的减少区域字线驱动电路
公开(公告)号：US5633832A
公开(公告)日：1997-05-27
申请号：US533755
申请日：1995-09-26
申请人： Vipul C. Patel , Kenneth A. Poteet , Chitranjan N. Reddy
发明人： Vipul C. Patel , Kenneth A. Poteet , Chitranjan N. Reddy
IPC分类号： G11C8/08 , G11C8/10 , G11C7/00
CPC分类号： G11C8/10 , G11C8/08
摘要： A word line driver circuit (10) for driving four word lines (18) is disclosed. In a preferred embodiment, the word line driver circuit (10) includes a decoder circuit (12) for pulling a decode node (20) to a logic low level (Vss) in response to internal row decode signals, a pull-up circuit (14) for pulling the decode node (20) to a logic high (Vcc) to deselect the word lines (18), four transfer transistors (NO) intermediate the decode node (20) and four control nodes (22), four CMOS inverters (18), each driving one word line (18) between a boost voltage and Vss. A PMOS level shifter transistor (P0) is associated with each inverter (18), and has a channel width that is small relative to both the channel widths of the transfer transistors (N0) and to the devices making up the decoder circuit (12), allowing the level shifter transistors (P0) to be overpowered by the decoder circuit (12). The channel width of the inverter NMOS transistors (N2) are relatively large in relation to the inverter PMOS transistors (P2), allowing the NMOS transistors (N2) to be turned on by a voltage of Vcc-Vtn, where Vtn is the threshold voltage of the transfer transistors (N0).
摘要翻译：公开了用于驱动四个字线（18）的字线驱动电路（10）。在优选实施例中，字线驱动电路（10）包括用于响应于内部行解码信号将解码节点（20）拉到逻辑低电平（Vss）的解码器电路（12），上拉电路 14），用于将解码节点（20）拉到逻辑高（Vcc）以取消选择字线（18），解码节点（20）和四个控制节点（22）之间的四个传输晶体管（NO），四个CMOS反相器（18），每个在升压电压和Vss之间驱动一个字线（18）。 PMOS电平移位晶体管（P0）与每个反相器（18）相关联，并且具有相对于传输晶体管（N0）的沟道宽度和构成解码器电路（12）的器件的沟道宽度小的沟道宽度，，允许电平移位器晶体管（P0）由解码器电路（12）过载。逆变器NMOS晶体管（N2）的沟道宽度相对于反相器PMOS晶体管（P2）相对较大，允许NMOS晶体管（N2）通过Vcc-Vtn的电压导通，其中Vtn是阈值电压的转移晶体管（N0）。

46. 发明授权

US5548560A Synchronous static random access memory having asynchronous test mode 失效
标题翻译：具有异步测试模式的同步静态随机存取存储器
公开(公告)号：US5548560A
公开(公告)日：1996-08-20
申请号：US423822
申请日：1995-04-19
申请人： Michael C. Stephens, Jr. , Ajit K. Medhekar , Chitranjan N. Reddy
发明人： Michael C. Stephens, Jr. , Ajit K. Medhekar , Chitranjan N. Reddy
IPC分类号： G11C7/22 , G11C8/18 , G11C8/00
CPC分类号： G11C7/22 , G11C8/18
摘要： A burst mode static random access memory (SRAM) (10) is disclosed that includes an address transition detect signal (ATD) generating circuit (14) that provides either an asynchronous ATD signal (a-ATD) or a synchronous ATD signal (s-ATD) depending upon the logic state of a mode signal (ATM). A rising edge of the a-ATD signal is generated by a change in address. A falling edge is generated after a predetermined time period according an a-ATD circuit (60) within the ATD generating circuit (14). A falling edge of the s-ATD signal is generated by a rising edge of an internal synchronous clock pulse (CLAT). The rising edge of the s-ATD signal is generated when data are sensed on data lines (40) by an end-of-cycle circuit (20). If ATM is high, the a-ATD signal is used for timing on the SRAM (10). If ATM is low, timing is determined according to the s-ATD signal. An ATD control circuit (16) is provided to generate I/O control signals in response to the ATD signal (either s-ATD or a-ATD). On a rising edge of the ATD signal the I/O control signals place the SRAM (10) in a precharge/equalization state wherein I/O lines (24, 32, 40) are equalized and sensing circuits (28, 34) are disabled. On a falling edge of the ATD signal, the SRAM (10) is placed in a read/write mode wherein the I/O lines (24, 32, 40) are ready to sense read data or be driven by written data, and sensing circuits (28, 34) are enabled for a read operation, or alternatively disabled for a write operation.
摘要翻译：公开了一种突发模式静态随机存取存储器（SRAM）（10），其包括地址转换检测信号（ATD）产生电路（14），其提供异步ATD信号（a-ATD）或同步ATD信号（s- ATD），取决于模式信号（ATM）的逻辑状态。 a-ATD信号的上升沿由地址变化产生。根据ATD生成电路（14）内的a-ATD电路（60），在预定时间段之后产生下降沿。 s-ATD信号的下降沿由内部同步时钟脉冲（CLAT）的上升沿产生。当通过循环周期电路（20）在数据线（40）上检测数据时，产生s-ATD信号的上升沿。如果ATM为高电平，则将a-ATD信号用于SRAM（10）上的定时。如果ATM低，则根据s-ATD信号确定定时。提供ATD控制电路（16）以响应于ATD信号（s-ATD或a-ATD）产生I / O控制信号。在ATD信号的上升沿，I / O控制信号将SRAM（10）置于预充电/均衡状态，其中I / O线（24,32,40）被均衡，并且感测电路（28,34）被禁用。在ATD信号的下降沿，SRAM（10）被置于读/写模式，其中I / O线（24,32,40）准备好读取数据或由写入数据驱动，并且感测电路（28,34）被启用用于读取操作，或者替代地禁用写入操作。

47. 发明授权

US5513147A Row driving circuit for memory devices 失效
标题翻译：存储器件的行驱动电路
公开(公告)号：US5513147A
公开(公告)日：1996-04-30
申请号：US359052
申请日：1994-12-19
申请人： Bruce L. Prickett, Jr.
发明人： Bruce L. Prickett, Jr.
IPC分类号： G11C8/08 , G11C16/12 , G11C8/00
CPC分类号： G11C16/12 , G11C8/08
摘要： A row driving circuit (10) having a reduced number of transistors provides range of row deselect voltages, and eliminates the need for an NMOS pull-down device. The row driving circuit (10) has a-level shifter (14) formed by a PMOS input pull transistor P1 that is drain coupled at node V 10 to an NMOS input transistor N1. N1 functions as passgate for a row select signal and inverted row select signal applied to its gate and source respectively. A PMOS row pull-up transistor P2 has its gate coupled to V 10, its source coupled to a variable positive supply voltage (12), and its drain coupled to the source of a PMOS row select transistor P3. The drain and gate of P3 are coupled to switching circuits S 11 and S 12 respectively. S 11 and S 12 provide gate and drain voltages to quickly deselect the row by pulling the row to a negative deselect voltage. A PMOS erase transistor is also source coupled to the row with its gate coupled to switching circuit S 13 and its drain coupled to switching circuit S14. S13 and S14 provide a negative erase voltage to both the gate and drain of P4. In addition, S13 and S 14 can bias P4 into linear mode, allowing P4 to operate a leaker transistor, pulling the row down to a deselect voltage.
摘要翻译：具有减少数量的晶体管的行驱动电路（10）提供行取消电压的范围，并且不需要NMOS下拉器件。行驱动电路（10）具有由PMOS输入拉电流晶体管P1形成的电平移位器（14），其在节点V 10处漏极耦合到NMOS输入晶体管N1。 N1用作分别用于其栅极和源极的行选择信号和反相行选择信号的通道。 PMOS行上拉晶体管P2的栅极耦合到V10，其源极耦合到可变的正电源电压（12），其漏极耦合到PMOS排选择晶体管P3的源极。 P3的漏极和栅极分别耦合到开关电路S11和S12。 S 11和S 12提供栅极和漏极电压，以通过将行拉取到负的取消选择电压来快速地取消行。 PMOS擦除晶体管也源耦合到该行，其栅极耦合到开关电路S13，其漏极耦合到开关电路S14。 S13和S14为P4的栅极和漏极提供一个负的擦除电压。此外，S13和S14可以将P4偏置为线性模式，允许P4操作漏电晶体管，将该行拉至取消选择电压。

48. 发明申请

US20010040581A1 Shared memory graphics accelerator system 审中-公开
标题翻译：共享内存图形加速器系统
公开(公告)号：US20010040581A1
公开(公告)日：2001-11-15
申请号：US09911516
申请日：2001-07-25
申请人： Alliance Semiconductor Corporation
发明人： Chitranjan N. Reddy
IPC分类号： G06F015/167
CPC分类号： G09G5/363 , G06T1/60 , G06T2200/28 , G09G5/39
摘要： A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-chip frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.
摘要翻译：向显示器提供图形显示数据的共享存储器图形加速器系统包括用于生成用于处理显示数据的图形显示数据和图形命令的中央处理单元。集成图形显示存储元件包括连接以接收显示数据的图形加速器和来自中央处理单元的图形命令和片上帧缓冲存储器元件。片上帧缓冲存储器元件被连接以经由显示数据分配总线从图形加速器接收显示数据。片外帧缓冲存储器元件也连接到显示数据分配总线，以从图形加速器接收显示数据。图形加速器基于预定的显示数据分布准则选择性地将显示数据分配到片上帧缓冲存储器元件和片外帧缓冲存储器元件。

49. 发明申请

US20010038636A1 Integrated high speed switch router using a multiport architecture 有权
标题翻译：集成高速交换机路由器使用多端口架构
公开(公告)号：US20010038636A1
公开(公告)日：2001-11-08
申请号：US09769929
申请日：2001-01-24
申请人： Alliance Semiconductor Corporation
发明人： Bhanu Nanduri , Chitranjan N. Reddy
IPC分类号： H04L012/28
CPC分类号： H04L49/103 , H04L49/201
摘要： A switch/router circuit integrates a multi-port memory array with the Media Access Control (MAC) units to facilitate direct transfer of packet payloads to the destination port. The store and forward functions are performed using a single memory cell with multiple pass gates, one pass gate designated for each MAC port. That is, a switch router is implemented using the multi-port memory array such that the number of ports in each memory cell is proportional to the number of MACs integrated in the single monolithic chip. An arbitrator arbitrates between the integrated ports, a lookup table identifies the destination port and a system controller controls all of the integrated elements.
摘要翻译：交换机/路由器电路将多端口存储器阵列与媒体访问控制（MAC）单元集成，以便于将分组有效载荷直接传送到目的地端口。存储和转发功能使用具有多个通过门的单个存储器单元执行，每个MAC端口指定一个通过门。也就是说，使用多端口存储器阵列实现交换路由器，使得每个存储器单元中的端口数量与集成在单个单片芯片中的MAC的数量成比例。仲裁员在集成端口之间进行仲裁，查找表标识目的端口，系统控制器控制所有集成元素。

50. 发明授权

US6108250A Fast redundancy scheme for high density, high speed memories 有权
标题翻译：高密度，高速存储器的快速冗余方案
公开(公告)号：US6108250A
公开(公告)日：2000-08-22
申请号：US293494
申请日：1999-04-15
申请人： Subramani Kengeri
发明人： Subramani Kengeri
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/789 , G11C29/84
摘要： A high speed process for determining whether an externally applied address points to a memory cell or a redundant memory cell in a memory is disclosed. Identification information associated with redundant memory rows and columns is stored and compared with decoded information based upon a decoded externally applied address. This comparison determines if a memory cell of a redundant memory cell is addressed.
摘要翻译：公开了用于确定外部施加的地址是指向存储器中的存储器单元还是冗余存储器单元的高速处理。与冗余存储器行和列相关联的识别信息基于解码的外部应用地址被存储并与解码信息进行比较。该比较确定冗余存储器单元的存储单元是否被寻址。

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