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1. 发明授权

US07539590B2 System and method for testing a memory 有权
标题翻译：用于测试内存的系统和方法
公开(公告)号：US07539590B2
公开(公告)日：2009-05-26
申请号：US11403783
申请日：2006-04-13
申请人： Niranjan Behera , Bruce L. Prickett, Jr.
发明人： Niranjan Behera , Bruce L. Prickett, Jr.
IPC分类号： G01R31/00 , G01R31/14
CPC分类号： G11C29/56 , G11C29/54
摘要： A method and apparatus for testing a memory at speed. A test and repair wrapper integrated with a memory instance is operable to receive test information scanned in from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the test and repair wrapper is operable to generate address, data and command signals based on the scanned test information, wherein the signals are used for effectuating one or more tests with respect to the memory instance.
摘要翻译：一种用于以速度测试存储器的方法和装置。与内存实例集成的测试和修复包装器可操作以接收从内置自检和修复（BISTR）处理器扫描的测试信息。与测试和修复包装器相关联的逻辑电路可操作以基于扫描的测试信息产生地址，数据和命令信号，其中所述信号用于实现关于存储器实例的一个或多个测试。

2. 发明授权

US07788551B2 System and method for repairing a memory 有权
标题翻译：用于修复内存的系统和方法
公开(公告)号：US07788551B2
公开(公告)日：2010-08-31
申请号：US12188892
申请日：2008-08-08
申请人： Niranjan Behera , Bruce L. Prickett, Jr. , Yervant Zorian
发明人： Niranjan Behera , Bruce L. Prickett, Jr. , Yervant Zorian
IPC分类号： G06F11/00 , G11C7/00
CPC分类号： G11C29/4401 , G11C29/16 , G11C29/44 , G11C29/848
摘要： A method and system for repairing a memory. A test and repair wrapper is operable to be integrated with input/output (I/O) circuitry of a memory instance to form a wrapper I/O (WIO) block that is operable to receive test and repair information from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the WIO block is operable generate a current error signal that is used locally by the BISTR processor for providing a repair enable control signal in order to repair a faulty memory portion using a redundant memory portion without having to access a post-processing environment for repair signature generation.
摘要翻译：一种用于修复存储器的方法和系统。测试和修复包装器可操作地与存储器实例的输入/输出（I / O）电路集成，以形成可操作以从内置自身接收测试和修复信息的包装器I / O（WIO）块测试和修复（BISTR）处理器。与WIO块相关联的逻辑电路可操作地产生由BISTR处理器本地使用的用于提供修复使能控制信号的电流误差信号，以便使用冗余存储器部分修复故障存储器部分，而不必访问后处理修复签名生成的环境。

3. 发明授权

US07415641B1 System and method for repairing a memory 有权
标题翻译：用于修复内存的系统和方法
公开(公告)号：US07415641B1
公开(公告)日：2008-08-19
申请号：US10702014
申请日：2003-11-05
申请人： Niranjan Behera , Bruce L. Prickett, Jr. , Yervant Zorian
发明人： Niranjan Behera , Bruce L. Prickett, Jr. , Yervant Zorian
IPC分类号： G06F11/00 , G11C7/00
CPC分类号： G11C29/4401 , G11C29/16 , G11C29/44 , G11C29/848
摘要： A method and system for repairing a memory. A test and repair wrapper is operable to be integrated with input/output (I/O) circuitry of a memory instance to form a wrapper I/O (WIO) block that is operable to receive test and repair information from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the WIO block is operable generate a current error signal that is used locally by the BISTR processor for providing a repair enable control signal in order to repair a faulty memory portion using a redundant memory portion without having to access a post-processing environment for repair signature generation.
摘要翻译：一种用于修复存储器的方法和系统。测试和修复包装器可操作地与存储器实例的输入/输出（I / O）电路集成，以形成可操作以从内置自身接收测试和修复信息的包装器I / O（WIO）块测试和修复（BISTR）处理器。与WIO块相关联的逻辑电路可操作地产生由BISTR处理器本地使用的用于提供修复使能控制信号的电流误差信号，以便使用冗余存储器部分修复故障存储器部分，而不必访问后处理修复签名生成的环境。

4. 发明授权

US5513147A Row driving circuit for memory devices 失效
标题翻译：存储器件的行驱动电路
公开(公告)号：US5513147A
公开(公告)日：1996-04-30
申请号：US359052
申请日：1994-12-19
申请人： Bruce L. Prickett, Jr.
发明人： Bruce L. Prickett, Jr.
IPC分类号： G11C8/08 , G11C16/12 , G11C8/00
CPC分类号： G11C16/12 , G11C8/08
摘要： A row driving circuit (10) having a reduced number of transistors provides range of row deselect voltages, and eliminates the need for an NMOS pull-down device. The row driving circuit (10) has a-level shifter (14) formed by a PMOS input pull transistor P1 that is drain coupled at node V 10 to an NMOS input transistor N1. N1 functions as passgate for a row select signal and inverted row select signal applied to its gate and source respectively. A PMOS row pull-up transistor P2 has its gate coupled to V 10, its source coupled to a variable positive supply voltage (12), and its drain coupled to the source of a PMOS row select transistor P3. The drain and gate of P3 are coupled to switching circuits S 11 and S 12 respectively. S 11 and S 12 provide gate and drain voltages to quickly deselect the row by pulling the row to a negative deselect voltage. A PMOS erase transistor is also source coupled to the row with its gate coupled to switching circuit S 13 and its drain coupled to switching circuit S14. S13 and S14 provide a negative erase voltage to both the gate and drain of P4. In addition, S13 and S 14 can bias P4 into linear mode, allowing P4 to operate a leaker transistor, pulling the row down to a deselect voltage.
摘要翻译：具有减少数量的晶体管的行驱动电路（10）提供行取消电压的范围，并且不需要NMOS下拉器件。行驱动电路（10）具有由PMOS输入拉电流晶体管P1形成的电平移位器（14），其在节点V 10处漏极耦合到NMOS输入晶体管N1。 N1用作分别用于其栅极和源极的行选择信号和反相行选择信号的通道。 PMOS行上拉晶体管P2的栅极耦合到V10，其源极耦合到可变的正电源电压（12），其漏极耦合到PMOS排选择晶体管P3的源极。 P3的漏极和栅极分别耦合到开关电路S11和S12。 S 11和S 12提供栅极和漏极电压，以通过将行拉取到负的取消选择电压来快速地取消行。 PMOS擦除晶体管也源耦合到该行，其栅极耦合到开关电路S13，其漏极耦合到开关电路S14。 S13和S14为P4的栅极和漏极提供一个负的擦除电压。此外，S13和S14可以将P4偏置为线性模式，允许P4操作漏电晶体管，将该行拉至取消选择电压。

5. 发明申请

US20080301507A1 System and Method for Repairing a Memory 有权
标题翻译：用于修复内存的系统和方法
公开(公告)号：US20080301507A1
公开(公告)日：2008-12-04
申请号：US12188892
申请日：2008-08-08
申请人： Niranjan Behera , Bruce L. Prickett, JR. , Yervant Zorian
发明人： Niranjan Behera , Bruce L. Prickett, JR. , Yervant Zorian
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/4401 , G11C29/16 , G11C29/44 , G11C29/848
摘要： A method and system for repairing a memory. A test and repair wrapper is operable to be integrated with input/output (I/O) circuitry of a memory instance to form a wrapper I/O (WIO) block that is operable to receive test and repair information from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the WIO block is operable generate a current error signal that is used locally by the BISTR processor for providing a repair enable control signal in order to repair a faulty memory portion using a redundant memory portion without having to access a post-processing environment for repair signature generation.
摘要翻译：一种用于修复存储器的方法和系统。测试和修复包装器可操作地与存储器实例的输入/输出（I / O）电路集成，以形成可操作以从内置自身接收测试和修复信息的包装器I / O（WIO）块测试和修复（BISTR）处理器。与WIO块相关联的逻辑电路可操作地产生由BISTR处理器本地使用的用于提供修复使能控制信号的电流误差信号，以便使用冗余存储器部分修复故障存储器部分，而不必访问后处理修复签名生成的环境。

6. 发明授权

US5856944A Self-converging over-erase repair method for flash EPROM 失效
标题翻译：闪存EPROM的自融合过擦除修复方法
公开(公告)号：US5856944A
公开(公告)日：1999-01-05
申请号：US556402
申请日：1995-11-13
申请人： Bruce L. Prickett, Jr. , Ritu Shrivastava
发明人： Bruce L. Prickett, Jr. , Ritu Shrivastava
IPC分类号： G11C16/34 , G11C7/00
CPC分类号： G11C16/3409 , G11C16/3404
摘要： A method of repairing over-erased flash EPROM cells (10) includes erasing the cells (12) and repairing the cells by a self-converging repair with a control gate bias (14), on a column by column basis. The self-converging repair includes grounding the sources (104) of the cells in a column, applying a pulsed bias voltage to the control gates of the cells (110), and a pulsed positive voltage to the drains of the cells (106). By varying the bias voltage at the control gate, the resulting threshold voltage of the cells after repair can be modulated to be greater than or less than an inherent steady state convergence value. Once one column of cells is repaired, the process is repeated on a subsequent column.
摘要翻译：修复过擦除的闪存EPROM单元（10）的方法包括通过逐列的控制门偏置（14）的自会聚修复来擦除单元（12）并修复单元。自收敛修复包括将列中的单元的源极（104）接地，将脉冲偏置电压施加到单元（110）的控制栅极，以及向单元（106）的漏极施加脉冲正电压。通过改变控制栅极处的偏置电压，可以将修复后的单元的所得到的阈值电压调制成大于或小于固有的稳态收敛值。一旦修复了一列单元格，则在随后的列上重复该过程。

7. 发明授权

US07031866B1 System and method for testing a memory 有权
公开(公告)号：US07031866B1
公开(公告)日：2006-04-18
申请号：US10701545
申请日：2003-11-05
申请人： Niranjan Behera , Bruce L. Prickett, Jr.
发明人： Niranjan Behera , Bruce L. Prickett, Jr.
IPC分类号： G01R31/00 , G01R31/14
CPC分类号： G11C29/56 , G11C29/54
摘要： A method and apparatus for testing a memory at speed. A test and repair wrapper integrated with a memory instance is operable to receive test information scanned in from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the test and repair wrapper is operable to generate address, data and command signals based on the scanned test information, wherein the signals are used for effectuating one or more tests with respect to the memory instance.

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