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41. 发明申请

US20070004132A1 DRAM memory device 有权
标题翻译： DRAM存储器件
公开(公告)号：US20070004132A1
公开(公告)日：2007-01-04
申请号：US11515648
申请日：2006-09-05
申请人： Kunal Parekh , Byron Burgess
发明人： Kunal Parekh , Byron Burgess
IPC分类号： H01L21/8242
CPC分类号： H01L21/76897 , H01L21/76831 , H01L21/76834 , H01L21/76895 , H01L27/10814 , H01L27/10855 , H01L27/10888 , H01L27/10894 , Y10S257/905 , Y10S257/906 , Y10S257/907
摘要： The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact opening between the pair of word lines. Sacrificial plugging material is removed from the bit node contact opening between the pair of word lines, and it is replaced with conductive material that is in electrical connection with the bit node. Thereafter, the conductive material is formed into a bit line.
摘要翻译：本发明包括形成存储器电路的方法。在一个实施方案中，半导体衬底包括一对在其间接收的位节点的字线。在位节点上的绝缘材料内形成位节点接触开口。牺牲性封堵材料形成在一对字线之间的位节点接触开口内。牺牲性封堵材料从一对字线对之间的位节点接触开口移除，并由与位节点电连接的导电材料代替。之后，将导电材料形成为位线。

42. 发明申请

US20060263987A1 Methods of forming fusible devices 审中-公开
标题翻译：形成易熔装置的方法
公开(公告)号：US20060263987A1
公开(公告)日：2006-11-23
申请号：US11496251
申请日：2006-07-31
申请人： Mark Fischer , Zhiping Yin , Thomas Glass , Kunal Parekh , Gurtej Sandhu
发明人： Mark Fischer , Zhiping Yin , Thomas Glass , Kunal Parekh , Gurtej Sandhu
IPC分类号： H01L21/336
CPC分类号： H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a laser fuse. The laser fuse comprises an element comprising a heat conductive material. The fuse also includes an absorption element comprising a material with an adjustable capacity for heat or light absorption that overlays the heat conductive element. The fuse also includes an outer insulating element that overlays and encloses the heat conductive element and the absorption element.
摘要翻译：本发明涉及一种激光熔丝。激光熔丝包括包含导热材料的元件。保险丝还包括吸收元件，该吸收元件包括具有与热传导元件重叠的热或光吸收的可调容量的材料。保险丝还包括覆盖并包围导热元件和吸收元件的外绝缘元件。

43. 发明申请

US20060234469A1 A method of forming semiconductor structures 审中-公开
标题翻译：一种形成半导体结构的方法
公开(公告)号：US20060234469A1
公开(公告)日：2006-10-19
申请号：US11409134
申请日：2006-04-21
申请人： David Dickerson , Richard Lane , Charles Dennison , Kunal Parekh , Mark Fischer , John Zahurak
发明人： David Dickerson , Richard Lane , Charles Dennison , Kunal Parekh , Mark Fischer , John Zahurak
IPC分类号： H01L21/76
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.
摘要翻译：一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物层和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。

44. 发明申请

US20060231528A1 Methods of forming semiconductor constructions 有权
公开(公告)号：US20060231528A1
公开(公告)日：2006-10-19
申请号：US11455023
申请日：2006-06-15
申请人： Werner Juengling , Steven McDonald , Kunal Parekh
发明人： Werner Juengling , Steven McDonald , Kunal Parekh
IPC分类号： B44C1/22 , C23F1/00 , H01L21/461 , H01L21/302
CPC分类号： H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the invention includes methods in which one or more processing steps associated with fabrication and patterning of bond pads and redistribution layers is conducted simultaneously over a fuse box region to form and/or remove materials that are directly over the fuse box region.

45. 发明申请

US20060046355A1 Methods of forming semiconductor constructions 有权
公开(公告)号：US20060046355A1
公开(公告)日：2006-03-02
申请号：US10925793
申请日：2004-08-24
申请人： Kunal Parekh , Chandra Mouli , M. Roberts , Fernando Gonzalez
发明人： Kunal Parekh , Chandra Mouli , M. Roberts , Fernando Gonzalez
IPC分类号： H01L21/00 , H01L21/84 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/76801 , H01L21/76829 , H01L21/76834 , H01L21/823462 , H01L21/823481 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/785
摘要： The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature of greater than or equal to 350° C. while exposing the construction to a deuterium-enriched ambient.

46. 发明申请

US20120314171A1 DISPLAY DEVICES HAVING ELECTROLESSLY PLATED CONDUCTORS AND METHODS 审中-公开
标题翻译：具有电镀导体的显示装置及方法
公开(公告)号：US20120314171A1
公开(公告)日：2012-12-13
申请号：US13155810
申请日：2011-06-08
申请人： Anurag Jindal , Kunal Parekh , Prashant Raghu , Nicolai Petrov , Mark Meldrim
发明人： Anurag Jindal , Kunal Parekh , Prashant Raghu , Nicolai Petrov , Mark Meldrim
IPC分类号： G02F1/1343 , H01L33/60 , H01L33/42
CPC分类号： G02F1/133553
摘要： In one or more embodiments, display devices having electrolessly plated conductors and methods are disclosed. One such embodiment is directed to a method of forming a reflective pixel array for a display device, including forming a plurality of conductive pads, each of the conductive pads corresponding to a reflective pixel, and electrolessly plating each of the conductive pads with a reflective conductor.
摘要翻译：在一个或多个实施例中，公开了具有无电镀导体和方法的显示装置。一个这样的实施例涉及一种形成用于显示装置的反射像素阵列的方法，包括形成多个导电焊盘，每个导电焊盘对应于反射像素，并用反射导体无电镀敷每个导电焊盘。

47. 发明申请

US20110220994A1 Method of Forming a DRAM Array of Devices with Vertically Integrated Recessed Access Device and Digitline 有权
标题翻译：形成具有垂直集成嵌入式接入设备和数字线的设备的DRAM阵列的方法
公开(公告)号：US20110220994A1
公开(公告)日：2011-09-15
申请号：US12721373
申请日：2010-03-10
申请人： Kunal Parekh , Ceredig Roberts , Thy Tran , Jim Jozwiak , David Hwang
发明人： Kunal Parekh , Ceredig Roberts , Thy Tran , Jim Jozwiak , David Hwang
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L27/10891 , H01L27/108 , H01L27/10882 , H01L27/10885
摘要： A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.
摘要翻译：公开了一种用于形成具有埋设的访问线（例如字线）和布置在垂直单元触点下方的掩埋数据/感测线（例如，数字线）的存储器件的方法。掩埋字线可以在沿第一方向延伸的衬底中形成沟槽，并且掩埋的数字线可以由垂直于第一方向的第二方向延伸的衬底中的沟槽形成。埋置的数字线可以通过设置在数字线和硅衬底之间的数字线接触件耦合到硅侧壁。

48. 发明申请

US20100003782A1 Methods Of Forming A Non-Volatile Resistive Oxide Memory Cell And Methods Of Forming A Non-Volatile Resistive Oxide Memory Array 有权
标题翻译：形成非易失性电阻氧化物记忆单元的方法和形成非易失性电阻氧化物存储器阵列的方法
公开(公告)号：US20100003782A1
公开(公告)日：2010-01-07
申请号：US12166604
申请日：2008-07-02
申请人： Nishant Sinha , John Smythe , Bhaskar Srinivasan , Gurtej Sandhu , Neil Greeley , Kunal Parekh
发明人： Nishant Sinha , John Smythe , Bhaskar Srinivasan , Gurtej Sandhu , Neil Greeley , Kunal Parekh
IPC分类号： H01L21/16
CPC分类号： H01L45/1683 , H01L27/2472 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.
摘要翻译：形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。含金属氧化物的材料形成在第一导电电极上。蚀刻停止材料沉积在包含金属氧化物的材料上。导电材料沉积在蚀刻停止材料上。包含所接收的导电材料的存储单元的第二导电电极形成在蚀刻停止材料上。这样包括通过导电材料蚀刻以相对于蚀刻停止材料停止并且形成非易失性电阻氧化物存储单元，以包括具有包含金属氧化物的材料和其间的蚀刻停止材料的第一和第二导电电极。考虑其他实现。

49. 发明授权

US07341906B2 Method of manufacturing sidewall spacers on a memory device, and device comprising same 有权
公开(公告)号：US07341906B2
公开(公告)日：2008-03-11
申请号：US11132472
申请日：2005-05-19
申请人： David K. Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
发明人： David K. Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
IPC分类号： H01L21/8244
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11543
摘要： The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.

50. 发明申请

US20070262395A1 Memory cell access devices and methods of making the same 审中-公开
标题翻译：存储单元访问设备及其制作方法
公开(公告)号：US20070262395A1
公开(公告)日：2007-11-15
申请号：US11432442
申请日：2006-05-11
申请人： Jasper Gibbons , Darren Young , Kunal Parekh , Casey Smith
发明人： Jasper Gibbons , Darren Young , Kunal Parekh , Casey Smith
IPC分类号： H01L29/94
CPC分类号： H01L29/4236 , H01L21/823425 , H01L21/82345 , H01L29/407 , H01L29/66621 , H01L29/7831
摘要： Planar access transistor devices and recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are electrically isolated from each other and supplied with two or more voltage supplies, or materials that create a diode junction within the gate electrode. Access device drivers are also provided which are capable of driving distinct or identical voltages to the gate electrodes.
摘要翻译：与半导体器件一起使用的平面存取晶体管器件和凹槽存取晶体管器件可以包括具有多个功函数的材料的栅电极，彼此电隔离并且被提供有两个或更多个电压源的材料，或在其内产生二极管结的材料栅电极。还提供了能够驱动与栅电极不同或相同电压的访问设备驱动器。

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