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41. 发明授权

US06259136B1 High-breakdown-voltage semiconductor device 有权
标题翻译：高击穿电压半导体器件
公开(公告)号：US06259136B1
公开(公告)日：2001-07-10
申请号：US09323552
申请日：1999-06-01
申请人： Yusuke Kawaguchi , Akio Nakagawa , Kozo Kinoshita
发明人： Yusuke Kawaguchi , Akio Nakagawa , Kozo Kinoshita
IPC分类号： H01L2976
CPC分类号： H01L29/0847 , H01L27/088 , H01L27/0922 , H01L29/0878 , H01L29/42368 , H01L29/7816 , H01L29/7835
摘要： A high-breakdown-voltage semiconductor device has a first offset layer and a second offset layer the dosage of which is higher than that of the first offset layer. When the gate is in the ON state, the first offset layer functions as a resurf layer. When the gate is in the OFF state, part of the charge in the first offset layer is neutralized by a drain current flowing through an element having a low ON-resistance, however, the second offset layer functions as a resurf layer. When the drain current is [Acm−1], the amount of charge of electrons is q[C], and the drift speed of carriers is &ugr;drift[cms−1], the dosage n2 of the second offset layer is given by n2≧ ID/(q&ugr;drift)[cms−2].
摘要翻译：高耐压半导体器件具有第一偏移层和第二偏移层，其剂量高于第一偏移层的掺杂层。当门处于ON状态时，第一个偏移层用作resurf层。当栅极处于截止状态时，第一偏移层中的电荷的一部分被流过具有低导通电阻的元件的漏极电流中和，然而，第二偏移层用作复现层。当漏极电流为[Acm-1]时，电子的电荷量为q [C]，载流子的漂移速度为漂移[cms-1]，第二偏移层的剂量n2由 n2> = ID /（q＆ugr; drift）[cms-2]。

42. 发明授权

US08049270B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08049270B2
公开(公告)日：2011-11-01
申请号：US11924175
申请日：2007-10-25
申请人： Miwako Akiyama , Akio Nakagawa , Yusuke Kawaguchi , Syotaro Ono , Yoshihiro Yamaguchi
发明人： Miwako Akiyama , Akio Nakagawa , Yusuke Kawaguchi , Syotaro Ono , Yoshihiro Yamaguchi
IPC分类号： H01L29/732
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/1095 , H01L29/41766
摘要： This semiconductor device an epitaxial layer of a first conductivity type formed on a surface of the first semiconductor layer, and a base layer of a second conductivity type formed on a surface of the epitaxial layer. A diffusion layer of a first conductivity type is selectively formed in the base layer, and a trench penetrates the base layer to reach the epitaxial layer. A gate electrode is formed in the trench through the gate insulator film formed on the inner wall of the trench. A first buried diffusion layer of a second conductivity type is formed in the epitaxial layer deeper than the bottom of the gate electrode. A second buried diffusion layer connects the first buried diffusion layer and the base layer and has a resistance higher than that of the first buried diffusion layer.
摘要翻译：该半导体器件形成在第一半导体层的表面上的第一导电类型的外延层和形成在外延层的表面上的第二导电类型的基极层。在基底层中选择性地形成第一导电类型的扩散层，并且沟槽穿透基底层以到达外延层。通过形成在沟槽内壁上的栅极绝缘膜，在沟槽中形成栅电极。在比栅电极的底部更深的外延层中形成第二导电类型的第一掩埋扩散层。第二掩埋扩散层连接第一掩埋扩散层和基底层，并且具有比第一掩埋扩散层的电阻高的电阻。

43. 发明授权

US07514783B2 Semiconductor module 失效
公开(公告)号：US07514783B2
公开(公告)日：2009-04-07
申请号：US11214730
申请日：2005-08-31
申请人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
发明人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
IPC分类号： H01L23/34
CPC分类号： H01L23/3121 , H01L21/565 , H01L23/36 , H01L23/367 , H01L23/4822 , H01L23/49805 , H01L23/49844 , H01L24/16 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/84 , H01L25/0655 , H01L25/165 , H01L29/4175 , H01L29/7802 , H01L29/7806 , H01L29/7809 , H01L29/7813 , H01L29/7835 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40225 , H01L2224/73153 , H01L2224/73204 , H01L2224/73253 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.

44. 发明申请

US20070257708A1 SEMICONDUCTOR MODULE 失效
标题翻译：半导体模块
公开(公告)号：US20070257708A1
公开(公告)日：2007-11-08
申请号：US11778516
申请日：2007-07-16
申请人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
发明人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
IPC分类号： H03D13/00
CPC分类号： H01L23/3121 , H01L21/565 , H01L23/36 , H01L23/367 , H01L23/4822 , H01L23/49805 , H01L23/49844 , H01L24/16 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/84 , H01L25/0655 , H01L25/165 , H01L29/4175 , H01L29/7802 , H01L29/7806 , H01L29/7809 , H01L29/7813 , H01L29/7835 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40225 , H01L2224/73153 , H01L2224/73204 , H01L2224/73253 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.
摘要翻译：半导体模块包括安装板。多个电源开关器件芯片通过倒装芯片接合安装在安装板上。芯片具有上表面和下表面，并且被配置为面向安装板的上表面。通过倒装芯片接合将驱动IC芯片安装在安装板上。驱动IC芯片用于驱动形成在多个功率开关器件芯片中的晶体管的栅极。多个散热构件分别位于多个功率开关器件芯片的下表面上。提供树脂构件以将单个封装中的多个功率开关器件芯片和驱动IC芯片密封。

45. 发明申请

US20070257376A1 SEMICONDUCTOR MODULE 审中-公开
公开(公告)号：US20070257376A1
公开(公告)日：2007-11-08
申请号：US11778493
申请日：2007-07-16
申请人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
发明人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
IPC分类号： H01L23/48
CPC分类号： H01L23/3121 , H01L21/565 , H01L23/36 , H01L23/367 , H01L23/4822 , H01L23/49805 , H01L23/49844 , H01L24/16 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/84 , H01L25/0655 , H01L25/165 , H01L29/4175 , H01L29/7802 , H01L29/7806 , H01L29/7809 , H01L29/7813 , H01L29/7835 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40225 , H01L2224/73153 , H01L2224/73204 , H01L2224/73253 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.

46. 发明授权

US07061047B2 Semiconductor device having trench gate structure and manufacturing method thereof 有权
公开(公告)号：US07061047B2
公开(公告)日：2006-06-13
申请号：US10682111
申请日：2003-10-10
申请人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
发明人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L29/772
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/267 , H01L29/42368 , H01L29/4933
摘要： A vertical MOSFET includes a base region formed on a drain region and a source region formed in the base region. A trench is formed to extend from the surface of the source region and penetrate the source region and has depth to reach a portion near the drain region. A gate insulating film is formed on the side walls and bottom portion of the trench and the gate electrode is formed in the trench. The impurity concentration profile of the base region has a first peak in a portion near the interface between the source region and the base region and a second peak which is formed in a portion near the interface between the base region and the drain region and is lower than the first peak. The threshold voltage is determined based on the first peak and the dose amount is determined based on the second peak.

47. 发明授权

US06452231B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06452231B1
公开(公告)日：2002-09-17
申请号：US09126777
申请日：1998-07-31
申请人： Akio Nakagawa , Yusuke Kawaguchi
发明人： Akio Nakagawa , Yusuke Kawaguchi
IPC分类号： H01L2976
CPC分类号： H01L29/4236 , H01L27/0623 , H01L29/0634 , H01L29/0878 , H01L29/1083 , H01L29/42368 , H01L29/7395 , H01L29/78 , H01L29/7825 , H01L29/7834 , H01L29/7835
摘要： According to the present invention, there are proposed semiconductor devices each constituted in such a manner that the ON resistance thereof is lowered without increasing the area of the element. More specifically, as the insulated gate structure, there is used a trench gate structure constituted in such a manner that a gate electrode is formed in a state buried, through a gate insulation film, in trenches formed in the surface of an n-type high-resistance layer. Further, an n-type RESURF (Reduced Surface Field) diffused-layer extending as far as the trenches in a state contacted with the n-type drain layer is formed in the surface of the n-type high-resistance layer. As a result, the channel width can be increased with the area of the element remaining unvaried corresponding to the depth of the trenches to thereby reduce the channel resistance.
摘要翻译：根据本发明，提出了各种半导体器件，其各自构造成使得其导通电阻降低而不增加元件的面积。更具体地，作为绝缘栅极结构，使用沟槽栅极结构，其构造为使得栅极形成为通过栅极绝缘膜在形成在n型高度的表面中的沟槽中埋入的状态电阻层。此外，在n型高电阻层的表面形成有与n型漏极层接触的状态下延伸至沟槽的n型RESURF（还原表面场）扩散层。结果，可以随着沟槽的深度保持不变的元件的面积而增加沟道宽度，从而降低沟道电阻。

48. 发明申请

US20110221409A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110221409A1
公开(公告)日：2011-09-15
申请号：US13110971
申请日：2011-05-19
申请人： Kazutoshi NAKAMURA , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
发明人： Kazutoshi NAKAMURA , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
IPC分类号： G05F1/00 , H03H11/26
CPC分类号： H03K5/00006 , G06F1/08 , H02J1/00 , H02M3/156 , H03K2005/00293 , H03L7/0996 , Y10T307/50
摘要： A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.
摘要翻译：一种半导体器件包括：具有多级的第一延迟元件的电压控制型时钟产生电路，其振荡频率根据施加到第一延迟元件的控制电压而被控制; 具有串联连接的多级第二延迟元件的延迟电路; 以及选择电路，从由各个第二延迟元件的多级输出的脉冲信号中选择一个。第一延迟元件和第二延迟元件具有形成在同一半导体衬底上的相同结构，并且根据控制电压来调整第二延迟元件的延迟量。

49. 发明申请

US20070013351A1 Electric power unit operating in continuous and discontinuous conduction modes and control method therefor 失效
标题翻译：电力单元在连续和不连续导通模式下工作及其控制方法
公开(公告)号：US20070013351A1
公开(公告)日：2007-01-18
申请号：US11485466
申请日：2006-07-13
申请人： Toshiyuki Naka , Akio Nakagawa , Kazutoshi Nakamura
发明人： Toshiyuki Naka , Akio Nakagawa , Kazutoshi Nakamura
IPC分类号： G05F1/00
CPC分类号： H02M3/157 , H02M3/1588 , Y02B70/1466
摘要： An electronic power unit includes first and second MOS transistors and a digital control circuit. The first MOS transistor applies a voltage to the load. The second MOS transistor remains on while the first MOS transistor remains off and rectifies the current flowing in the load. The digital control circuit turns on the first transistor upon lapse of a first time interval from the time the second MOS transistor is turned off. The digital control circuit turns on the second MOS transistor upon lapse of a second time interval from the time the first MOS transistor is turned off. The digital control circuit controls the on-period of the first MOS transistor so that the voltage applied to the load is constant in a discontinuous conduction mode. The digital control circuit determines, while the voltage applied to the load is constant, an optimal value of the first time from the duty.
摘要翻译：电子功率单元包括第一和第二MOS晶体管和数字控制电路。第一个MOS晶体管向负载施加电压。第二MOS晶体管保持导通，而第一MOS晶体管保持关断并且对负载中流动的电流进行整流。数字控制电路在从第二MOS晶体管截止时起第一时间间隔开启第一晶体管。数字控制电路在从第一MOS晶体管截止时经过第二时间间隔开启第二MOS晶体管。数字控制电路控制第一MOS晶体管的导通周期，使得施加到负载的电压在不连续导通模式下是恒定的。数字控制电路在施加到负载的电压是恒定的情况下确定第一次从占空比的最佳值。

50. 发明授权

US07432579B2 Semiconductor device with horizontal MOSFET and Schottky barrier diode provided on single substrate 失效
标题翻译：在单个基板上提供具有水平MOSFET和肖特基势垒二极管的半导体器件
公开(公告)号：US07432579B2
公开(公告)日：2008-10-07
申请号：US10959201
申请日：2004-10-07
申请人： Tomoko Matsudai , Kazutoshi Nakamura , Akio Nakagawa
发明人： Tomoko Matsudai , Kazutoshi Nakamura , Akio Nakagawa
IPC分类号： H01L29/47 , H01L29/872
CPC分类号： H01L27/0727
摘要： A MOS field-effect transistor includes a semiconductor substrate of a first-conductivity type, a semiconductor layer of the first-conductivity type, a source region of a second-conductivity type, a first drain region of the second-conductivity type, a resurf layer of the second-conductivity type provided in the surface of the semiconductor layer between the source region and the first drain region in contact with the first drain region, and having a lower impurity concentration than the first drain region, a gate insulation film, and a gate electrode provided on the gate insulation film between the source region and resurf layer. A Schottky barrier diode includes a second drain region of the second-conductivity type provided in the surface of the semiconductor layer separate from the first drain region in a direction away from the gate electrode, and a Schottky electrode provided on the semiconductor layer between the first and second drain regions.
摘要翻译： MOS场效应晶体管包括第一导电类型的半导体衬底，第一导电类型的半导体层，第二导电类型的源极区域，第二导电类型的第一漏极区域，第二导电类型的半导体层，所述第二导电型层设置在与所述第一漏极区域接触的所述源极区域和所述第一漏极区域之间的所述半导体层的表面中，并且具有比所述第一漏极区域低的杂质浓度，栅极绝缘膜和栅电极，设置在源极区域和复合层之间的栅极绝缘膜上。肖特基势垒二极管包括设置在半导体层的表面上的第二导电类型的第二漏极区域，该第二漏极区域在远离栅极电极的方向上与第一漏极区域分开，以及肖特基电极，设置在第一和第二漏区。

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