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41. 发明申请

US20080252652A1 PROGRAMMABLE GRAPHICS PROCESSING ELEMENT 审中-公开
标题翻译：可编程图形处理元件
公开(公告)号：US20080252652A1
公开(公告)日：2008-10-16
申请号：US11735353
申请日：2007-04-13
申请人： Guofang Jiao , Lingjun Chen , Chun Yu , Yun Du
发明人： Guofang Jiao , Lingjun Chen , Chun Yu , Yun Du
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06T15/40 , G06T15/503
摘要： In general, this disclosure describes techniques for performing graphics operations using programmable processing units in a graphics processing unit (GPU). As described herein, a GPU includes a graphics pipeline that includes a programmable graphics processing element (PGPE). In accordance with the techniques described herein, an arbitrary set of instructions is loaded into the PGPE. Subsequently, the PGPE may execute the set of instructions in order to generate a new pixel object. A pixel object describes a displayable pixel. The new pixel object may represent a result of performing a graphics operation on a first pixel object. A display device may display a pixel described by the new pixel object.
摘要翻译：通常，本公开描述了使用图形处理单元（GPU）中的可编程处理单元执行图形操作的技术。如本文所述，GPU包括包括可编程图形处理元件（PGPE）的图形流水线。根据本文描述的技术，任意一组指令被加载到PGPE中。随后，PGPE可以执行该组指令以便生成新的像素对象。像素对象描述可显示像素。新的像素对象可以表示对第一像素对象执行图形操作的结果。显示装置可以显示由新像素对象描述的像素。

42. 发明申请

US20080235316A1 PROCESSOR WITH ADAPTIVE MULTI-SHADER 有权
标题翻译：具有自适应多镜像的处理器
公开(公告)号：US20080235316A1
公开(公告)日：2008-09-25
申请号：US11690358
申请日：2007-03-23
申请人： Yun Du , Guofang Jiao , Chun Yu
发明人： Yun Du , Guofang Jiao , Chun Yu
IPC分类号： G06F7/38
CPC分类号： G06T15/005
摘要： The disclosure describes an adaptive multi-shader within a processor that uses one or more high-precision arithmetic logic units (ALUs) and low-precision ALUs to process data based on the type of the data. Upon receiving a stream of data, the adaptive multi-shader first determines the type of the data. For example, the adaptive multi-shader may determine whether the data is suitable for high-precision processing or low-precision processing. The adaptive multi-shader then processes the data using the high-precision ALUs when the data is suitable for high-precision processing, and processes the data using the high-precision ALUs and the low-precision ALUs when the data is suitable for low-precision processing. The adaptive multi-shader may substantially reduce power consumption and silicon size of the processor by implementing the low-precision ALUs while maintaining the ability to process data using high-precision processing by implementing the high-precision ALUs.
摘要翻译：本公开描述了处理器内的自适应多着色器，其使用一个或多个高精度算术逻辑单元（ALU）和低精度ALU来基于数据的类型来处理数据。在接收到数据流之后，自适应多着色器首先确定数据的类型。例如，自适应多着色器可以确定数据是否适合于高精度处理或低精度处理。然后，当数据适用于高精度处理时，自适应多着色器使用高精度ALU处理数据，并且当数据适合低精度处理时，使用高精度ALU和低精度ALU处理数据，精密加工。自适应多着色器可以通过实施低精度ALU同时保持使用通过实施高精度ALU的高精度处理数据的能力来显着降低处理器的功耗和硅尺寸。

43. 发明申请

US20070283356A1 Multi-threaded processor with deferred thread output control 有权
标题翻译：具有延迟线程输出控制的多线程处理器
公开(公告)号：US20070283356A1
公开(公告)日：2007-12-06
申请号：US11445100
申请日：2006-05-31
申请人： Yun Du , Guofang Jiao , Chun Yu
发明人： Yun Du , Guofang Jiao , Chun Yu
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/30123 , G06F9/3836 , G06F9/3851 , G06F9/3855 , G06F9/3857 , Y02D10/24
摘要： A multi-threaded processor is provided that internally reorders output threads thereby avoiding the need for an external output reorder buffer. The multi-threaded processor writes its thread results back to an internal memory buffer to guarantee that thread results are outputted in the same order in which the threads are received. A thread scheduler within the multi-threaded processor manages thread ordering control to avoid the need for an external reorder buffer. A compiler for the multi-threaded processor converts instructions that would normally send processed results directly to an external reorder buffer so that the processed thread results are instead sent to the internal memory buffer of the multi-threaded processor.
摘要翻译：提供了多线程处理器，其内部重新排序输出线程，从而避免了对外部输出重排序缓冲器的需要。多线程处理器将其线程结果写回内部存储器缓冲区，以保证以与接收线程相同的顺序输出线程结果。多线程处理器内的线程调度器管理线程排序控制，以避免需要外部重排序缓冲区。用于多线程处理器的编译器将通常将处理结果直接发送到外部重排序缓冲器的指令转换成经处理的线程结果而不是发送到多线程处理器的内部存储器缓冲区。

44. 发明申请

US20090265528A1 PROGRAMMABLE STREAMING PROCESSOR WITH MIXED PRECISION INSTRUCTION EXECUTION 有权
标题翻译：具有混合精度指令执行的可编程流水处理器
公开(公告)号：US20090265528A1
公开(公告)日：2009-10-22
申请号：US12106654
申请日：2008-04-21
申请人： Yun Du , Chun Yu , Guofang Jiao , Stephen Molloy
发明人： Yun Du , Chun Yu , Guofang Jiao , Stephen Molloy
IPC分类号： G06F9/30
CPC分类号： G06T15/005 , G06F8/47
摘要： The disclosure relates to a programmable streaming processor that is capable of executing mixed-precision (e.g., full-precision, half-precision) instructions using different execution units. The various execution units are each capable of using graphics data to execute instructions at a particular precision level. An exemplary programmable shader processor includes a controller and multiple execution units. The controller is configured to receive an instruction for execution and to receive an indication of a data precision for execution of the instruction. The controller is also configured to receive a separate conversion instruction that, when executed, converts graphics data associated with the instruction to the indicated data precision. When operable, the controller selects one of the execution units based on the indicated data precision. The controller then causes the selected execution unit to execute the instruction with the indicated data precision using the graphics data associated with the instruction.
摘要翻译：本公开涉及一种能够使用不同执行单元执行混合精度（例如，全精度，半精度）指令的可编程流式处理器。各种执行单元都能够使用图形数据来执行特定精度级别的指令。示例性可编程着色器处理器包括控制器和多个执行单元。控制器被配置为接收用于执行的指令并且接收用于执行指令的数据精度的指示。控制器还被配置为接收单独的转换指令，该指令在执行时将与指令相关联的图形数据转换为所指示的数据精度。当可操作时，控制器基于指示的数据精度选择一个执行单元。然后，控制器使所选择的执行单元使用与指令相关联的图形数据，以指示的数据精度执行指令。

45. 发明申请

US20090113402A1 SERVER-BASED CODE COMPILATION 有权
标题翻译：基于服务器的代码编译
公开(公告)号：US20090113402A1
公开(公告)日：2009-04-30
申请号：US11925476
申请日：2007-10-26
申请人： Lingjun Chen , Guofang Jiao , Yun Du , Chun Yu
发明人： Lingjun Chen , Guofang Jiao , Yun Du , Chun Yu
IPC分类号： G06F9/45
CPC分类号： G06F8/41
摘要： A server is disclosed that includes an interface to a data communication network, a compiler library that stores a plurality of different compilers, and compiler selection logic responsive to data received at the interface and including logic. The compiler selection logic is configured to select one of the plurality of different compilers based on an evaluation of the received data. The selected compiler generates compiled output data and the compiled output data is communicated over the data communication network to a client.
摘要翻译：公开了一种服务器，其包括对数据通信网络的接口，存储多个不同编译器的编译器库，以及响应于在接口处接收的数据并包括逻辑的编译器选择逻辑。编译器选择逻辑被配置为基于对接收到的数据的评估来选择多个不同编译器之一。所选择的编译器生成编译的输出数据，并且编译的输出数据通过数据通信网络传送到客户机。

46. 发明申请

US20090096797A1 DEMAND BASED POWER CONTROL IN A GRAPHICS PROCESSING UNIT 有权
标题翻译：图形处理单元中基于需求的功率控制
公开(公告)号：US20090096797A1
公开(公告)日：2009-04-16
申请号：US11870597
申请日：2007-10-11
申请人： Yun Du , Chun Yu , Guofang Jiao , Stephen Molloy
发明人： Yun Du , Chun Yu , Guofang Jiao , Stephen Molloy
IPC分类号： G06F15/80
CPC分类号： G06F1/3203 , G06F1/3287 , G06T1/20 , Y02D10/171 , Y02D50/20
摘要： Disclosed herein is power controller for use with a graphics processing unit. The power controller monitors, manages and controls power supplied to components of a pipeline of the graphics processing unit. The power controller determining whether and to what extent power is to be supplied to a pipeline component based on status information received by the power controller in connection with the pipeline component. The power controller is capable of identifying a trend using the received status information, and determining whether and to what extent power is to be supplied to a pipeline component based on the identified trend.
摘要翻译：这里公开了与图形处理单元一起使用的功率控制器。功率控制器监视，管理和控制提供给图形处理单元的管线的组件的电力。功率控制器基于由电力控制器与流水线部件相关联的状态信息来确定是否以及在何种程度上向管道部件提供功率。功率控制器能够使用接收到的状态信息来识别趋势，并且基于所识别的趋势来确定是否以及在何种程度上向管道部件供电。

47. 发明申请

US20080201716A1 ON-DEMAND MULTI-THREAD MULTIMEDIA PROCESSOR 有权
标题翻译：多用途多媒体处理器
公开(公告)号：US20080201716A1
公开(公告)日：2008-08-21
申请号：US11677362
申请日：2007-02-21
申请人： Yun Du , Guofang Jiao , Chun Yu
发明人： Yun Du , Guofang Jiao , Chun Yu
IPC分类号： G06F9/46
CPC分类号： G06F12/0842 , G06F9/30145 , G06F9/30167 , G06F9/382 , G06F9/383 , G06F9/3851 , G06F9/3885 , G06F9/45558 , G06F9/5016 , G06F12/10 , G06F2009/45579 , G06F2009/45583 , Y02D10/13 , Y02D10/22
摘要： A device includes a multimedia processor that can concurrently support multiple applications for various types of multimedia such as graphics, audio, video, camera, games, etc. The multimedia processor includes configurable storage resources to store instructions, data, and state information for the applications and assignable processing units to perform various types of processing for the applications. The configurable storage resources may include an instruction cache to store instructions for the applications, register banks to store data for the applications, context registers to store state information for threads of the applications, etc. The processing units may include an arithmetic logic unit (ALU) core, an elementary function core, a logic core, a texture sampler, a load control unit, a flow controller, etc. The multimedia processor allocates a configurable portion of the storage resources to each application and dynamically assigns the processing units to the applications as requested by these applications.
摘要翻译：一种设备包括多媒体处理器，其可以同时支持用于各种类型的多媒体（例如图形，音频，视频，照相机，游戏等）的多个应用。多媒体处理器包括可配置的存储资源以存储用于应用的指令，数据和状态信息以及可分配处理单元来执行用于应用的各种类型的处理。可配置的存储资源可以包括用于存储用于应用的指令的指令高速缓存，寄存器组存储用于应用的数据，上下文寄存器以存储用于应用的线程的状态信息等。处理单元可以包括算术逻辑单元（ALU ）核心，基本功能核心，逻辑核心，纹理采样器，负载控制单元，流量控制器等。多媒体处理器将存储资源的可配置部分分配给每个应用，并且将处理单元动态地分配给应用按照这些应用的要求。

48. 发明申请

US20080074430A1 GRAPHICS PROCESSING UNIT WITH UNIFIED VERTEX CACHE AND SHADER REGISTER FILE 有权
标题翻译：具有统一VERTEX CACHE和SHADER寄存器文件的图形处理单元
公开(公告)号：US20080074430A1
公开(公告)日：2008-03-27
申请号：US11535809
申请日：2006-09-27
申请人： Guofang Jiao , Chun Yu , Yun Du
发明人： Guofang Jiao , Chun Yu , Yun Du
IPC分类号： G06T1/00
CPC分类号： G06T15/005
摘要： Techniques are described for processing computerized images with a graphics processing unit (GPU) using a unified vertex cache and shader register file. The techniques include creating a shared shader coupled to the GPU pipeline and a unified vertex cache and shader register file coupled to the shared shader to substantially eliminate data movement within the GPU pipeline. The GPU pipeline sends image geometry information based on an image geometry for an image to the shared shader. The shared shader performs vertex shading to generate vertex coordinates and attributes of vertices in the image. The shared shader then stores the vertex attributes in the unified vertex cache and shader register file, and sends only the vertex coordinates of the vertices back to the GPU pipeline. The GPU pipeline processes the image based on the vertex coordinates, and the shared shader processes the image based on the vertex attributes.
摘要翻译：描述了使用统一的顶点高速缓存和着色器寄存器文件处理具有图形处理单元（GPU）的计算机化图像的技术。这些技术包括创建耦合到GPU流水线的共享着色器和耦合到共享着色器的统一顶点高速缓存和着色器寄存器文件，以基本上消除GPU流水线内的数据移动。 GPU管道将基于图像的图像几何的图像几何信息发送到共享着色器。共享着色器执行顶点着色以生成图像中顶点坐标和顶点属性。共享着色器然后将顶点属性存储在统一的顶点缓存和着色器寄存器文件中，并且仅将顶点的顶点坐标发送回GPU管道。 GPU流水线基于顶点坐标处理图像，共享着色器基于顶点属性处理图像。

49. 发明申请

US20070252843A1 Graphics system with configurable caches 有权
标题翻译：具有可配置缓存的图形系统
公开(公告)号：US20070252843A1
公开(公告)日：2007-11-01
申请号：US11412678
申请日：2006-04-26
申请人： Chun Yu , Guofang Jiao , Yun Du
发明人： Chun Yu , Guofang Jiao , Yun Du
IPC分类号： G09G5/36
CPC分类号： G06T1/60 , G06T15/005
摘要： A graphics system includes a graphics processor and a cache memory system. The graphics processor includes processing units that perform various graphics operations to render graphics images. The cache memory system may include fully configurable caches, partially configurable caches, or a combination of configurable and dedicated caches. The cache memory system may further include a control unit, a crossbar, and an arbiter. The control unit may determine memory utilization by the processing units and assign the configurable caches to the processing units based on memory utilization. The configurable caches may be assigned to achieve good utilization of these caches and to avoid memory access bottleneck. The crossbar couples the processing units to their assigned caches. The arbiter facilitates data exchanges between the caches and a main memory.
摘要翻译：图形系统包括图形处理器和高速缓冲存储器系统。图形处理器包括执行各种图形操作以渲染图形图像的处理单元。高速缓冲存储器系统可以包括完全可配置的高速缓存，部分可配置的高速缓存，或可配置和专用高速缓存的组合。高速缓存存储器系统还可以包括控制单元，交叉开关和仲裁器。控制单元可以确定处理单元的存储器利用率，并且基于存储器利用率将配置的高速缓存分配给处理单元。可以分配可配置的高速缓存以实现这些高速缓存的良好利用并避免存储器访问瓶颈。交叉开关将处理单元耦合到其分配的高速缓存。仲裁器便于缓存和主存储器之间的数据交换。

50. 发明授权

US08773459B2 3-D clipping in a graphics processing unit 有权
标题翻译：图形处理单元中的3-D剪辑
公开(公告)号：US08773459B2
公开(公告)日：2014-07-08
申请号：US13524946
申请日：2012-06-15
申请人： Guofang Jiao , Chun Yu , Lingjun Chen , Yun Du
发明人： Guofang Jiao , Chun Yu , Lingjun Chen , Yun Du
IPC分类号： G09G5/00 , G06T1/20 , G06T15/30 , G06T19/00 , G06T11/40 , G06T15/00 , G06T11/60
CPC分类号： G06T1/20 , G06T11/40 , G06T11/60 , G06T15/005 , G06T15/30 , G06T19/00 , G09G5/393
摘要： A graphics processing unit (GPU) efficiently performs 3-dimensional (3-D) clipping using processing units used for other graphics functions. The GPU includes first and second hardware units and at least one buffer. The first hardware unit performs 3-D clipping of primitives using a first processing unit used for a first graphics function, e.g., an ALU used for triangle setup, depth gradient setup, etc. The first hardware unit may perform 3-D clipping by (a) computing clip codes for each vertex of each primitive, (b) determining whether to pass, discard or clip each primitive based on the clip codes for all vertices of the primitive, and (c) clipping each primitive to be clipped against clipping planes. The second hardware unit computes attribute component values for new vertices resulting from the 3-D clipping, e.g., using an ALU used for attribute gradient setup, attribute interpolation, etc. The buffer(s) store intermediate results of the 3-D clipping.
摘要翻译：图形处理单元（GPU）使用用于其他图形功能的处理单元有效地执行三维（3-D）剪辑。 GPU包括第一和第二硬件单元和至少一个缓冲器。第一硬件单元使用用于第一图形功能的第一处理单元（例如用于三角形设置的ALU，深度梯度设置等）来对原语执行3-D限幅。第一硬件单元可以通过（ a）计算每个图元的每个顶点的剪辑代码，（b）基于所述基元的所有顶点的剪辑代码来确定是否传递，丢弃或剪切每个图元，以及（c）剪切要针对剪切平面剪切的每个图元。第二硬件单元计算由3-D限幅产生的新顶点的属性分量值，例如使用用于属性梯度设置，属性插值等的ALU。该缓冲器存储3-D限幅的中间结果。

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