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41. 发明申请

US20110049221A1 METHOD OF JOINING A CHIP ON A SUBSTRATE 有权
标题翻译：在基板上接合芯片的方法
公开(公告)号：US20110049221A1
公开(公告)日：2011-03-03
申请号：US12551960
申请日：2009-09-01
申请人： Pascal P. Blais , Paul F. Fortier , Kang-Wook Lee , Jae-Woong Nah , Soojae Park , Robert L. Toutant , Alain A. Warren
发明人： Pascal P. Blais , Paul F. Fortier , Kang-Wook Lee , Jae-Woong Nah , Soojae Park , Robert L. Toutant , Alain A. Warren
IPC分类号： B23K37/04 , B23K31/00
CPC分类号： B23K1/0016 , H01L21/563 , H01L24/75 , H01L24/81 , H01L2224/13099 , H01L2224/131 , H01L2224/73204 , H01L2224/75704 , H01L2224/75985 , H01L2224/81005 , H01L2224/81191 , H01L2224/81815 , H01L2224/8191 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01076 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/15787 , H01L2924/3511 , H01L2924/01026 , H01L2924/00
摘要： A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.
摘要翻译：公开了一种用于制造芯片组件的方法和装置，其防止或减少在芯片组装过程中可能发生的Si芯片中后端的超低k电介质的开裂和分层。该方法和装置在芯片接合过程期间对基板的顶表面和底表面施加压力，使得组装的模块的弯曲和翘曲减小。减少弯曲和翘曲防止或减少超低k电介质的开裂和分层。

42. 发明授权

US07537959B2 Chip stack package and manufacturing method thereof 有权
标题翻译：芯片堆叠封装及其制造方法
公开(公告)号：US07537959B2
公开(公告)日：2009-05-26
申请号：US11889400
申请日：2007-08-13
申请人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
发明人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
IPC分类号： H01L21/00 , H01L21/26 , H01L21/44 , H01L29/40
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/481 , H01L23/5389 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05166 , H01L2224/05548 , H01L2224/05556 , H01L2224/05569 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , Y02P80/30 , Y10S438/977 , Y10T436/104998 , Y10T436/108331 , Y10T436/17 , Y10T436/175383 , H01L2224/81 , H01L2224/82 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.
摘要翻译：通过在与芯片相邻的划线中形成连接通孔并且使用重新布线将连接器件芯片焊盘连接到连接通孔，在晶片级制造芯片堆叠封装。然后将下部芯片连接并连接到可以是测试晶片的衬底，并且上部芯片被附接并连接到下部芯片，电连接通过它们各自的连接通孔来实现。除了连接通孔之外，芯片堆叠封装可以包括在垂直相邻的芯片和/或下部芯片和衬底之间形成的连接凸块。优选的基板是测试晶片，其允许附接的芯片被测试并且如果有故障则被替换，从而确保每层堆叠的芯片仅在连接下一层芯片之前仅包括“已知的芯片”，从而提高生产率并提高产量。

43. 发明申请

US20080124568A1 New flux composition and process for use thereof 失效
标题翻译：新的助焊剂组合物及其使用方法
公开(公告)号：US20080124568A1
公开(公告)日：2008-05-29
申请号：US11493724
申请日：2006-07-26
申请人： Eric Duchesne , Kang-Wook Lee , Valerie Oberson
发明人： Eric Duchesne , Kang-Wook Lee , Valerie Oberson
IPC分类号： B32B15/01 , B23K1/00 , B23K35/363
CPC分类号： B23K35/362 , Y10T428/12493
摘要： The invention relates to a composition of matter comprising a soldering flux, wherein the flux consists essentially of a combination of a fluxing agent and a solvent, and wherein the fluxing agent comprises a keto acid such as levulinic acid or acetylbutyric acid. The flux may also comprises an ester acid, or comprises a mixture of the keto acid with the ester acid. The solvent comprises a mixture of a tacky solvent with a non-tacky solvent. The invention also relates to a process comprising soldering at least two surfaces together, each of which comprises a metal area to which solder can adhere by employing the following steps in any order: applying solder to at least one of the metal areas, aligning the metal areas so that they are superimposed over one another, heating at least one of the areas to a temperature that comprises at least the melting temperature of the solder. The last step comprises joining the superimposed areas to one another. The process employs the flux composition operatively associated with the solder, and in one embodiment the invention comprises a mixture of the flux composition with powdered solder. In another embodiment, the process comprises IMS, C4 and C4NP processes and the solder comprises a lead free solder. The invention also comprises a product produced by the foregoing process or processes.
摘要翻译：本发明涉及包含助焊剂的物质组合物，其中助熔剂基本上由助熔剂和溶剂的组合组成，并且其中助熔剂包括酮酸，例如乙酰丙酸或乙酰基丁酸。助熔剂还可以包含酯酸，或包含酮酸与酯酸的混合物。溶剂包括粘性溶剂与非粘性溶剂的混合物。本发明还涉及一种方法，其包括将至少两个表面焊接在一起，每个表面包括金属区域，焊料可以以任何顺序通过以下步骤粘附到该金属区域：将焊料施加到至少一个金属区域，使金属对准区域，使得它们彼此叠加，将至少一个区域加热至至少包括焊料的熔化温度的温度。最后一步包括将叠加的区域相互连接。该方法使用与焊料可操作地相关联的助熔剂组合物，并且在一个实施方案中，本发明包括焊剂组合物与粉末焊料的混合物。在另一个实施方案中，该方法包括IMS，C4和C4NP方法，焊料包括无铅焊料。本发明还包括通过前述方法或方法生产的产品。

44. 发明申请

US20070281374A1 Chip stack package and manufacturing method thereof 有权
公开(公告)号：US20070281374A1
公开(公告)日：2007-12-06
申请号：US11889400
申请日：2007-08-13
申请人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
发明人： Kang-Wook Lee , Gu-Sung Kim , Dong-Hyeon Jang , Seung-Duk Baek , Jae-Sik Chung
IPC分类号： H01L21/66 , H01L21/58
CPC分类号： H01L25/50 , H01L21/76898 , H01L23/481 , H01L23/5389 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05166 , H01L2224/05548 , H01L2224/05556 , H01L2224/05569 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , Y02P80/30 , Y10S438/977 , Y10T436/104998 , Y10T436/108331 , Y10T436/17 , Y10T436/175383 , H01L2224/81 , H01L2224/82 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

45. 发明申请

US20070170576A1 Wafer level stack structure for system-in-package and method thereof 有权
公开(公告)号：US20070170576A1
公开(公告)日：2007-07-26
申请号：US11727760
申请日：2007-03-28
申请人： Kang-Wook Lee , Se-Yong Oh , Young-Hee Song , Gu-Sung Kim
发明人： Kang-Wook Lee , Se-Yong Oh , Young-Hee Song , Gu-Sung Kim
IPC分类号： H01L23/02
CPC分类号： H01L25/50 , H01L23/3128 , H01L23/481 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/48 , H01L24/49 , H01L24/94 , H01L25/0657 , H01L2224/02372 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/06181 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/48095 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2225/06589 , H01L2924/00 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A method of forming a wafer level stack structure, including forming a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, forming a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including at least one first device chip having a first plurality of input/output (I/O) pads and at least one second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.

46. 发明授权

US06933586B2 Porous low-k dielectric interconnects with improved adhesion produced by partial burnout of surface porogens 失效
公开(公告)号：US06933586B2
公开(公告)日：2005-08-23
申请号：US10290616
申请日：2002-11-08
申请人： Ann R Fornof , Jeffrey C Hedrick , Kang-Wook Lee , Christy S Tyberg
发明人： Ann R Fornof , Jeffrey C Hedrick , Kang-Wook Lee , Christy S Tyberg
IPC分类号： H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L29/00
CPC分类号： H01L21/22 , H01L21/02118 , H01L21/02126 , H01L21/022 , H01L21/02203 , H01L21/02282 , H01L21/02362 , H01L21/31695 , H01L21/76801 , H01L21/76807 , H01L21/7682 , H01L21/76829 , H01L21/76832 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2221/1047 , H01L2924/0002 , Y10T428/31663 , H01L2924/00
摘要： An electrical interconnect structure on a substrate, includes a first porous dielectric layer with surface region from which a porogen has been removed; and an etch stop layer disposed upon the first porous dielectric layer so that the etch stop layer extends to partially fill pores in the surface region of the first porous dielectric layer from which the porogen has been removed, thus improving adhesion during subsequent processing. The porogen may be removed from the surface region by heating, and in particular by hot plate baking. A second porous dielectric layer, which may have the same composition as the first porous dielectric layer, may be formed over the etch stop layer. Electrical vias and lines may be formed in the first and second porous dielectric layer, respectively. The layers may be part of a multilayer stack, wherein all of the layers are cured simultaneously in a spin application tool porous dielectric layer.

47. 发明授权

US06854778B2 Upper tray mounting structure 失效
标题翻译：上托盘安装结构
公开(公告)号：US06854778B2
公开(公告)日：2005-02-15
申请号：US10330333
申请日：2002-12-30
申请人： Kang-Wook Lee
发明人： Kang-Wook Lee
IPC分类号： B60N3/00 , B60N3/12 , B60R7/06
CPC分类号： B60N3/002 , B60N3/12 , B60R7/06
摘要： An upper tray mounted on an instrument panel of a vehicle includes a receiving member mounted on an upper portion of the instrument panel. A hinge member is movably attached to the receiving member. A cover member is joined to the hinge member to rotate about a fixed pivot and configured to close the receiving member. A coil spring connects the hinge member with the receiving member. The coil spring is configured to provide a force in a direction that the cover member opens.
摘要翻译：安装在车辆的仪表板上的上托盘包括安装在仪表板上部的接收构件。铰链构件可移动地附接到接收构件。盖构件连接到铰链构件以围绕固定枢轴旋转并且构造成关闭接收构件。螺旋弹簧将铰链构件与接收构件连接。螺旋弹簧构造成在盖构件打开的方向上提供力。

48. 发明授权

US5786041A Alignment film, a method for producing the alignment film and a liquid crystal display device using the alignment film 失效
标题翻译：取向膜，取向膜的制造方法以及使用取向膜的液晶显示装置
公开(公告)号：US5786041A
公开(公告)日：1998-07-28
申请号：US476214
申请日：1995-06-07
申请人： Atsushi Takenaka , Kenichi Tajima , Hideo Takano , Shui-Chih A. Lien , Kang-Wook Lee
发明人： Atsushi Takenaka , Kenichi Tajima , Hideo Takano , Shui-Chih A. Lien , Kang-Wook Lee
IPC分类号： G02F1/1337
CPC分类号： G02F1/133788 , G02F1/133711 , Y10T428/1005
摘要： An alignment-film in which the pretilt angle is changed by ultraviolet irradiation, a material for forming the same, a liquid crystal display device using the alignment film, a method for producing an alignment-film formation material, and a method for producing an alignment film. Ultraviolet irradiation causes large changes in pretilt angle but few changes in electrical characteristics, and a liquid crystal display device free from deterioration of the liquid crystal, image sticking, or the occurrence of flicker results. A first polymer forms the underlying principal layer and a second polymer forms thereon a surface layer thinner than the principal layer. The first polymer may exhibit a small change in electrical characteristics due to ultraviolet radiation and the second polymer may exhibit a large change in pretilt angle due to ultraviolet radiation.
摘要翻译：其中通过紫外线照射改变预倾斜角度的取向膜，其形成用材料，使用取向膜的液晶显示装置，取向膜形成材料的制造方法以及对准膜的制造方法电影。紫外线照射引起预倾角变化大，电特性变化小，液晶显示装置没有劣化，图像残留，闪烁现象等。第一聚合物形成下面的主要层，并且第二聚合物在其上形成比主层更薄的表面层。第一聚合物可能由于紫外线辐射而表现出小的电特性变化，并且第二聚合物可能由于紫外线辐射而呈现预倾角变化大。

49. 发明授权

US5151304A Structure and method for enhancing adhesion to a polyimide surface 失效
标题翻译：用于增强与聚酰亚胺表面的粘附性的结构和方法
公开(公告)号：US5151304A
公开(公告)日：1992-09-29
申请号：US644063
申请日：1991-01-22
申请人： Kang-Wook Lee
发明人： Kang-Wook Lee
IPC分类号： C08G73/10 , B05D3/02 , B05D3/10 , C08J7/04 , C08J7/12 , C23C14/02 , C23C14/20 , H05K1/03 , H05K3/38
CPC分类号： C08J7/12 , B05D3/10 , C23C14/02 , C23C14/20 , B05D2202/10 , B05D2505/50 , B05D3/0254 , C08J2379/08 , H05K1/0346 , H05K3/381
摘要： The surface of a substrate made of substantially crystalline polyimide is converted to form a layer of substantially amorphous polyimide. The substantially amorphous layer is formed by treating the crystalline polimide surface with a base followed by treatment with an acid to form a polyamic acid layer, which is reimidized to form a substantially amorphous layer by a low temperature heat cycle. Metals or polyimides can be deposited onto this amorphous layer, which is then cured to convert the amorphous layer to substantially crystalline polyimide. This process enhances the adhesion of the metal or polyimide layer without introducing contamination (new foreign materials or new functional groups) from surface treatments of adhesion layers.
摘要翻译：将由基本上结晶的聚酰亚胺制成的基材的表面转化成基本无定形的聚酰亚胺层。基本上非晶层通过用碱处理结晶聚酰亚胺表面然后用酸处理形成聚酰胺酸层而形成，其被重塑以通过低温热循环形成基本无定形的层。可以将金属或聚酰亚胺沉积到该非晶层上，然后将其固化以将非晶层转化为基本上结晶的聚酰亚胺。该过程增强了金属或聚酰亚胺层的粘附性，而不会从粘附层的表面处理中引入污染（新的异物或新的官能团）。

50. 发明授权

US09815149B2 Flux composition and techniques for use thereof 有权
公开(公告)号：US09815149B2
公开(公告)日：2017-11-14
申请号：US13438213
申请日：2012-04-03
申请人： Kang-Wook Lee , Nathalie Normand , Valerie Oberson
发明人： Kang-Wook Lee , Nathalie Normand , Valerie Oberson
IPC分类号： B23K35/362 , B23K35/36 , B23K1/00 , B23K35/26
CPC分类号： B23K35/362 , B23K1/0016 , B23K35/262 , B23K35/3601 , B23K35/3612 , B23K35/3618
摘要： The present invention is directed to flux compositions and uses thereof. One composition comprises an activator and a solvent being a glycerol ethoxylate with a molecular weight of 200-500. Another composition comprises an activator, a solvent being a glycerol ethoxylate with a molecular weight of 200-500 and an amine. A soldering method for joining objects is also provided, comprising the steps of applying a flux composition to at least a portion of one or more of the objects, and joining the objects.

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