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41. 发明授权

US07098819B2 Modulation apparatus/method, demodulation apparatus/method and program presenting medium 有权
标题翻译：调制装置/方法，解调装置/方法和程序呈现介质
公开(公告)号：US07098819B2
公开(公告)日：2006-08-29
申请号：US10704277
申请日：2003-11-07
申请人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shinpuku , Tatsuya Narahara , Kosuke Nakamura
发明人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shinpuku , Tatsuya Narahara , Kosuke Nakamura
IPC分类号： H03M7/00
CPC分类号： G11B20/1426 , G11B2020/1453 , H03M5/145
摘要： A DSV control bit determining/inserting unit inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit. This modulation unit converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit. The conversion table used by the modulation unit includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit. In addition, the conversion table enforces a conversion rule, according to which the remaineder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.
摘要翻译： DSV控制位确定/插入单元将用于执行DSV控制的DSV控制位插入到输入数据串中，并将包括DSV控制位的数据串输出到调制单元。该调制单元根据转换表将具有2位的基本数据长度的数据串转换为具有3位的基本码长度的可变长度码，并将从转换得到的代码输出到NRZI编码单元。由调制单元使用的转换表包括用于将最小运行的连续出现次数限制为预定值的替换代码和用于保持游程长度限制的替代代码。另外，转换表执行转换规则，根据该转换规则，数据字符串中的元素“1”计数的剩余值除以2，值为0或1，总是等于由数据字符串转换得到的代码中的元素的“1”计数为2。

42. 发明授权

US07046736B2 Method and apparatus for modulating and demodulating data into a variable-length code and providing a sync signal to the train of codes 有权
标题翻译：用于将数据调制和解调为可变长度代码并向代码串提供同步信号的方法和装置
公开(公告)号：US07046736B2
公开(公告)日：2006-05-16
申请号：US11088464
申请日：2005-03-24
申请人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
发明人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
IPC分类号： H04B14/04
CPC分类号： G11B20/1426 , G11B20/1403 , G11B2020/1287 , G11B2020/1453 , G11B2020/1457 , H03M5/145 , H04L7/0083 , H04L7/041 , H04L7/044
摘要： A data-demodulating apparatus for demodulating a variable-length code (d, k; m, n; r) having a basic code length of n bits to data having a basic data length of m bits. A train of codes is received, and a sync signal having a pattern that breaks a maximum run is detected. The pattern is repeated twice continuously and the minimum run is repeated no more than six times. The first bit of the sync signal is “1” when the train of modulated codes that immediately precedes the sync signal is included in a termination table used to terminate, at a desired position, a code when less than a predetermined number of variable length codes are available.
摘要翻译：一种数据解调装置，用于将具有n位基本码长的可变长度码（d，k; m，n; r）解调为具有m比特的基本数据长度的数据。接收一串代码，并且检测到具有中断最大运行的模式的同步信号。该模式连续重复两次，最小运行重复不超过六次。当紧接在同步信号之前的调制码序列包括在终止表中时，同步信号的第一位为“1”，用于当期望位置在小于预定数量的可变长度码时终止代码可用。

43. 发明授权

US06982660B2 Modulation apparatus and method, and DSV-control-bit generating method 失效
标题翻译：调制装置和方法，以及DSV控制位产生方法
公开(公告)号：US06982660B2
公开(公告)日：2006-01-03
申请号：US11102359
申请日：2005-04-07
申请人： Toshiyuki Nakagawa , Minoru Tobita , Hiroshige Okamura
发明人： Toshiyuki Nakagawa , Minoru Tobita , Hiroshige Okamura
IPC分类号： H03M5/00 , H03M7/40
CPC分类号： G11B20/1426 , H03M5/145
摘要： A modulation apparatus and method for more accurately determining a value of a control bit to be inserted into a data sequence and digital sum value (DSV) control bit generating method in which a data conversion unit supplies modulation-delimiter information including information regarding delimiters of modulation of a data sequence based on a conversion table to a modulation-delimiter detecting unit and supplies to a valid-delimiter detecting unit a DSV-segment-delimiter signal including information regarding a delimiter position of a DSV segment of the data sequence having the DSV control bit. The modulation-delimiter detecting unit detects modulation-delimiter positions based on the modulation-delimiter information supplied thereto and supplies a modulation-delimiter signal to the valid-delimiter detecting unit. The valid-delimiter detecting unit, based on the DSV-segment-delimiter signal supplied thereto, detects a valid-delimiter position for controlling timing for determining a DSV control bit of the relevant DSV segment from the modulation-delimiter positions represented by the modulation-delimiter signal supplied thereto.
摘要翻译：一种用于更精确地确定要插入到数据序列中的控制位的值的调制装置和方法以及数字和值（DSV）控制位产生方法，其中数据转换单元提供包括关于调制定界符的信息的调制分隔符信息将基于转换表的数据序列发送到调制分隔符检测单元，并向有效定界符检测单元提供包括关于具有DSV控制的数据序列的DSV段的定界符位置的信息的DSV段分隔符信号位。调制分隔符检测单元根据提供给其的调制分隔符信息来检测调制分隔符位置，并将调制分隔符信号提供给有效分隔符检测单元。有效定界符检测单元基于提供给其的DSV段分隔符信号，从由调制分隔符表示的调制分隔符位置检测用于控制用于确定相关DSV段的DSV控制位的定时的有效分隔符位置，分隔符信号。

44. 发明授权

US06950042B2 Modulating apparatus and method, and DSV control bit producing method 失效
标题翻译：调制装置和方法，以及DSV控制位产生方法
公开(公告)号：US06950042B2
公开(公告)日：2005-09-27
申请号：US10467399
申请日：2002-12-10
申请人： Toshiyuki Nakagawa , Hiroshige Okamura , Minoru Tobita
发明人： Toshiyuki Nakagawa , Hiroshige Okamura , Minoru Tobita
IPC分类号： G11B20/10 , G11B20/14 , H03M5/14 , H03M7/14 , H03M5/00
CPC分类号： H03M5/145 , G11B20/10 , G11B20/1426 , G11B2020/1457
摘要： The present invention relates to a modulation apparatus and method and a DSV-control-bit generating method for suppressing an increase in circuit size of the modulation apparatus. When an input data stream is supplied to a DSV control bit determination unit 31, the DSV control bit determination unit 31 determines a DSV control bit to be inserted into the input data stream. Upon supplying the input data stream to the DSV control bit determination unit 31, the input data stream is simultaneously supplied to a delay processor 32. The input data stream is delayed for a predetermined delay time and supplied to a determined-DSV-control-bit insertion unit 33. The determined-DSV-control-bit insertion unit 33 inserts the DSV control bit determined by the DSV control bit determination unit 31 into a predetermined position of the input data stream supplied by the delay means and supplies the input data stream containing the DSV control bit to a modulator 34. The modulator 34 modulates the input data stream containing the DSV control bit into a code string in accordance with a predetermined coding rule (for example, 1,7PP modulation).
摘要翻译：本发明涉及用于抑制调制装置的电路尺寸增加的调制装置和方法以及DSV控制位产生方法。当输入数据流被提供给DSV控制位确定单元31时，DSV控制位确定单元31确定要插入到输入数据流中的DSV控制位。在将输入数据流提供给DSV控制位确定单元31时，输入数据流被同时提供给延迟处理器32。输入数据流延迟预定的延迟时间并提供给确定的DSV控制位插入单元33。确定的DSV控制位插入单元33将由DSV控制位确定单元31确定的DSV控制位插入由延迟装置提供的输入数据流的预定位置，并将包含DSV控制位的输入数据流到调制器34。调制器34根据预定的编码规则（例如，1,7PP调制）将包含DSV控制位的输入数据流调制成代码串。

45. 发明授权

US06879637B1 Method and apparatus for modulating and demodulating data into a variable length code and a providing medium for implementing the method 有权
标题翻译：用于将数据调制和解调成可变长度码的方法和装置以及用于实现该方法的提供媒体
公开(公告)号：US06879637B1
公开(公告)日：2005-04-12
申请号：US09530074
申请日：1999-08-24
申请人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
发明人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
IPC分类号： H03M7/14 , G11B20/14 , H03M5/14 , H04L7/00 , H04L7/04 , H04B14/04
CPC分类号： G11B20/1426 , G11B20/1403 , G11B2020/1287 , G11B2020/1453 , G11B2020/1457 , H03M5/145 , H04L7/0083 , H04L7/041 , H04L7/044
摘要： A method and apparatus for modulating data modulates data having a length of m-bits to a variable length code having a basic code length of n-bits. A SYNC but insertion section adds a sync signal to a train of codes, after a minimum run. The sync signal has a pattern that breaks a maximum run.
摘要翻译：用于调制数据的方法和装置将具有m比特长度的数据调制为具有n比特的基本码长度的可变长度码。 SYNC但插入部分在最小运行后将同步信号添加到代码列。同步信号具有中断最大运行的模式。

46. 发明申请

US20050017881A1 Modulating apparatus and method, and dsv control bit producing method 失效
标题翻译：调制装置和方法，以及dsv控制位产生方法
公开(公告)号：US20050017881A1
公开(公告)日：2005-01-27
申请号：US10467399
申请日：2002-12-10
申请人： Toshiyuki Nakagawa , Hiroshige Okamura , Minoru Tobita
发明人： Toshiyuki Nakagawa , Hiroshige Okamura , Minoru Tobita
IPC分类号： G11B20/10 , G11B20/14 , H03M5/14 , H03M7/14 , H03M7/00
CPC分类号： H03M5/145 , G11B20/10 , G11B20/1426 , G11B2020/1457
摘要： The present invention relates to a modulation apparatus and method and a DSV-control-bit generating method for suppressing an increase in circuit size of the modulation apparatus. When an input data stream is supplied to a DSV control bit determination unit 31, the DSV control bit determination unit 31 determines a DSV control bit to be inserted into the input data stream. Upon supplying the input data stream to the DSV control bit determination unit 31, the input data stream is simultaneously supplied to a delay processor 32. The input data stream is delayed for a predetermined delay time and supplied to a determined-DSV-control-bit insertion unit 33. The determined-DSV-control-bit insertion unit 33 inserts the DSV control bit determined by the DSV control bit determination unit 3.1 into a predetermined position of the input data stream supplied by the delay means and supplies the input data stream containing the DSV control bit to a modulator 34. The modulator 34 modulates the input data stream containing the DSV control bit into a code string in accordance with a predetermined coding rule (for example, 1,7PP modulation).
摘要翻译：本发明涉及用于抑制调制装置的电路尺寸增加的调制装置和方法以及DSV控制位产生方法。当输入数据流被提供给DSV控制位确定单元31时，DSV控制位确定单元31确定要插入到输入数据流中的DSV控制位。在将输入数据流提供给DSV控制位确定单元31时，输入数据流被同时提供给延迟处理器32.输入数据流被延迟预定的延迟时间并提供给确定的DSV控制位插入单元33.确定的DSV控制位插入单元33将由DSV控制位确定单元3.1确定的DSV控制位插入由延迟装置提供的输入数据流的预定位置，并提供包含 DSV控制位到调制器34.调制器34根据预定的编码规则（例如，1,7PP调制）将包含DSV控制位的输入数据流调制成代码串。

47. 发明申请

US20050005193A1 Data recording/reproduction device and data recording/reproduction method 有权
标题翻译：数据记录/再现装置和数据记录/再现方法
公开(公告)号：US20050005193A1
公开(公告)日：2005-01-06
申请号：US10487606
申请日：2003-07-22
申请人： Toshiyuki Nakagawa , Keitarou Kondou , Hiroaki Eto , Yoshihide Shimpuku
发明人： Toshiyuki Nakagawa , Keitarou Kondou , Hiroaki Eto , Yoshihide Shimpuku
IPC分类号： G11B5/09 , G11B20/10 , G11B20/12 , G11B20/18 , H03M13/15 , H03M13/29 , H02H3/05
CPC分类号： G11B20/1833 , G11B20/1258 , G11B20/1866 , G11B2020/1222 , G11B2020/1232 , G11B2020/1238 , G11B2020/1267 , G11B2020/1294 , G11B2220/2516
摘要： In order to reproduce data in a stable manner by correction of random and burst errors of a wide range without lowering a transfer speed, C2 error correction for correcting an inter-sector error is carried out in addition to the conventional C1 error correction for correcting an error generated in a sector. The configuration of an error correction unit (or an ECC block) including C1 and C2 codes is formed as a track. That is to say, one track is used as the base of an ECC block unit. In this way, two ECC block units never exist in the same track.
摘要翻译：为了通过校正宽范围的随机和脉冲串错误而不降低传送速度来稳定地再现数据，除了用于校正传输速度的常规C1错误校正之外还执行用于校正扇区间误差的C2纠错扇区中产生的错误。包括C1和C2码的纠错单元（或ECC块）的配置被形成为轨道。也就是说，使用一个轨道作为ECC块单元的基础。以这种方式，两个ECC块单元永远不存在于同一个轨道中。

48. 发明授权

US06677866B2 Modulation apparatus/method, demodulation apparatus/method and program presenting medium 有权
标题翻译：调制装置/方法，解调装置/方法和程序呈现介质
公开(公告)号：US06677866B2
公开(公告)日：2004-01-13
申请号：US10263079
申请日：2002-10-02
申请人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert J. Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shinpuku , Tatsuya Narahara , Kosuke Nakamura
发明人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert J. Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shinpuku , Tatsuya Narahara , Kosuke Nakamura
IPC分类号： H03M700
CPC分类号： G11B20/1426 , G11B2020/1453 , H03M5/145
摘要： How to record and play back data at a high line density. A DSV control bit determining/inserting unit 11 inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit 12. The modulation unit 12 converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit 13. The conversion table used by the modulation unit 12 includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit. In addition, the conversion table enforces a conversion rule, according to which the remainder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.
摘要翻译：如何以高线密度记录和播放数据。 DSV控制位确定/插入单元11将用于执行DSV控制的DSV控制位插入到输入数据串中，并将包括DSV控制位的数据串输出到调制单元12.调制单元12将数据串以基本 2比特的数据长度根据转换表具有3比特的基本码长度的可变长度码，并将从转换得到的码输出到NRZI编码单元13.调制单元12使用的转换表包括替换码用于将最小运行的连续出现次数限制为预定值，以及用于保持游程长度限制的替代代码。另外，转换表强制执行转换规则，根据该转换规则，数据串中的元素的“1”计数的余数除以2，值为0或1，其总和必须等于由数据字符串转换得到的代码中的元素的“1”计数为2。

49. 发明授权

US06359930B1 Modulation device and method and distribution medium 有权
标题翻译：调制装置及方法及配送介质
公开(公告)号：US06359930B1
公开(公告)日：2002-03-19
申请号：US09208125
申请日：1998-12-09
申请人： Toshiyuki Nakagawa , Yoshihide Shimpuku
发明人： Toshiyuki Nakagawa , Yoshihide Shimpuku
IPC分类号： H03M702
CPC分类号： H03M7/46 , G11B20/1426 , G11B2020/1457 , H03M5/145
摘要： A DSV bit is inserted in an input data string by a DSV bit determining insertion unit. A modulation unit has a conversion table, and the element of the conversion table comprises the element for determining uniquely, and has a conversion rule that residues obtained by dividing the number of “1” in the element of a data string and the number of “1” in the element of a code word string to be converted by 2 are identically 1 or 0 for both residues. A channel bit string is modulated according to the conversion table, and further NRZI modulated by an NRZI modulation unit. Thus, DSV control can be performed with reduced redundancy.
摘要翻译：通过DSV位确定插入单元将DSV位插入到输入数据串中。调制单元具有转换表，并且转换表的元素包括用于唯一地确定的元素，并且具有转换规则，即通过将数据串的元素中的“1”数除以“ 要转换为2的代码字串的元素中的“1”对于两个残差都相同地为1或0。根据转换表调制通道位串，并且由NRZI调制单元进一步调制NRZI。因此，可以以减少的冗余来执行DSV控制。

50. 发明授权

US06340938B1 Demodulating device, demodulating method and supply medium with predetermined error length 失效
标题翻译：解调装置，解调方式和预定误差长度的供电介质
公开(公告)号：US06340938B1
公开(公告)日：2002-01-22
申请号：US09378064
申请日：1999-08-20
申请人： Toshiyuki Nakagawa
发明人： Toshiyuki Nakagawa
IPC分类号： H03M500
CPC分类号： H03M5/00 , H03M7/00 , H03M7/40 , H03M7/46
摘要： A demodulating device of the present invention in which an error code/constraint length determining unit, a minimum run continuation restricting code detecting unit and a minimum run/maximum run compensating code detecting unit specify a constraint length of a code having a predetermined length including an error and inverse conversion units and an error data demodulation table demodulate the code based on the specified constraint length, thus reducing error propagation by a simpler constitution when bit shift error is caused.
摘要翻译：本发明的解调装置，其中错误代码/约束长度确定单元，最小运行延续限制代码检测单元和最小运行/最大运行补偿代码检测单元指定具有预定长度的代码的约束长度，包括错误和逆转换单元以及错误数据解调表基于指定的约束长度来解调代码，从而通过更简单的结构减少错误传播，当发生位移错误时。

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