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41. 发明授权

US5059554A Method for forming polycrystalline silicon contacts 失效
标题翻译：形成多晶硅接触的方法
公开(公告)号：US5059554A
公开(公告)日：1991-10-22
申请号：US370615
申请日：1989-06-23
申请人： Charles R. Spinner , Fusen F. Chen , Fu-Tai Liou
发明人： Charles R. Spinner , Fusen F. Chen , Fu-Tai Liou
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/285 , H01L21/768 , H01L23/52
CPC分类号： H01L21/28525 , Y10S148/019 , Y10S148/147
摘要： A method for fabricating integrated circuits is used to improve contacts between polycrystalline interconnect and underlying polycrystalline or monocrystalline silicon regions. After contact openings are formed, a layer of titanium is deposited over the integrated circuit. The titanium is reacted in nitrogen to form a silicide layer only in the openings. Titanium nitride and unreacted titanium are then removed, and a layer of polycrystalline silicon deposited and patterned. The silicide layer between the polycrystalline interconnect and the underlying silicon ensures that a high quality contact is formed.

42. 发明授权

US4962414A Method for forming a contact VIA 失效
标题翻译：形成触点的方法VIA
公开(公告)号：US4962414A
公开(公告)日：1990-10-09
申请号：US366194
申请日：1989-06-08
申请人： Fu-Tai Liou , Robert O. Miller , Mohammed M. Farohani , Yu-Pin Han
发明人： Fu-Tai Liou , Robert O. Miller , Mohammed M. Farohani , Yu-Pin Han
IPC分类号： H01L21/768 , H01L23/485 , H01L23/532
CPC分类号： H01L21/76856 , H01L21/76802 , H01L21/76831 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L23/53223 , H01L2924/0002 , Y10S148/147 , Y10S257/915
摘要： A method for forming a connection between two levels in a semiconductor structure includes first forming a VIA (14) through an insulating layer (12) to an underlying structure (10). Sidewall spacers (22) and (24) are formed on the vertical walls of the VIA (14). The spacers (22) and (24) have tapered surfaces. A barrier layer (30) is then formed over the bottom surface of the VIA followed by CVD deposition of a conductive layer (32) of WSi.sub.2 to provide a conformal conductive layer. An aluminum layer (38) is then deposited by physical vapor deposition techniques with the descending portions of layer (32) providing a conductive connection between the aluminum layer (38) and the lower structure (10) in the VIA (14).
摘要翻译：用于在半导体结构中形成两层之间的连接的方法包括首先通过绝缘层（12）形成VIA（14）到下面的结构（10）。侧壁间隔件（22）和（24）形成在VIA（14）的垂直壁上。间隔件（22）和（24）具有锥形表面。然后在VIA的底表面上形成阻挡层（30），随后CVD沉积WSi2的导电层（32）以提供保形导电层。然后通过物理气相沉积技术沉积铝层（38），层（32）的下降部分在VIA（14）中的铝层（38）和下结构（10）之间提供导电连接。

43. 发明授权

US4863562A Method for forming a non-planar structure on the surface of a semiconductor substrate 失效
标题翻译：在半导体衬底的表面上形成非平面结构的方法
公开(公告)号：US4863562A
公开(公告)日：1989-09-05
申请号：US155148
申请日：1988-02-11
申请人： Frank R. Bryant , Fu-Tai Liou
发明人： Frank R. Bryant , Fu-Tai Liou
IPC分类号： H01L21/32 , H01L21/336 , H01L21/762
CPC分类号： H01L21/32 , H01L21/76202 , H01L29/66795
摘要： A method for increasing the width of a transistor includes first forming a nitride cap (14) over the substrate (10) and then forming trenches (24) and (26) on either side of the cap (14) and having tapered sidewalls (28) and (30). A conformal layer of nitride (32) is formed over the substrate and then anisotropically etched to form sidewall layers (34) and (36). Field oxide is grown in the trenches with birds beaks (42) and (44) extending upward under the sidewall layers (34) and (36). A portion of the sidewalls (28) and (30) of the trenches remain such that the overall surface area between the edges of the birds beaks (42) and (44) is increased. A layer of strip oxide is then grown on the substrate to provide rounded edges (47) and (49). The strip oxide is then removed by a fifty percent over etch to cause the birds beaks (42) and (44) to recede, thus further increasing the surface area. The gate electrode of a transistor (54) can then be disposed thereacross, thus increasing the width of the transistor for a given silicon surface area in the initial material.

44. 发明授权

US08871529B2 Method for manufacturing integrated circuit structure with magnetoresistance component 有权
标题翻译：用于制造具有磁阻部件的集成电路结构的方法
公开(公告)号：US08871529B2
公开(公告)日：2014-10-28
申请号：US13427875
申请日：2012-03-22
申请人： Fu-Tai Liou , Chien-Min Lee , Chih-Chien Liang , Nai-Chung Fu
发明人： Fu-Tai Liou , Chien-Min Lee , Chih-Chien Liang , Nai-Chung Fu
IPC分类号： H01L21/00 , H01L43/12
CPC分类号： H01L43/12
摘要： A method or manufacturing an integrated circuit structure with a magnetoresistance component is provided. A substrate is provided. A circuit structure layer including a metal pad is formed on the substrate. A dielectric layer is formed on the circuit structure. A metal damascene structure is formed in the dielectric layer. An opening is formed in the dielectric layer so as to form a step-drop. A magnetoresistance material layer is formed on the dielectric layer after forming the metal damascene structure and the opening. A photolithography process is applied to pattern the magnetoresistance material layer to form a magnetoresistance component electrically connected to the metal damascene structure.
摘要翻译：提供了一种制造具有磁阻部件的集成电路结构的方法或制造方法。提供基板。在基板上形成包括金属焊盘的电路结构层。在电路结构上形成介电层。在电介质层中形成金属镶嵌结构。在电介质层中形成开口以便形成分步骤。在形成金属镶嵌结构和开口之后，在电介质层上形成磁阻材料层。应用光刻工艺以对磁阻材料层进行图案化以形成电连接到金属镶嵌结构的磁阻组件。

45. 发明授权

US08749232B2 Magnatoresistive sensing component and agnatoresistive sensing device 有权
标题翻译：磁阻电感传感元件和电阻传感器
公开(公告)号：US08749232B2
公开(公告)日：2014-06-10
申请号：US13625009
申请日：2012-09-24
申请人： Nai-Chung Fu , Kuang-Ching Chen , Fu-Tai Liou
发明人： Nai-Chung Fu , Kuang-Ching Chen , Fu-Tai Liou
IPC分类号： G01R33/02
CPC分类号： G01R33/096 , G01R33/0011 , G01R33/0206 , G01R33/09
摘要： A magnetoresistive sensing component includes a strip of horizontal magnetoresistive layer, a conductive part and a first magnetic-field-sensing layer. The strip of horizontal magnetoresistive layer is disposed above a surface of a substrate and has a first side and a second side opposite the first side along its extending direction. The conductive part is disposed above or below the horizontal magnetoresistive layer and electrically coupled to the horizontal magnetoresistive layer. The conductive part and the horizontal magnetoresistive layer together form at least an electrical current path. The first magnetic-field-sensing layer is not parallel to the surface of the substrate and magnetically coupled to the horizontal magnetoresistive layer at the first side of the horizontal magnetoresistive layer.
摘要翻译：磁阻感测部件包括水平磁阻层条，导电部分和第一磁场感测层。水平磁阻层的条带设置在基板的表面上方，并且沿其延伸方向具有与第一侧相对的第一侧和第二侧。导电部分设置在水平磁阻层的上方或下方，并电耦合到水平磁阻层。导电部分和水平磁阻层一起形成至少一个电流路径。第一磁场感测层不平行于衬底的表面并且磁耦合到水平磁阻层的第一侧处的水平磁阻层。

46. 发明授权

US06320254B1 Plug structure 有权
标题翻译：插头结构
公开(公告)号：US06320254B1
公开(公告)日：2001-11-20
申请号：US09289773
申请日：1999-04-08
申请人： Fu-Tai Liou , Andy Chuang
发明人： Fu-Tai Liou , Andy Chuang
IPC分类号： H01L2348
CPC分类号： H05K3/325 , H01L23/13 , H01L23/3157 , H01L23/3171 , H01L23/32 , H01L23/49811 , H01L23/49816 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/81 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/05567 , H01L2224/13099 , H01L2224/16237 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48464 , H01L2224/48599 , H01L2224/48699 , H01L2224/48799 , H01L2224/81192 , H01L2224/81898 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2924/00015 , H01L2224/85399 , H01L2224/05599
摘要： A plug structure capable of directly coupling to a packageless bonding pad without having to go through a third conductive medium. The plug structure includes several plugs on a base substrate, such as a printed circuit board or a carrier. A solder is disposed on the plug surface in which the plug can be a cylinder or mushroom-like shape and the solder can be a film or a ball.
摘要翻译：一种能够直接耦合到无封装焊盘而不必经过第三导电介质的插头结构。插头结构在基底基板上包括几个插头，例如印刷电路板或载体。焊料被布置在插头表面上，其中插头可以是气缸或蘑菇状形状，并且焊料可以是膜或球。

47. 发明授权

US06180517B2 Method of forming submicron contacts and vias in an integrated circuit 失效
标题翻译：在集成电路中形成亚微米触点和通孔的方法
公开(公告)号：US06180517B2
公开(公告)日：2001-01-30
申请号：US08948904
申请日：1997-10-10
申请人： Fu-Tai Liou , Mehdi Zamanian
发明人： Fu-Tai Liou , Mehdi Zamanian
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/76807
摘要： A method is provided of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, an opening is formed partially through an insulating layer overlying a conductive region. Sidewall spacers are formed along the sidewalls of the opening. The remaining insulating layer is etched to expose the underlying conductive region. The contact dimension of the opening is smaller than the opening which can be printed from modern photolithography techniques. According to an alternate embodiment, the opening in the insulating layer expose the underlying conductive region. A polysilicon layer is formed over the insulating layer and in the opening. The polysilicon is oxidized to form a thick oxide in the opening and is etched back to form oxidized polysilicon sidewall spacers which decrease the contact dimension of the opening. According to a further alternate embodiment, an etch stop layer is formed between the insulating layer and conductive region and an opening is formed in the insulating layer exposing the etch stop layer. A sidewall spacer film is formed over the insulating layer and the etch stop layer, both layers having a similar etch rate for a given etchant. The etch stop and spacer layers are etched in the opening to expose the underlying conductive layer thereby forming a contiguous sidewall spacer and etch stop layer on the sides of and under the insulating layer, thereby decreasing the contact dimension of the opening.
摘要翻译：公开了一种通过半导体集成电路或接触形成小几何形状的方法，以及根据该半导体集成电路形成的集成电路。根据第一公开的实施例，部分地通过覆盖导电区域的绝缘层形成开口。沿着开口的侧壁形成侧壁间隔物。蚀刻剩余的绝缘层以暴露下面的导电区域。开口的接触尺寸小于可以用现代光刻技术印刷的开口。根据替代实施例，绝缘层中的开口暴露下面的导电区域。在绝缘层和开口中形成多晶硅层。多晶硅被氧化以在开口中形成厚的氧化物并被回蚀以形成减小开口的接触尺寸的氧化的多晶硅侧壁间隔物。根据另一替代实施例，在绝缘层和导电区域之间形成蚀刻停止层，并且在暴露蚀刻停止层的绝缘层中形成开口。在绝缘层和蚀刻停止层上形成侧壁间隔膜，两层对于给定的蚀刻剂具有相似的蚀刻速率。蚀刻停止层和间隔层在开口中被蚀刻以暴露下面的导电层，从而在绝缘层上和下方形成连续的侧壁间隔物和蚀刻停止层，从而减小开口的接触尺寸。

48. 发明授权

US6156634A Method of fabricating local interconnect 失效
标题翻译：制造局部互连的方法
公开(公告)号：US6156634A
公开(公告)日：2000-12-05
申请号：US173508
申请日：1998-10-15
申请人： Fu-Tai Liou
发明人： Fu-Tai Liou
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/44
CPC分类号： H01L21/32051 , H01L21/76895
摘要： A method of fabricating a local interconnect uses hydrogen plasma or hydrogen thermal treatment to form a local interconnect by transforming a part of the refractory metal oxide to a conductor. The local interconnect can be used to electrically connect two electrodes in a device, or to electrically connect same electrodes of different devices.
摘要翻译：制造局部互连的方法使用氢等离子体或氢热处理以通过将难熔金属氧化物的一部分转变成导体来形成局部互连。局部互连可用于电连接器件中的两个电极，或电连接不同器件的相同电极。

49. 发明授权

US6140198A Method of fabricating load resistor 失效
标题翻译：制造负载电阻的方法
公开(公告)号：US6140198A
公开(公告)日：2000-10-31
申请号：US187620
申请日：1998-11-06
申请人： Fu-Tai Liou
发明人： Fu-Tai Liou
IPC分类号： H01C7/00 , H01L21/02 , H01L21/822 , H01L21/8244 , H01L27/04 , H01L27/11 , H01L21/20
CPC分类号： H01L28/24 , H01L27/11 , H01L27/1112
摘要： A method of fabricating a load resistor. The load resistor is often applied in a static random access memory. The interconnect between different conductive regions such as gate and source/drain region is formed by applying a hydrogen treatment to a refractory metal oxide layer, while the load resistors are formed by applying a hydrogen treatment with different parameters as the former one. The insulation is formed by the refractory metal oxide layer which is not to be covered.
摘要翻译：一种制造负载电阻的方法。负载电阻通常应用在静态随机存取存储器中。通过对难熔金属氧化物层进行氢处理，形成不同导电区域（例如栅极和源极/漏极区域）之间的互连，而负载电阻器通过以不同的参数进行氢处理而形成。绝缘体由不被覆盖的难熔金属氧化物层形成。

50. 发明授权

US6031293A Package-free bonding pad structure 失效
标题翻译：无封装焊盘结构
公开(公告)号：US6031293A
公开(公告)日：2000-02-29
申请号：US299330
申请日：1999-04-26
申请人： Min-Chih Hsuan , Fu-Tai Liou
发明人： Min-Chih Hsuan , Fu-Tai Liou
IPC分类号： H01K23/48
CPC分类号： H01L23/3192 , H01L23/53295 , H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/04042 , H01L2224/05553 , H01L2224/0556 , H01L2224/05571 , H01L2224/0613 , H01L2224/06179 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/4813 , H01L2224/48464 , H01L24/45 , H01L2924/10253 , H01L2924/13091 , H01L2924/14
摘要： A package-free bonding pad structure on a silicon chip that includes a plurality of metal pads on the upper surface of the silicon chip and a passivation layer covering the upper surface of the silicon chip. The passivation layer has a plurality of open cavities directly above the metal pad areas for exposing a portion of each metal pad. Diameter of the open cavity gets smaller on approaching the upper surface of the passivation layer and grows bigger in the neighborhood of the metal pad area.
摘要翻译：一种硅芯片上的无封装焊盘结构，其包括硅芯片上表面上的多个金属焊盘和覆盖硅芯片上表面的钝化层。钝化层具有在金属焊盘区域正上方的多个开放空腔，用于暴露每个金属焊盘的一部分。开口腔的直径在接近钝化层的上表面时变小，并且在金属垫区域附近增大。

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