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1. 发明授权

US5371041A Method for forming a contact/VIA 失效
标题翻译：形成接触/ VIA的方法
公开(公告)号：US5371041A
公开(公告)日：1994-12-06
申请号：US831089
申请日：1992-02-07
申请人： Fu-Tai Liou , Robert O. Miller , Mohammed M. Farohani , Yu-Pin Han
发明人： Fu-Tai Liou , Robert O. Miller , Mohammed M. Farohani , Yu-Pin Han
IPC分类号： H01L21/768 , H01L23/485 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76856 , H01L21/76802 , H01L21/76831 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L23/53223 , H01L2924/0002 , Y10S148/147 , Y10S257/915
摘要： A method for forming a connection between two levels in a semiconductor structure includes first forming a VIA (14) through an insulating layer (12) to an underlying structure (10). Sidewall spacers (22) and (24) are formed on the vertical walls of the VIA (14). The spacers (22) and (24) have tapered surfaces. A barrier layer (30) is then formed over the bottom surface of the VIA followed by CVD deposition of a conductive layer (32) of WSi.sub.2 to provide a conformal conductive layer. An aluminum layer (38) is then deposited by physical vapor deposition techniques with the descending portions of layer (32) providing a conductive connection between the aluminum layer (38) and the lower structure (10) in the VIA (14).
摘要翻译：用于在半导体结构中形成两层之间的连接的方法包括首先通过绝缘层（12）形成VIA（14）到下面的结构（10）。侧壁间隔件（22）和（24）形成在VIA（14）的垂直壁上。间隔件（22）和（24）具有锥形表面。然后在VIA的底表面上形成阻挡层（30），随后CVD沉积WSi2的导电层（32）以提供保形导电层。然后通过物理气相沉积技术沉积铝层（38），层（32）的下降部分在VIA（14）中的铝层（38）和下结构（10）之间提供导电连接。

2. 发明授权

US4962414A Method for forming a contact VIA 失效
标题翻译：形成触点的方法VIA
公开(公告)号：US4962414A
公开(公告)日：1990-10-09
申请号：US366194
申请日：1989-06-08
申请人： Fu-Tai Liou , Robert O. Miller , Mohammed M. Farohani , Yu-Pin Han
发明人： Fu-Tai Liou , Robert O. Miller , Mohammed M. Farohani , Yu-Pin Han
IPC分类号： H01L21/768 , H01L23/485 , H01L23/532
CPC分类号： H01L21/76856 , H01L21/76802 , H01L21/76831 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L23/53223 , H01L2924/0002 , Y10S148/147 , Y10S257/915
摘要： A method for forming a connection between two levels in a semiconductor structure includes first forming a VIA (14) through an insulating layer (12) to an underlying structure (10). Sidewall spacers (22) and (24) are formed on the vertical walls of the VIA (14). The spacers (22) and (24) have tapered surfaces. A barrier layer (30) is then formed over the bottom surface of the VIA followed by CVD deposition of a conductive layer (32) of WSi.sub.2 to provide a conformal conductive layer. An aluminum layer (38) is then deposited by physical vapor deposition techniques with the descending portions of layer (32) providing a conductive connection between the aluminum layer (38) and the lower structure (10) in the VIA (14).
摘要翻译：用于在半导体结构中形成两层之间的连接的方法包括首先通过绝缘层（12）形成VIA（14）到下面的结构（10）。侧壁间隔件（22）和（24）形成在VIA（14）的垂直壁上。间隔件（22）和（24）具有锥形表面。然后在VIA的底表面上形成阻挡层（30），随后CVD沉积WSi2的导电层（32）以提供保形导电层。然后通过物理气相沉积技术沉积铝层（38），层（32）的下降部分在VIA（14）中的铝层（38）和下结构（10）之间提供导电连接。

3. 发明授权

US4886764A Process for making refractory metal silicide cap for protecting multi-layer polycide structure 失效
$Process for making refractory metal silicide cap for protecting multi-layer polycide structure$
标题翻译：制造难熔金属硅化物帽以保护多层聚硅氧烷结构的方法
公开(公告)号：US4886764A
公开(公告)日：1989-12-12
申请号：US357666
申请日：1989-05-25
申请人： Robert O. Miller , Fu-Tai Liou
发明人： Robert O. Miller , Fu-Tai Liou
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336
CPC分类号： H01L29/66575 , H01L21/28052 , H01L21/28518 , Y10S148/015 , Y10S148/019 , Y10S148/147
摘要： A process for forming a capping layer over a titanium silicide layer includes forming a layer of polysilicon (16) over a gate-oxide layer (14). A layer of titanium (18) is then formed over the poly layer (16) followed by deposition of a composite layer of tantalum silicide (20). The structure is then patterned and subjected to an annealing process to form a titanium silicide layer (22) covered by the capping layer (20) of tantalum silicide. The tantalum silicide provides a much higher oxidation resistant layer with the underlying titanium silicide providing the desirable conductive properties needed for long runs of interconnects on a semiconductor structure.

4. 外观设计

USD496909S1 Right angle connector handle 失效
标题翻译：直角连接器手柄
公开(公告)号：USD496909S1
公开(公告)日：2004-10-05
申请号：US29170595
申请日：2002-11-08
申请人： James D'Addario , Robert O. Miller
设计人： James D'Addario , Robert O. Miller

5. 发明授权

US5578872A Planar contact with a void 失效
标题翻译：与空虚平面接触
公开(公告)号：US5578872A
公开(公告)日：1996-11-26
申请号：US418838
申请日：1995-04-07
申请人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
发明人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L29/41 , H01L29/43
CPC分类号： H01L21/76843 , H01L21/76877 , Y10S257/915
摘要： A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A first conductive structure is formed over the integrated circuit. A dielectric is formed over the first conductive structure having a contact opening exposing a portion of the underlying first conductive layer. A barrier layer is formed in the bottom of the contact opening. A second, substantially conformal conductive layer is formed by chemical vapor deposition over the dielectric layer; along the sidewalls and in the bottom of the contact opening. A third conductive layer is then formed over the second conductive layer wherein the third conductive layer does not fill the contact opening. The second and third conductive layers are etched to form an interconnect substantially over the contact opening.
摘要翻译：提供了用于图案化集成电路的亚微米半导体层的方法，以及根据该集成电路形成的集成电路。在集成电路上形成第一导电结构。在第一导电结构上形成电介质，其具有暴露下面的第一导电层的一部分的接触开口。阻挡层形成在接触开口的底部。通过化学气相沉积在介电层上形成第二基本上保形的导电层; 沿着接触开口的侧壁和底部。然后在第二导电层上形成第三导电层，其中第三导电层不填充接触开口。第二和第三导电层被蚀刻以形成基本上在接触开口上的互连。

6. 发明授权

US5523624A Integrated circuit device structure with dielectric and metal stacked plug in contact hole 失效
标题翻译：集成电路器件结构，电介质和金属堆叠插头接触孔
公开(公告)号：US5523624A
公开(公告)日：1996-06-04
申请号：US112863
申请日：1993-08-26
申请人： Fusen E. Chen , Robert O. Miller , Girish A. Dixit
发明人： Fusen E. Chen , Robert O. Miller , Girish A. Dixit
IPC分类号： H01L21/28 , H01L21/285 , H01L21/302 , H01L21/3065 , H01L21/768 , H01L29/417 , H01L29/43
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/76843 , H01L21/76844 , H01L21/76877 , Y10S257/915
摘要： A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A conductive structure is formed on the integrated circuit. A dielectric layer is formed over the integrated circuit. A contact opening is formed in the dielectric layer exposing a portion of the underlying first conductive structure. A barrier layer is formed on the dielectric layer and in the contact opening. A substantially conformal layer is formed over the barrier layer and in the contact opening. The conformal layer is partially etched away wherein the conformal layer remains only in a bottom portion of the contact opening. A second conductive layer is formed over the barrier layer and the remaining conformal layer.
摘要翻译：提供了用于图案化集成电路的亚微米半导体层的方法，以及根据该集成电路形成的集成电路。在集成电路上形成导体结构。在集成电路上形成介电层。在电介质层中形成接触开口，暴露下面的第一导电结构的一部分。在电介质层和接触开口中形成阻挡层。在阻挡层和接触开口中形成基本上共形的层。共形层被部分蚀刻掉，其中保形层仅保留在接触开口的底部。在阻挡层和剩余的保形层上形成第二导电层。

7. 发明授权

US5491355A Self-aligned contact formation 失效
标题翻译：自对准接触形成
公开(公告)号：US5491355A
公开(公告)日：1996-02-13
申请号：US97366
申请日：1993-07-23
申请人： Che C. Wei , Chiara Zaccherini , Robert O. Miller , Girish A. Dixit
发明人： Che C. Wei , Chiara Zaccherini , Robert O. Miller , Girish A. Dixit
IPC分类号： H01L21/74 , H01L21/768 , H01L23/485 , H01L29/45 , H01L29/04
CPC分类号： H01L21/76895 , H01L21/743 , H01L23/485 , H01L29/456 , H01L2924/0002
摘要： A polycrystalline silicon layer is deposited and patterned to define a level of interconnect. Contact opening to lower conductive layers are then defined and patterned. A refractory metal such as tungsten is selectively deposited over the device, so that it adheres to the polycrystalline silicon in the interconnect leads and silicon of the lower conductive layer which is exposed in the contact openings. This provides a low resistance interconnect, and good, metal, contacts to underlying layers. Shared contacts between two or more polycrystalline silicon interconnect layers and in underlying conductive layers such as a substrate are easily formed using this technique.
摘要翻译：沉积并图案化多晶硅层以限定互连水平。然后对下导电层的接触开口被限定和图案化。诸如钨的难熔金属被选择性地沉积在器件上，使得其粘附到互连引线中的多晶硅和暴露在接触开口中的下导电层的硅。这提供了低电阻互连，以及良好的金属触点到底层。使用该技术容易地形成两个或更多个多晶硅互连层之间和底层导电层（例如基板）中的共用接触。

8. 发明授权

US5135884A Method of producing isoplanar isolated active regions 失效
标题翻译：生产ISOPLANAR隔离活性区的方法
公开(公告)号：US5135884A
公开(公告)日：1992-08-04
申请号：US677649
申请日：1991-03-28
申请人： Robert O. Miller
发明人： Robert O. Miller
IPC分类号： H01L21/205 , H01L21/302 , H01L21/3065 , H01L21/762
CPC分类号： H01L21/76245 , H01L21/76294
摘要： A method is provided for forming isoplanar isolated regions in an integrated circuit, and an integrated circuit formed according to the same. According to a first disclosed embodiment, a first epitaxial layer is formed over a substrate, the substrate having a (100) crystal orientation. A first masking layer is formed over the first epitaxial layer. The first masking layer is patterned and the first epitaxial layer is etched to form openings. The sidewalls of these openings have a (111) crystal orientation. The first masking layer is then removed and a second masking layer is formed in the openings. The first epitaxial layer is anodized and oxidized. The second masking layer is removed and a second epitaxial layer is formed in the openings. According to an alternate embodiment, after the first epitaxial layer is anodized, the second epitaxial layer is formed in the openings and the first epitaxial layer is then oxidized. According to a further alternate embodiment, the first epitaxial layer is anodized and oxidized after the second epitaxial layer is formed in the openings.

9. 发明授权

US07967643B1 Phone plug signal tip 有权
标题翻译：手机插头信号提示
公开(公告)号：US07967643B1
公开(公告)日：2011-06-28
申请号：US12804736
申请日：2010-07-28
申请人： James D'Addario , Robert O. Miller
发明人： James D'Addario , Robert O. Miller
IPC分类号： H01R24/00
CPC分类号： H01R24/58 , H01R2103/00 , H01R2201/16
摘要： An electric plug having a central signal shaft terminating in a tip, wherein the tip has a substantially frustoconical nose, a convex annular shoulder centered at an axial distance of less than 0.120 inch from the front end of the tip, (defining a bulbous portion) and a concave waist having a radius of curvature greater than about 0.75 inch, defining the detent adjacent to the bulbous portion.
摘要翻译：一种具有中心信号轴终止于尖端的电插塞，其中尖端具有基本上截头圆锥形的鼻部，以尖端前端小于0.120英寸的轴向距离为中心的凸形环形肩部（限定球根部分）以及具有大于约0.75英寸的曲率半径的凹腰部，限定邻近球根部分的棘爪。

10. 发明申请

US20080261447A1 Plug connector 有权
标题翻译：插头连接器
公开(公告)号：US20080261447A1
公开(公告)日：2008-10-23
申请号：US11788945
申请日：2007-04-23
申请人： James D'Addario , Robert O. Miller
发明人： James D'Addario , Robert O. Miller
IPC分类号： H01R9/05
CPC分类号： H01R9/0521 , H01R4/2408 , H01R4/26 , H01R24/40 , H01R2103/00
摘要： A plug connector for use with coaxial cable having a central signal wire in which a base member has a bore defined by a side wall adapted to receive the end of a coaxial cable. A member having a pointed end extends into the bore and is adapted to extend into the coaxial cable in contact with the central signal wire. A threaded bore extends through the side wall of the base member and a threaded screw member is mounted in the threaded bore. The screw member is adapted to be driven into the side of the coaxial cable. The screw member has a head portion at one end and a knife edge at the other end, the end having the knife edge having a pocket therein to receive the material of the coaxial cable cut by the knife edge.
摘要翻译：一种用于具有中心信号线的同轴电缆的插头连接器，其中基座构件具有由适于接收同轴电缆的端部的侧壁限定的孔。具有尖端的构件延伸到孔中并且适于延伸到与中心信号线接触的同轴电缆中。螺纹孔延伸穿过基部构件的侧壁，螺纹螺纹构件安装在螺纹孔中。螺钉构件适于被驱动到同轴电缆的侧面。螺钉构件在一端具有头部部分，在另一端具有刀刃，其端部具有刀口，其中具有凹口，以容纳由刀刃切割的同轴电缆的材料。

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