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41. 发明申请

US20120097205A1 MAGNESIUM-SILICON COMPOSITE MATERIAL AND PROCESS FOR PRODUCING SAME, AND THERMOELECTRIC CONVERSION MATERIAL, THERMOELECTRIC CONVERSION ELEMENT, AND THERMOELECTRIC CONVERSION MODULE EACH COMPRISING OR INCLUDING THE COMPOSITE MATERIAL 审中-公开
标题翻译：镁硅复合材料及其制造方法，以及热电转换材料，热电转换元件和包含复合材料的热电转换模块
公开(公告)号：US20120097205A1
公开(公告)日：2012-04-26
申请号：US13379593
申请日：2010-06-30
申请人： Tsutomu Iida , Yasuhiko Honda , Naoki Fukushima , Tatsuya Sakamoto , Yohiko Mito , Hirokuni Nanba , Yutaka Taguchi
发明人： Tsutomu Iida , Yasuhiko Honda , Naoki Fukushima , Tatsuya Sakamoto , Yohiko Mito , Hirokuni Nanba , Yutaka Taguchi
IPC分类号： H01L35/28 , H01B1/04
CPC分类号： H01L35/22 , C01B33/06 , C01P2002/70 , C01P2004/61 , C04B35/58085 , C04B35/6261 , C04B35/62665 , C04B35/645 , C04B35/6455 , C04B2235/40 , C04B2235/401 , C04B2235/402 , C04B2235/407 , C04B2235/408 , C04B2235/428 , C04B2235/6562 , C04B2235/6565 , C04B2235/6582 , C04B2235/666 , C04B2235/72 , C04B2235/80 , C04B2235/9607 , C22C23/00 , F27D17/004 , H01M4/1395 , H01M4/38 , H01M4/383 , Y02E60/324
摘要： Provided is a magnesium-silicon composite material which contains Mg2Si as an intermetallic compound imposing no burden on the environment, is suitable for use as a material for thermoelectric conversion modules, and has excellent thermoelectric conversion performance. The magnesium-silicon composite material has a dimensionless figure-of-merit parameter at 866K of 0.665 or larger. This magnesium-silicon composite material can have high thermoelectric conversion performance when used in, for example, a thermoelectric conversion module.
摘要翻译：提供一种含有作为金属间化合物的Mg2Si作为环境无负担的镁硅复合材料，适用于热电转换模块的材料，具有优异的热电转换性能。镁硅复合材料在866K下具有0.665或更大的无量纲品质参数。当在例如热电转换模块中使用时，该镁硅复合材料可以具有高的热电转换性能。

42. 发明授权

US08159884B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08159884B2
公开(公告)日：2012-04-17
申请号：US12884878
申请日：2010-09-17
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C7/12
CPC分类号： G11C16/3418 , G11C16/26
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor, a word line, a row decoder, a sense amplifier which determines the data in the memory cell transistor via the bit line, a first bit line clamp transistor connected in series between the bit line and the sense amplifier, a second bit line clamp transistor connected in parallel to the first bit line clamp transistor and having a current driving capability higher than that of the first bit line clamp transistor, and a bit line control circuit which turns on the first bit line clamp transistor and the second bit line clamp transistor using a common gate voltage during a predetermined period from a start of charge of the bit line, and turns off only the second bit line clamp transistor when the predetermined period has elapsed.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括存储单元晶体管，字线，行解码器，通过位线确定存储单元晶体管中的数据的读出放大器，串联连接的第一位线钳位晶体管在位线和读出放大器之间，与第一位线钳位晶体管并联连接的第二位线钳位晶体管，其电流驱动能力高于第一位线钳位晶体管的电流驱动能力，以及位线控制电路，在第一位线钳位晶体管和第二位线钳位晶体管之间，在从位线开始充电的预定时间期间使用公共栅极电压，并且当经过预定周期时，仅关断第二位线钳位晶体管。

43. 发明授权

US07864614B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07864614B2
公开(公告)日：2011-01-04
申请号：US12338041
申请日：2008-12-18
申请人： Tatsuro Midorikawa , Yasuhiko Honda , Gyosho Chin
发明人： Tatsuro Midorikawa , Yasuhiko Honda , Gyosho Chin
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C5/147 , G11C8/08 , G11C11/5642 , G11C16/28 , G11C16/30 , G11C2211/5621
摘要： A semiconductor memory device includes a memory cell array which includes a plurality of memory cells which are arrayed in a matrix at intersections between a plurality of word lines and a plurality of bit lines and a power supply circuit which includes a first band gap reference circuit which outputs a first output voltage, and a second band gap reference circuit which outputs a second output voltage having lower temperature characteristics than the first output voltage on a low temperature side, and generates a power supply voltage on the basis of the second output voltage at a time of a data write operation of the memory cells.
摘要翻译：半导体存储器件包括存储单元阵列，其包括在多个字线和多个位线之间的交叉处以矩阵排列的多个存储器单元，以及包括第一带隙基准电路的电源电路，输出第一输出电压和第二带隙基准电路，其在低温侧输出具有比第一输出电压低的温度特性的第二输出电压，并且基于第二输出电压在第二输出电压存储单元的数据写入操作的时间。

44. 发明授权

US07859915B2 Semiconductor device and method of controlling the same 失效
标题翻译：半导体装置及其控制方法
公开(公告)号：US07859915B2
公开(公告)日：2010-12-28
申请号：US11770381
申请日：2007-06-28
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C7/10
CPC分类号： H01L27/115 , G11C29/20
摘要： A semiconductor device comprises a board, a first semiconductor storage device placed on the board, and a second semiconductor storage device placed on the board. Each of the first and second semiconductor storage devices has a first pad for inputting a chip enable signal, a second pad for inputting a write enable signal, a third pad for inputting an output enable signal, a fourth pad for inputting an address signal, and a fifth pad for inputting data. The first semiconductor storage device has a sixth pad which is electrically connected to the first pad of the second semiconductor device, and the second semiconductor storage device has a seventh pad which is electrically connected to the first pad of the first semiconductor device.
摘要翻译：一种半导体器件包括一个板，一个位于该板上的第一个半导体存储器件，以及一个位于该板上的第二个半导体存储器件。第一和第二半导体存储装置中的每一个具有用于输入芯片使能信号的第一焊盘，用于输入写使能信号的第二焊盘，用于输入输出使能信号的第三焊盘，用于输入地址信号的第四焊盘，以及用于输入数据的第五个垫。第一半导体存储装置具有电连接到第二半导体器件的第一焊盘的第六焊盘，并且第二半导体存储器件具有电连接到第一半导体器件的第一焊盘的第七焊盘。

45. 发明申请

US20090115500A1 VOLTAGE GENERATING CIRCUIT 失效
标题翻译：电压发生电路
公开(公告)号：US20090115500A1
公开(公告)日：2009-05-07
申请号：US12260366
申请日：2008-10-29
申请人： Masaaki Kuwagata , Yasuhiko Honda , Yoshihiko Kamata
发明人： Masaaki Kuwagata , Yasuhiko Honda , Yoshihiko Kamata
IPC分类号： G05F1/10
CPC分类号： G11C16/30 , G11C5/143 , G11C5/145 , H02M3/073 , H02M2001/0025 , H02M2001/0032 , Y02B70/16
摘要： A voltage generating circuit for outputting a voltage from an output terminal, has a first voltage dividing circuit which is connected between the output terminal and ground; a switch circuit connected between the output terminal and the first voltage dividing circuit; a first voltage detecting circuit which outputs a first pumping signal corresponding to a comparison result; a second voltage dividing circuit which is connected between the output terminal and the ground; a second voltage detecting circuit which outputs a second pumping signal corresponding to a comparison result; a pump circuit that outputs a voltage boosted from a power supply voltage; and a boost circuit which has a capacitive element having one end connected to the voltage dividing resistor of the first voltage dividing circuit.
摘要翻译：用于从输出端子输出电压的电压产生电路具有连接在输出端子与地之间的第一分压电路; 连接在输出端和第一分压电路之间的开关电路; 第一电压检测电路，输出与比较结果对应的第一泵浦信号; 连接在输出端子和地之间的第二分压电路; 第二电压检测电路，其输出与比较结果相对应的第二泵浦信号; 输出从电源电压提升的电压的泵电路; 以及升压电路，其具有一端与第一分压电路的分压电阻连接的电容元件。

46. 发明授权

US07420863B2 Nonvolatile semiconductor memory device which stores multivalue data 失效
公开(公告)号：US07420863B2
公开(公告)日：2008-09-02
申请号：US11763743
申请日：2007-06-15
申请人： Yasuhiko Honda , Masao Kuriyama
发明人： Yasuhiko Honda , Masao Kuriyama
IPC分类号： G11C7/02
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5634
摘要： A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

47. 发明授权

US07397716B2 Nonvolatile semiconductor memory device which stores multivalue data 有权
公开(公告)号：US07397716B2
公开(公告)日：2008-07-08
申请号：US11401286
申请日：2006-04-11
申请人： Yasuhiko Honda , Masao Kuriyama
发明人： Yasuhiko Honda , Masao Kuriyama
IPC分类号： G11C7/02
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5634
摘要： A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

48. 发明授权

US07362587B2 Multi-chip package 失效
标题翻译：多芯片封装
公开(公告)号：US07362587B2
公开(公告)日：2008-04-22
申请号：US11677351
申请日：2007-02-21
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： H05K7/02 , H05K7/06 , H05K7/08 , H05K7/10
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1066 , H01L25/18 , H01L2924/0002 , H01L2924/00
摘要： A multi-chip package includes a first semiconductor memory controlled by a clock signal and an inverted clock signal, and a second semiconductor memory controlled by the clock signal. The first semiconductor memory and the second semiconductor memory each include a circuit for guaranteeing that a signal delay is suppressed between a peripheral circuit, and a pad to which the clock signal is input, a pad to which the inverted clock signal is input, a pad for outputting a data enable signal and a pad for outputting a data signal. Thus, it is guaranteed that the signal delay is suppressed, and the reliability of the multi-chip package is improved.
摘要翻译：多芯片封装包括由时钟信号和反相时钟信号控制的第一半导体存储器和由时钟信号控制的第二半导体存储器。第一半导体存储器和第二半导体存储器各自包括用于保证在外围电路和输入时钟信号的焊盘之间抑制信号延迟的电路，输入反相时钟信号的焊盘，焊盘用于输出数据使能信号和用于输出数据信号的焊盘。因此，可以保证信号延迟得到抑制，提高了多芯片封装的可靠性。

49. 发明授权

US07088631B2 Semiconductor storage apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US07088631B2
公开(公告)日：2006-08-08
申请号：US11019271
申请日：2004-12-23
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C7/02 , G11C7/12 , G11C16/24
摘要： A semiconductor storage apparatus includes a cell array including memory cells and reference cells, normal column selection transistors connected to columns of the memory cells, a normal data line array including normal data lines connected to columns of the memory cells, first dummy data lines formed of a same wiring layer of which the normal data lines are formed, a normal data line charging circuit, reference column selection transistors connected to reference columns of the reference cells, a reference data line array including reference data lines formed of a same wiring layer of which the normal data lines are formed, second dummy data lines formed of a same wiring layer of which the reference data lines are formed, a reference data line charging circuit, a first dummy data line charging circuit, a second dummy data line charging circuit, and a sense amplifier which senses data stored in the memory cells.
摘要翻译：一种半导体存储装置，包括：包括存储单元和参考单元的单元阵列，连接到存储单元的列的正常列选择晶体管，包括连接到存储单元的列的正常数据线的正常数据线阵列，由形成正常数据线的相同布线层，正常数据线充电电路，连接到参考单元的参考列的参考列选择晶体管，包括由相同布线层形成的参考数据线的参考数据线阵列形成正常的数据线，由形成基准数据线的相同布线层形成的第二虚拟数据线，参考数据线充电电路，第一虚拟数据线充电电路，第二虚拟数据线充电电路和感测放大器，其感测存储在存储单元中的数据。

50. 发明申请

US20050024942A1 SEMICONDUCTOR MEMORY DEVICE HAVING A BURST CONTINUOUS READ FUNCTION 有权
标题翻译：具有BURST连续读功能的半导体存储器件
公开(公告)号：US20050024942A1
公开(公告)日：2005-02-03
申请号：US10692329
申请日：2003-10-22
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C16/02 , G11C7/10 , G11C11/34 , G11C16/06 , G11C29/00
CPC分类号： G11C29/846 , G11C7/103 , G11C7/1051 , G11C7/106 , G11C7/1069
摘要： Several sense amplifiers detect data read from a memory cell of a bank in accordance with read address. Several first holding circuits individually hold data output from the sense amplifiers. Several second holding circuits hold data output from the corresponding first holding circuit after being delayed by time that the read address gains with respect to the burst address. Decoders individually supply data held in several second holding circuits to the corresponding line of a bus line.
摘要翻译：几个感测放大器根据读取地址检测从存储体的存储单元读取的数据。几个第一保持电路分别保存来自读出放大器的数据输出。几个第二保持电路在被读取地址相对于突发地址增益的时间延迟之后，保持来自对应的第一保持电路的数据输出。解码器将保持在几个第二保持电路中的数据单独提供给总线的相应线路。

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