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41. 发明授权

US06748559B1 Method and system for reliably defining and determining timeout values in unreliable datagrams 有权
标题翻译：用于在不可靠数据报中可靠地定义和确定超时值的方法和系统
公开(公告)号：US06748559B1
公开(公告)日：2004-06-08
申请号：US09692349
申请日：2000-10-19
申请人： Gregory Francis Pfister , Giles Roger Frazier , Danny Marvin Neal , Steven Mark Thurber
发明人： Gregory Francis Pfister , Giles Roger Frazier , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1100
CPC分类号： H04L41/00 , H04L41/046 , H04L41/0806 , H04L41/082 , H04L41/12 , H04L43/0852
摘要： A method for managing allocation of network resources within the distributed computer system is provided. Specifically, the network traversal time and the end node response time for requests and/or packets being routed in a switch-connected system area network are utilized to determine the total round trip time for completion of the particular network operation. The sum of the timeout values for all switches that participate in routing the request from a requester (source) to the receptor node (target) is provided to the requester's channel adapter (CA). The time-out values are provided by the switch manufacturer and are sent to a network Subnet Manager (SM) via SM packets (SMP). The timeout values added together represent the SubnetTimeout. The time-out value of the target channel adapter (CA), the ResponseTime, is also provided to the requester. The requester then utilizes one of two timeout equations to calculate the overall response time required for the request to be completed. A timer is started and the elapsed time to complete the request is monitored and compared with the overall response time calculated. When the timer expires before a response is received at the requester, the operation is assumed to have failed and the network resources being utilized by the request may be reallocated to another network operation.
摘要翻译：提供了一种管理分布式计算机系统内网络资源分配的方法。具体地，利用在交换机连接的系统区域网络中路由的请求和/或分组的网络遍历时间和终止节点响应时间来确定完成特定网络操作的总往返时间。参与将请求从请求者（源）路由到接收节点（目标）的所有交换机的超时值的总和提供给请求者的信道适配器（CA）。超时值由交换机制造商提供，并通过SM数据包（SMP）发送到网络子网管理器（SM）。添加的超时值表示SubnetTimeout。目标通道适配器（CA）的超时值ResponseTime也提供给请求者。然后，请求者使用两个超时方程之一来计算请求完成所需的总体响应时间。启动定时器，并监视完成请求的经过时间，并与计算的总响应时间进行比较。当定时器在请求者接收到响应之前到期时，假设该操作已经失败，并且该请求所利用的网络资源可能被重新分配到另一个网络操作。

42. 发明授权

US06718422B1 Enhanced bus arbiter utilizing variable priority and fairness 失效
标题翻译：增强总线仲裁器利用可变优先权和公平性
公开(公告)号：US06718422B1
公开(公告)日：2004-04-06
申请号：US09363947
申请日：1999-07-29
申请人： Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1336
CPC分类号： G06F13/364 , G06F13/4031
摘要： A bus arbiter for a computer system having a bus for connection to a plurality of bus devices where each bus device requests control of bus by use of a bus request signal. The bus arbiter contains logic which incorporates a fairness scheme for controlling and prioritizing the bus request signals based on a predetermined priority of each bus device and each bus device's prior access within a fairness cycle. Each device's prior access is tracked by bits in a data register and is determined by whether or not the device actually received or sent information over the bus, and not by a simple granting of access which could result in a retry signal.
摘要翻译：一种用于计算机系统的总线仲裁器，其具有用于连接到多个总线设备的总线，其中每个总线设备通过使用总线请求信号来请求总线的控制。总线仲裁器包含逻辑，其包含用于基于每个总线设备的预定优先级和每个总线设备在公平循环内的先前访问来控制和优先化总线请求信号的公平方案。每个设备的先前访问由数据寄存器中的位跟踪，并且由设备是否实际上通过总线接收或发送信息而不是简单地授予可能导致重试信号的访问来确定。

43. 发明授权

US06295568B1 Method and system for supporting multiple local buses operating at different frequencies 失效
标题翻译：支持多个本地总线工作在不同频率的方法和系统
公开(公告)号：US06295568B1
公开(公告)日：2001-09-25
申请号：US09055414
申请日：1998-04-06
申请人： Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1338
CPC分类号： G06F13/4022
摘要： A method and system for supporting multiple Peripheral Component Interconnect (PCI) local buses through a single PCI host bridge having multiple PCI interfaces within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. One or more PCI local buses are connected to the system bus through a single PCI host bridge having bus and frequency control logic and bus clocks. The PCI local buses include sets of in-line electronic switches, dividing each PCI local bus into PCI local bus segments for supporting more PCI peripheral component slots then are called out by the PCI local bus standard. The sets of in-line electronic switches are open and closed in accordance with the bus and frequency control logic within the PCI host bridge thereby allowing the PCI peripheral component slots to operate at different bus frequencies, including bus frequencies higher than 66 MHz by using the bus clocks. The sets of in-line electronic switches further allowing different bus segments on the same PCI logical bus to dynamically be operated at different frequencies.
摘要翻译：公开了一种通过在数据处理系统内具有多个PCI接口的单个PCI主机桥来支持多个外围组件互连（PCI）局部总线的方法和系统。根据本发明的方法和系统，处理器和系统存储器连接到系统总线。一个或多个PCI本地总线通过具有总线和频率控制逻辑和总线时钟的单个PCI主机桥连接到系统总线。 PCI本地总线包括一系列在线电子开关，将每个PCI本地总线划分为PCI本地总线段，以支持更多的PCI外设组件插槽，然后由PCI本地总线标准进行调用。这些串联式电子开关根据PCI主机桥内的总线和频率控制逻辑开启和关闭，从而允许PCI外设组件插槽在不同的总线频率下工作，包括高于66MHz的总线频率，通过使用总线时钟这些在线电子开关进一步允许在同一PCI逻辑总线上的不同总线段动态地以不同的频率工作。

44. 发明授权

US06223299B1 Enhanced error handling for I/O load/store operations to a PCI device via bad parity or zero byte enables 失效
标题翻译：通过坏的奇偶校验或零字节使I / O加载/存储操作到PCI设备的增强的错误处理能够实现
公开(公告)号：US06223299B1
公开(公告)日：2001-04-24
申请号：US09072418
申请日：1998-05-04
申请人： Douglas Craig Bossen , Charles Andrew McLaughlin , Danny Marvin Neal , James Otto Nicholson , Steven Mark Thurber
发明人： Douglas Craig Bossen , Charles Andrew McLaughlin , Danny Marvin Neal , James Otto Nicholson , Steven Mark Thurber
IPC分类号： G06F1100
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/0793
摘要： Device selects lines from each I/O device are brought into a PCI host bridge individually so that the device number of a failing device may be logged in an error register when an error is seen on the PCI bus. Until the error register is reset, subsequent load and store operations are delayed until the device number of the subject device may be checked against the error register. If the subject device is a previously failing device, the load/store operation to that device is prevented from completing, either by forcing bad parity or zeroing all byte enables. By forcing bad parity of zero byte enables, the I/O device will respond to the load or store request by activating its device select line, but will not accept store data. Operations to devices which are not logged in the error register are permitted to proceed normally, as are all load store operations when the error register is clear. Normal system operations are thus not impacted, and operations during error recovery are permitted to proceed if no further damage will be caused by such operations.
摘要翻译：设备选择每个I / O设备的线路分别插入PCI主机桥，以便在PCI总线上出现错误时，可能会将故障设备的设备号记录在错误寄存器中。在错误寄存器复位之前，后续的加载和存储操作将被延迟，直到可以针对错误寄存器检查主体设备的设备编号。如果主机设备是先前发生故障的设备，则通过强制坏的奇偶校验或归零所有字节使能来防止对该设备的加载/存储操作完成。通过强制零字节的不良奇偶使能，I / O设备将通过激活其设备选择行来响应加载或存储请求，但不接受存储数据。允许对未登录在错误寄存器中的设备进行操作，正常情况下，正常情况下进行加载存储操作。因此，正常的系统操作不会受到影响，并且如果这种操作不会造成进一步的损坏，则允许错误恢复期间的操作进行。

45. 发明授权

US5761461A Method and system for preventing peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a data processing system 失效
标题翻译：用于防止在数据处理系统内的多个PCI主机桥的外围组件互连（PCI）对等访问的方法和系统
公开(公告)号：US5761461A
公开(公告)日：1998-06-02
申请号：US766735
申请日：1996-12-13
申请人： Danny Marvin Neal , Steven Mark Thurber
发明人： Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F13/40 , G06F13/42 , G06F13/00
CPC分类号： G06F13/4027
摘要： A method for preventing peer-to-peer access across separate Peripheral Component Interconnect (PCI) host bridges within a data-processing system is described. In accordance with the method and system of the present invention, during an access request from a PCI device, a first determination is made as to whether or not the access request is for a system memory attached to a system bus. In response to a determination that the access request is not for a system memory attached to the system bus, another determination is made as to whether or not the access request is for a PCI device under the same PCI host bridge as the requesting PCI device. In response to a determination that the access request is not for a PCI device under the same PCI host bridge as the requesting PCI device, denying the access request such that a PCI peer-to-peer access across separate PCI host bridges within a data processing system is prevented.
摘要翻译：描述了用于防止在数据处理系统内的分开的外围组件互连（PCI）主机桥的对等访问的方法。根据本发明的方法和系统，在来自PCI设备的访问请求期间，首先确定访问请求是否用于连接到系统总线的系统存储器。响应于确定访问请求不是连接到系统总线的系统存储器，则另外确定访问请求是否用于与请求的PCI设备相同的PCI主机桥下的PCI设备。响应于确定访问请求不是针对与请求的PCI设备相同的PCI主机桥下的PCI设备，拒绝访问请求，使得跨数据处理中的单独PCI主机桥的PCI对等访问系统被阻止。

46. 发明授权

US5673399A System and method for enhancement of system bus to mezzanine bus transactions 失效
标题翻译：将系统总线增强到夹层总线交易的系统和方法
公开(公告)号：US5673399A
公开(公告)日：1997-09-30
申请号：US552034
申请日：1995-11-02
申请人： Guy Lynn Guthrie , Danny Marvin Neal , Edward John Silha , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Danny Marvin Neal , Edward John Silha , Steven Mark Thurber
IPC分类号： G06F13/36 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4027
摘要： A data processing system includes a host processor, a number of peripheral devices, and one or more bridges which may connect between the host, peripheral devices and other hosts or peripheral devices such as in a network. Each bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) and a secondary bus wherein for the purpose of clarity, the primary bus will be considered as the source for outbound transactions and the destination for inbound transactions and the secondary bus would be considered the destination for outbound transactions and the source for inbound transactions. The host bridge includes an outbound data path, an inbound data path, and a control mechanism. The outbound data path includes a queued buffer for storing transactions in order of receipt from the primary bus where the requests in the queued buffer may be mixed as between read requests and write transactions, the outbound path also includes a number of parallel buffers for storing read reply data and address information. The inbound path is a mirror image of the outbound path with read requests and write requests being stored in a sequential buffer and read replies being stored in a number of parallel buffers. Both the inbound path and the outbound path in the host bridge are controlled by a state machine which takes into consideration activity in both directions and permits or inhibits bypass transactions based on the protocol of the buses being interconnected through the bridge.
摘要翻译：数据处理系统包括主处理器，多个外围设备以及可以在主机，外围设备和其他主机或诸如网络中的外围设备之间连接的一个或多个网桥。每个桥梁（如PCI主机桥）连接在主总线（例如系统总线）和辅助总线之间，为了清楚起见，主总线将被视为出站事务的来源和入站事务的目的地，辅助总线将被视为出站交易的目的地和入站交易的来源。主桥包括出站数据路径，入站数据路径和控制机制。出站数据路径包括排队缓冲器，用于按照从主总线接收的顺序存储事务，其中排队缓冲器中的请求可以在读请求和写事务之间混合，出站路径还包括多个用于存储读取的并行缓冲器回复数据和地址信息。入站路径是出站路径的镜像，读取请求和写入请求存储在顺序缓冲区中，并且读取回复存储在多个并行缓冲区中。主桥中的入站路径和出站路径都由状态机控制，该状态机考虑到两个方向的活动，并且基于通过桥互连的总线的协议允许或禁止旁路交易。

47. 发明授权

US06760793B2 Transaction credit control for serial I/O systems 失效
公开(公告)号：US06760793B2
公开(公告)日：2004-07-06
申请号：US10207449
申请日：2002-07-29
申请人： Richard A. Kelley , Danny Marvin Neal
发明人： Richard A. Kelley , Danny Marvin Neal
IPC分类号： G06F302
CPC分类号： G06F13/385
摘要： A method and implementing computer system are provided which allows for significantly improved input/output (I/O) subsystem designs in all systems which include serialized I/O transactions such as so-called Express specification systems. Transaction control methodology is implemented to improve Express design requirements for Express devices such as an Express switch, Express-PCI bridge, endpoint, and root complex. This is accomplished by utilizing improved transaction ordering and state machine and corresponding buffer design and improved flow control credit methodology which enables improved processing for controlling transactions flowing through Express devices including Express switches and Express-PCI bridges. An Express-PCI/PCIX transition bridge design is also provided, along with the flow control credit methodology and implementation within the Express-PCI/PCIX bridge design to enable efficient interfacing between Express and legacy or existing PCI/PCIX systems.

48. 发明授权

US06795107B1 Video conferencing apparatus and method therefor 有权
标题翻译：视频会议装置及其方法
公开(公告)号：US06795107B1
公开(公告)日：2004-09-21
申请号：US09353948
申请日：1999-07-15
申请人： Danny Marvin Neal , Richard A. Kelley
发明人： Danny Marvin Neal , Richard A. Kelley
IPC分类号： H04N714
CPC分类号： H04N21/4143 , H04N7/142 , H04N7/15 , H04N7/157 , H04N21/4223 , H04N21/4788
摘要： A videoconferencing apparatus and method are implemented. Each participant in the videoconference has a representation within the system as a “stick figure,” or linear frame, object similar to “stick figure” objects in the computer animation art. A participant's linear frame object is endowed with the persona of the participant by wrapping the object with an outer texture generated from a preloaded image of the participant. Small tags placed at preselected locations on each participant are detected by the videoconferencing system, and each of the participants stick figures is animated in accordance with changes in positions as revealed by the tags.
摘要翻译：实现视频会议装置和方法。视频会议中的每个参与者在系统中具有作为“棒图”或线性框架的对象，类似于计算机动画艺术中的“棒图”对象。参与者的线性框架对象通过用从参与者的预加载图像生成的外部纹理包裹对象来赋予参与者的角色。通过视频会议系统检测放置在每个参与者的预选位置的小标签，并且每个参与者粘贴的人物根据标签显示的位置变化而动画化。

49. 发明授权

US07165110B2 System and method for simultaneously establishing multiple connections 有权
标题翻译：同时建立多个连接的系统和方法
公开(公告)号：US07165110B2
公开(公告)日：2007-01-16
申请号：US09903725
申请日：2001-07-12
申请人： Danny Marvin Neal , Gregory Francis Pfister , Renato John Recio
发明人： Danny Marvin Neal , Gregory Francis Pfister , Renato John Recio
IPC分类号： G06F15/16 , G06F11/30 , G06F12/14 , H04L9/32 , H04L9/00
CPC分类号： H04L29/06 , H04L69/14 , H04L69/22 , Y02D50/30
摘要： A system and method for establishing multiple connections using a private data field of a communication management protocol is provided. With the present invention, a Service ID identifies a specific consumer and the private data field contains a list of connection attributes for each connection that is to be established. An active side requests a connection and the passive side replies to the connection request. The active side sends the passive side a connection establishment request. This connection establishment request includes a Service ID which identifies a passive side process associated with a service. This connection establishment request also includes communication attributes of one or more connected services and datagram services associated with the Service ID. The passive passes the connection request to a process associated with the service. If the passive side process does not wish to carry out the service, a negative reply message is returned to the active side. If the passive side process does wish to carry out the service, a positive reply is returned to the active side and the reply includes the communication attributes for the connection and unreliable services associated with the Service ID used in the connection establishment request.
摘要翻译：提供了一种使用通信管理协议的私有数据字段建立多个连接的系统和方法。利用本发明，服务ID标识特定消费者，并且专用数据字段包含要建立的每个连接的连接属性的列表。主动端请求连接，被动方回复连接请求。主动端将被动方发送连接建立请求。该连接建立请求包括识别与服务相关联的被动侧进程的服务ID。该连接建立请求还包括与服务ID相关联的一个或多个连接的服务和数据报服务的通信属性。被动将连接请求传递给与服务关联的进程。如果被动侧进程不希望执行该服务，则将一个否定的回复消息返回到主动端。如果被动侧进程确实希望执行该服务，则肯定的答复返回到主动侧，并且回复包括用于连接的通信属性和与在连接建立请求中使用的服务ID相关联的不可靠服务。

50. 发明授权

US07149220B2 System, method, and product for managing data transfers in a network 有权
公开(公告)号：US07149220B2
公开(公告)日：2006-12-12
申请号：US10132456
申请日：2002-04-25
申请人： Bruce Leroy Beukema , Thomas Anthony Gregg , Danny Marvin Neal , Renato John Recio
发明人： Bruce Leroy Beukema , Thomas Anthony Gregg , Danny Marvin Neal , Renato John Recio
IPC分类号： H04L12/56
CPC分类号： H04L29/06 , H04L49/90 , H04L69/326
摘要： A method, system, and product in a data processing system are disclosed for managing data transmitted from a first end node to a second end node included in the data processing system. A logical connection is established between the first end node and the second end node prior to transmitting data between the end nodes. An instance number is associated with this particular logical connection. The instance number is included in each packet transmitted between the end nodes while this logical connection remains established. The instance number remains constant during this logical connection. The instance number is altered, such as by incrementing it, each time a logical connection between these end nodes is reestablished. Thus, each packet is associated with a particular instance of the logical connection. When a packet is received, the instance number included in the packet may be used to determine whether the packet is a stale packet transmitted during a previous logical connection between these end nodes.

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