专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US08363367B2 Electrical overstress protection circuit 有权
标题翻译：电气过载保护电路
公开(公告)号：US08363367B2
公开(公告)日：2013-01-29
申请号：US12632015
申请日：2009-12-07
申请人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
发明人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
IPC分类号： H02H9/00
CPC分类号： H01L27/0251 , G06F17/5045
摘要： A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond.
摘要翻译：提供了一种用于电力过应力（EOS）保护的半导体电路。半导体电路采用静电放电（ESD）保护电路，其具有连接到放电电容器的电阻 - 电容（RC）延时网络。连接具有电压骤回特性或二极管行为的电子部件，以改变在EOS事件下放电晶体管的栅极的逻辑状态。特别地，电子部件被配置成在电应力（EOS）条件以及ESD事件的整个持续时间期间打开放电电容器的栅极。可以采用设计结构来设计或制造半导体电路，该半导体电路在没有时间限制的情况下提供针对EOS状态的保护，即不受时间长度超过1微秒的EOS事件的RC时间延迟网络的时间常数的限制。

42. 发明授权

US07203045B2 High voltage ESD power clamp 失效
标题翻译：高压ESD电源钳
公开(公告)号：US07203045B2
公开(公告)日：2007-04-10
申请号：US10711748
申请日：2004-10-01
申请人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Mahmoud A. Mousa , Mujahid Muhammad , Christopher S. Putnam
发明人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Mahmoud A. Mousa , Mujahid Muhammad , Christopher S. Putnam
IPC分类号： H02H3/20 , H02H3/22 , H02H9/00 , H02H9/04
CPC分类号： H01L27/0266 , H03K17/08142
摘要： A structure and apparatus is provided for an electrostatic discharge power clamp, for use with high voltage power supplies. The power clamp includes a network of transistor devices, for example, nFETs arranged in series between a power rail and a ground rail. The first transistor device is biased into a partially on-state, and thus, neither device sees the full voltage potential between the power rail and the ground rail. Accordingly, the power clamp can function in voltage environments higher than the native voltage of the transistor devices. Additionally, the second transistor device is controlled by an RC network functioning as a trigger which allows the second transistor device to turn on during a voltage spike such as occurs during an ESD event. The capacitor of the RC network may be small thereby requiring small real estate on the integrated circuit. The clamp may have fast turn-on times as well as conducting current for long periods of time after turning on.
摘要翻译：为静电放电电源钳提供一种用于高压电源的结构和装置。功率钳包括晶体管器件网络，例如串联布置在电源轨和接地轨之间的nFET。第一晶体管器件被偏置成部分导通状态，因此，两个器件都不会看到电源轨和接地轨之间的全电压电位。因此，功率钳可以在高于晶体管器件的天然电压的电压环境中工作。此外，第二晶体管器件由用作触发器的RC网络控制，该RC网络允许第二晶体管器件在诸如在ESD事件期间发生的电压尖峰期间导通。 RC网络的电容器可能很小，从而在集成电路上需要小的空间。打开后，夹具可能会导通快速导通时间，并长时间传导电流。

43. 发明授权

US07005686B1 Mixed voltage tolerant electrostatic discharge protection silicon controlled rectifier with enhanced turn-on time 失效
标题翻译：混合耐压静电放电保护可控硅整流器，增加开启时间
公开(公告)号：US07005686B1
公开(公告)日：2006-02-28
申请号：US11161184
申请日：2005-07-26
申请人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Mujahid Muhammad , Andreas D. Stricker , Min Woo
发明人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Mujahid Muhammad , Andreas D. Stricker , Min Woo
IPC分类号： H01L29/66 , H01L21/33
CPC分类号： H01L27/0262 , H01L29/87
摘要： Disclosed is a method for increasing substrate resistance in a silicon controlled rectifier in order to decrease turn on time so that the silicon controlled rectifier may be used as an effective electrostatic discharge protection device to protect against HBM, MM and CDM discharge events. Additionally, disclosed is an improved SCR structure that is adapted for use as an electrostatic discharge device to protect against human body model events by delivering an electrostatic discharge current directly to a ground rail. The improved SCR structure incorporates various features for increasing substrate resistance and, thereby, for decreasing turn on time. These features include a second n-well that functions as an obstacle to current flow, a narrow current flow channel between co-planar buried n-bands connected to a lower portion of the second n-well, a zero threshold voltage area, and an external resistor electrically connected between the SCR and the ground rail.
摘要翻译：公开了一种用于增加可控硅整流器中的衬底电阻以减少导通时间的方法，使得可控硅整流器可以用作有效的静电放电保护装置，以防止HBM，MM和CDM放电事件。此外，公开了一种改进的SCR结构，其适于用作静电放电装置，以通过将静电放电电流直接递送到接地轨来防止人体模型事件。改进的SCR结构包含用于增加衬底电阻并因此减少导通时间的各种特征。这些特征包括作为电流流动的障碍的第二n阱，连接到第二n阱的下部的共平面埋入n波段之间的窄电流流动通道，零阈值电压区域和外部电阻电连接在SCR和接地导轨之间。

44. 发明授权

US06940130B2 Body contact MOSFET 失效
标题翻译：体接触MOSFET
公开(公告)号：US06940130B2
公开(公告)日：2005-09-06
申请号：US10687333
申请日：2003-10-16
申请人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
发明人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
IPC分类号： H01L21/336 , H01L29/786 , H01L27/01
CPC分类号： H01L29/66772 , H01L29/78615
摘要： A body contact structure utilizing an insulating structure between the body contact portion of the active area and the transistor portion of the active area is disclosed. In one embodiment, the present invention substitutes an insulator for at least a portion of the gate layer in the regions between the transistor and the body contact. In another embodiment, a portion of the gate layer is removed and replaced with an insulative layer in regions between the transistor and the body contact. In still another embodiment, the insulative structure is formed by forming multiple layers of gate dielectric between the gate and the body in regions between the transistor and the body contact. The body contact produced by these methods adds no significant gate capacitance to the gate.
摘要翻译：公开了一种在有源区的主体接触部分和有源区的晶体管部分之间利用绝缘结构的体接触结构。在一个实施例中，本发明将绝缘体替代晶体管和身体接触之间的区域中的栅极层的至少一部分。在另一个实施例中，栅极层的一部分被去除并且在晶体管和身体接触之间的区域中被绝缘层替代。在另一个实施例中，通过在晶体管和身体接触之间的区域中在栅极和主体之间形成多个栅极电介质层来形成绝缘结构。通过这些方法产生的身体接触对栅极没有增加显着的栅极电容。

45. 发明授权

US06677645B2 Body contact MOSFET 有权
标题翻译：体接触MOSFET
公开(公告)号：US06677645B2
公开(公告)日：2004-01-13
申请号：US10061263
申请日：2002-01-31
申请人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
发明人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L29/78615
摘要： A body contact structure utilizing an insulating structure between the body contact portion of the active area and the transistor portion of the active area is disclosed. In one embodiment, the present invention substitutes an insulator for at least a portion of the gate layer in the regions between the transistor and the body contact. In another embodiment, a portion of the gate layer is removed and replaced with an insulative layer in regions between the transistor and the body contact. In still another embodiment, the insulative structure is formed by forming multiple layers of gate dielectric between the gate and the body in regions between the transistor and the body contact. The body contact produced by these methods adds no significant gate capacitance to the gate.
摘要翻译：公开了一种在有源区的主体接触部分和有源区的晶体管部分之间利用绝缘结构的体接触结构。在一个实施例中，本发明将绝缘体替代晶体管和身体接触之间的区域中的栅极层的至少一部分。在另一个实施例中，栅极层的一部分被去除并且在晶体管和身体接触之间的区域中被绝缘层替代。在另一个实施例中，通过在晶体管和身体接触之间的区域中在栅极和主体之间形成多个栅极电介质层来形成绝缘结构。通过这些方法产生的身体接触对栅极没有增加显着的栅极电容。

46. 发明授权

US06646305B2 Grounded body SOI SRAM cell 有权
标题翻译：接地体SOI SRAM单元
公开(公告)号：US06646305B2
公开(公告)日：2003-11-11
申请号：US09915061
申请日：2001-07-25
申请人： Fariborz Assaderaghi , Andres Bryant , Peter E. Cottrell , Robert J. Gauthier, Jr. , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
发明人： Fariborz Assaderaghi , Andres Bryant , Peter E. Cottrell , Robert J. Gauthier, Jr. , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L2701
CPC分类号： H01L27/1203 , H01L27/1104
摘要： A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to VDD.
摘要翻译：一种半导体存储器件，包括：在衬底绝缘体的顶部上具有薄硅层的SOI衬底; 以及包括四个NFET和位于薄硅层中的两个PFET的SRAM，每个NFET和PFET具有在源极区域和漏极区域之间的主体区域，其中两个NFET的主体电连接到地。另外，两个PFET的主体电连接到VDD。

47. 发明授权

US07075153B2 Grounded body SOI SRAM cell 有权
标题翻译：接地体SOI SRAM单元
公开(公告)号：US07075153B2
公开(公告)日：2006-07-11
申请号：US10640807
申请日：2003-08-14
申请人： Fariborz Assaderaghi , Andres Bryant , Peter E. Cottrell , Robert J. Gauthier, Jr. , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
发明人： Fariborz Assaderaghi , Andres Bryant , Peter E. Cottrell , Robert J. Gauthier, Jr. , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L27/1203 , H01L27/1104
摘要： A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to VDD.
摘要翻译：一种半导体存储器件，包括：在衬底绝缘体的顶部上具有薄硅层的SOI衬底; 以及包括四个NFET和位于薄硅层中的两个PFET的SRAM，每个NFET和PFET具有在源极区域和漏极区域之间的主体区域，其中两个NFET的主体电连接到地。另外，两个PFET的主体电连接到V DD。

48. 发明授权

US06387742B2 Thermal conductivity enhanced semiconductor structures and fabrication processes 失效
标题翻译：热导率增强的半导体结构和制造工艺
公开(公告)号：US06387742B2
公开(公告)日：2002-05-14
申请号：US09862451
申请日：2001-05-23
申请人： Robert J. Gauthier, Jr. , Dominic J. Schepis , William R. Tonti , Steven H. Voldman
发明人： Robert J. Gauthier, Jr. , Dominic J. Schepis , William R. Tonti , Steven H. Voldman
IPC分类号： H01L21336
CPC分类号： H01L29/78648 , H01L21/76264 , H01L21/76286 , H01L21/763 , H01L23/3677 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Silicon is formed at selected locations on a substrate during fabrication of selected electronic components. A dielectric separation region is formed within the top silicon layer, and filled with a thermally conductive material. A liner material may be optionally deposited prior to depositing the thermally conductive material. In a second embodiment, a horizontal layer of thermally conductive material is also deposited in an oxide layer or bulk silicon layer below the top layer of silicon.
摘要翻译：在选择的电子部件的制造期间，在基板上的选定位置处形成硅。介电分离区形成在顶层硅层内，并填充有导热材料。衬里材料可以在沉积导热材料之前任选地沉积。在第二实施例中，水平导热材料层也沉积在硅顶层之下的氧化物层或体硅层中。

49. 发明授权

US06288426B1 Thermal conductivity enhanced semiconductor structures and fabrication processes 有权
标题翻译：热导率增强的半导体结构和制造工艺
公开(公告)号：US06288426B1
公开(公告)日：2001-09-11
申请号：US09514106
申请日：2000-02-28
申请人： Robert J. Gauthier, Jr. , Dominic J. Schepis , William R. Tonti , Steven H. Voldman
发明人： Robert J. Gauthier, Jr. , Dominic J. Schepis , William R. Tonti , Steven H. Voldman
IPC分类号： H01L2900
CPC分类号： H01L29/78648 , H01L21/76264 , H01L21/76286 , H01L21/763 , H01L23/3677 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Silicon is formed at selected locations on a substrate during fabrication of selected electronic components. A dielectric separation region is formed within the top silicon layer, and filled with a thermally conductive material. A liner material may be optionally deposited prior to depositing the thermally conductive material. In a second embodiment, a horizontal layer of thermally conductive material is also deposited in an oxide layer or bulk silicon layer below the top layer of silicon.
摘要翻译：在选择的电子部件的制造期间，在基板上的选定位置处形成硅。介电分离区形成在顶层硅层内，并填充有导热材料。衬里材料可以在沉积导热材料之前任选地沉积。在第二实施例中，水平导热材料层也沉积在硅顶层之下的氧化物层或体硅层中。

50. 发明授权

US06232163B1 Method of forming a semiconductor diode with depleted polysilicon gate structure 有权
标题翻译：形成具有耗尽的多晶硅栅结构的半导体二极管的方法
公开(公告)号：US06232163B1
公开(公告)日：2001-05-15
申请号：US09362549
申请日：1999-07-28
申请人： Steven H. Voldman , Robert J. Gauthier, Jr. , Jeffrey S. Brown
发明人： Steven H. Voldman , Robert J. Gauthier, Jr. , Jeffrey S. Brown
IPC分类号： H01L218238
CPC分类号： H01L27/0811 , H01L29/7391 , H01L2924/0002 , H01L2924/00
摘要： A high voltage tolerant diode structure for mixed-voltage, and mixed signal and analog/digital applications. The preferred silicon diode includes a polysilicon gate structure on at least one dielectric film layer on a semiconductor (silicon) layer or body. A well or an implanted area is formed in a bulk semiconductor substrate or in a surface silicon layer on an SOI wafer. Voltage applied to the polysilicon gate film, electrically depletes it, reducing voltage stress across the dielectric film. An intrinsic polysilicon film may be counter-doped, implanted with a low doped implantation, implanted with a low doped source/drain implant, or with a low doped MOSFET LDD or extension implant. Alternatively, a block mask may be formed over the gate structure when defining the depleted-polysilicon gate silicon diode to form low series resistance diode implants, preventing over-doping the film. Optionally, a hybrid photoresist method may be used to form higher doped edge implants in the silicon to reduce diode series resistance without a block mask.
摘要翻译：用于混合电压，混合信号和模拟/数字应用的高耐压二极管结构。优选的硅二极管包括在半导体（硅）层或主体上的至少一个电介质膜层上的多晶硅栅极结构。阱体或植入区域形成在SOI半导体衬底或SOI晶片的表面硅层中。施加到多晶硅栅极膜的电压，电耗电，降低电介质膜两端的电压。本征多晶硅膜可以是反掺杂的，注入低掺杂注入，注入低掺杂源/漏注入，或者与低掺杂的MOSFET LDD或延伸注入。或者，当限定耗尽多晶硅栅极硅二极管以形成低串联电阻二极管植入物时，可以在栅极结构上形成块掩模，防止膜过度掺杂。可选地，可以使用混合光致抗蚀剂方法在硅中形成更高掺杂的边缘注入，以减少二极管串联电阻而不使用块掩模。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式