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41. 发明授权

US06780782B1 Bi-level resist structure and fabrication method for contact holes on semiconductor substrates 有权
标题翻译：半导体衬底上的接触孔的双层抗蚀剂结构和制造方法
公开(公告)号：US06780782B1
公开(公告)日：2004-08-24
申请号：US10357579
申请日：2003-02-04
申请人： Ming-Huan Tsai , Hun-Jan Tao , Tsang Jiuh Wu , Ju Wang Hsu
发明人： Ming-Huan Tsai , Hun-Jan Tao , Tsang Jiuh Wu , Ju Wang Hsu
IPC分类号： H01L21302
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/31138 , H01L21/31144
摘要： An improved method of etching very small contact holes through dielectric layers used to separate conducting layers in multilevel integrated circuits formed on semiconductor substrates has been developed. The method uses bi-level ARC coatings in the resist structure and a unique combination of gaseous components in a plasma etching process which is used to dry develop the bi-level resist mask as well as etch through a silicon oxide dielectric layer. The gaseous components comprise a mixture of a fluorine containing gas, such as C4F8, C5F8, C4F6, CHF3 or similar species, an inert gas, such as helium or argon, an optional weak oxidant, such as CO or O2 or similar species, and a nitrogen source, such as N2, N2O, or NH3 or similar species. The patterned masking layer can be used to reliably etch contact holes in silicon oxide layers on semiconductor substrates, where the holes have diameters of about 0.1 micron or less.
摘要翻译：已经开发了一种通过介电层蚀刻非常小的接触孔的改进方法，其用于在半导体衬底上形成的多层集成电路中分离导电层。该方法在抗蚀剂结构中使用双层ARC涂层，并且在等离子体蚀刻工艺中使用气态组分的独特组合，其用于干燥显影双电平抗蚀剂掩模以及通过氧化硅介电层进行蚀刻。气态组分包括含氟气体如C 4 F 8，C 5 F 8，C 4 F 6，CHF 3或类似物质，惰性气体如氦气或氩气，任选的弱氧化剂如CO或O 2或类似物质的混合物，以及氮源，例如N 2，N 2 O或NH 3或类似物质。图案化掩模层可用于可靠地蚀刻半导体衬底上的氧化硅层中的接触孔，其中孔的直径为约0.1微米或更小。

42. 发明授权

US06777340B1 Method of etching a silicon containing layer using multilayer masks 有权
标题翻译：使用多层掩模蚀刻含硅层的方法
公开(公告)号：US06777340B1
公开(公告)日：2004-08-17
申请号：US09949505
申请日：2001-09-10
申请人： Hsien-Kuang Chiu , Fang-Chang Chen , Hun-Jan Tao , Yuan-Hung Chiu , Jeng-Horng Chen
发明人： Hsien-Kuang Chiu , Fang-Chang Chen , Hun-Jan Tao , Yuan-Hung Chiu , Jeng-Horng Chen
IPC分类号： H01L21302
CPC分类号： H01L21/3081 , H01L21/32139
摘要： A new method is provided for the etch of ultra-small patterns in a silicon based surface. Under the first embodiment, a hardmask layer over a substrate and a layer of ARC over the hardmask layer are successively patterned. The patterned layer of ARC is removed, the remaining patterned hardmask layer is used as a mask for etching the substrate. Under the second embodiment, a first hardmask layer over a substrate, a second hardmask layer over the first hardmask layer and a layer of ARC over the second hardmask layer are successively patterned. The patterned layer of ARC and the second hardmask layer are removed, the remaining first patterned hardmask layer is used as a mask for etching the substrate.
摘要翻译：提供了一种用于在硅基表面中蚀刻超小图案的新方法。在第一实施例中，在衬底上的硬掩模层和硬掩模层上的ARC层被连续地图案化。去除图案化的ARC层，剩余的图案化硬掩模层用作蚀刻衬底的掩模。在第二实施例中，基板上的第一硬掩模层，第一硬掩模层上的第二硬掩模层和第二硬掩模层上的ARC层被连续地图案化。去除ARC和第二硬掩模层的图案层，剩余的第一图案化硬掩模层用作蚀刻衬底的掩模。

43. 发明授权

US06524938B1 Method for gate formation with improved spacer profile control 有权
标题翻译：具有改进的间隔物轮廓控制的栅极形成方法
公开(公告)号：US06524938B1
公开(公告)日：2003-02-25
申请号：US10075842
申请日：2002-02-13
申请人： Hun-Jan Tao , Yuan-Hung Chiu
发明人： Hun-Jan Tao , Yuan-Hung Chiu
IPC分类号： H01L213205
CPC分类号： H01L29/6656 , H01L21/28247 , H01L21/31116 , H01L29/4983
摘要： A new process is provided for the creation of an improved gate spacer profile. A layer of hardmask material is patterned over the surface of a layer of gate material. The layer of gate material is etch in accordance with the patterned layer of hardmask material, reducing the thickness of the patterned layer of hardmask material. A liner oxide is formed, a film of gate spacer material is deposited over the liner material. The layer of spacer material is etched, forming gate spacers and at the same time the remaining layer of hardmask material.
摘要翻译：提供了一种新的工艺来创建改进的浇口间隔件。在栅极材料层的表面上形成一层硬掩模材料。栅极材料层根据硬掩模材料的图案化层进行蚀刻，从而减小硬掩模材料图案化层的厚度。形成衬垫氧化物，栅衬垫材料的膜沉积在衬垫材料上。蚀刻隔离层材料层，形成栅极间隔物，同时形成剩余的硬掩模材料层。

44. 发明授权

US06503848B1 Method of forming a smooth polysilicon surface using a soft etch to enlarge the photo lithography window 有权
标题翻译：使用软蚀刻形成光滑多晶硅表面以扩大光刻窗的方法
公开(公告)号：US06503848B1
公开(公告)日：2003-01-07
申请号：US09989804
申请日：2001-11-20
申请人： Bor-Wen Chan , Yuan-Hung Chiu , Huan-Just Lin , Hun-Jan Tao
发明人： Bor-Wen Chan , Yuan-Hung Chiu , Huan-Just Lin , Hun-Jan Tao
IPC分类号： H01L21469
CPC分类号： H01L21/32115 , H01L21/31055 , H01L21/3127 , H01L21/32137
摘要： A method is disclosed for smoothing the top surface of a layer of polysilicon which, as deposited, has a rough top surface due to the formation of polysilicon grains. A polymer, such as CxFyBrz, is deposited using chemical vapor deposition. The polymer layer has a thickness large enough so that the top surface of the polymer is at least a critical distance above the peaks of the grains on the top surface of the layer of polysilicon. The layer of polymer and part of the layer of polysilicon are then etched away using an etch back method which etches the polymer and polysilicon at the same etch rate. This results in a layer of polysilicon having a smooth top surface and the same thickness over the entire layer of polysilicon.
摘要翻译：公开了一种用于平滑多晶硅层的顶表面的方法，由于多晶硅颗粒的形成，沉积的多晶硅层具有粗糙的顶表面。使用化学气相沉积法沉积聚合物，如CxFyBrz。聚合物层的厚度足够大，使得聚合物的顶表面至少在多晶硅层顶表面上的晶粒峰值之上的临界距离。然后使用以相同蚀刻速率蚀刻聚合物和多晶硅的回蚀法蚀刻掉聚合物层和多晶硅层的一部分。这导致一层多晶硅在整个多晶硅层上具有平滑的顶表面和相同的厚度。

45. 发明授权

US06407002B1 Partial resist free approach in contact etch to improve W-filling 有权
标题翻译：接触蚀刻中的部分抗光蚀刻方法，以改善W填充
公开(公告)号：US06407002B1
公开(公告)日：2002-06-18
申请号：US09636583
申请日：2000-08-10
申请人： Li-Te Lin , Yuan-Hung Chiu , Ming-Huan Tsai , Hun-Jan Tao
发明人： Li-Te Lin , Yuan-Hung Chiu , Ming-Huan Tsai , Hun-Jan Tao
IPC分类号： H01L21302
CPC分类号： H01L21/31144 , H01L21/31138 , H01L21/76804 , H01L21/76829 , H01L21/76877
摘要： A method is provided for improving the tungsten, W-filling of hole openings in semiconductor substrates. This is accomplished by forming an opening—which can be used either as a contact or via hole—with a faceted entrance along with tapered side-walls. This combination of faceted entrance and tapered side-walls improves substantially the tungsten W-filling of contact/via holes in substrates without the formation of key-holes, thereby resulting in metal plugs of high electrical integrity and high reliability.
摘要翻译：提供了一种提高半导体衬底中的开孔的钨，W填充的方法。这可以通过形成开口来实现，该开口可以作为接触或通孔使用，与开口的入口以及锥形侧壁一起使用。面形入口和锥形侧壁的这种组合基本上改善了衬底中的接触/通孔的钨W填充，而没有形成键孔，从而导致高电气完整性和高可靠性的金属插头。

46. 发明授权

US06326296B1 Method of forming dual damascene structure with improved contact/via edge integrity 失效
标题翻译：形成双镶嵌结构的方法，具有改进的接触/通孔边缘完整性
公开(公告)号：US06326296B1
公开(公告)日：2001-12-04
申请号：US09108867
申请日：1998-07-01
申请人： Chia Shiung Tsai , Hun-Jan Tao
发明人： Chia Shiung Tsai , Hun-Jan Tao
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/31116 , H01L21/31144 , H01L21/3144 , H01L21/3145 , H01L21/3185 , H01L2221/1036
摘要： A new method of forming a dual damascene interconnect is disclosed for manufacturing semiconductor substrates. A contact/via hole is first formed in a first dielectric layer formed over a substructure of a substrate having devices formed therein and/or metal layers formed thereon. The contact/via hole is filled with a protective material prior to forming a second dielectric layer. Conductive line opening is formed in the second dielectric layer and over the contact/via hole having the protective material in it. The protective material protects the edge of the contact/via hole from damage due to the second etching of the conductive line opening. Thus, a dual damascene structure is disclosed wherein the integrity of the edge of the contact/via hole is preserved, avoiding any reliability problems in the semiconductor product.
摘要翻译：公开了一种形成双镶嵌互连的新方法，用于制造半导体衬底。接触/通孔首先形成在形成在其上形成有器件和/或其上形成金属层的衬底的子结构之上的第一电介质层中。在形成第二电介质层之前，接触/通孔填充有保护材料。导电线路开口形成在第二电介质层中并且在其中具有保护材料的接触/通孔之上。保护材料保护接触/通孔的边缘免受由于导电线开口的第二次蚀刻的损害。因此，公开了一种双镶嵌结构，其中保留了接触/通孔的边缘的完整性，避免了半导体产品中的任何可靠性问题。

47. 发明授权

US6040248A Chemistry for etching organic low-k materials 失效
标题翻译：化学蚀刻有机低k材料
公开(公告)号：US6040248A
公开(公告)日：2000-03-21
申请号：US104032
申请日：1998-06-24
申请人： Chao-Cheng Chen , Ming-Hsin Huang , Hun-Jan Tao , Chia-Shiung Tsai
发明人： Chao-Cheng Chen , Ming-Hsin Huang , Hun-Jan Tao , Chia-Shiung Tsai
IPC分类号： H01L21/311 , H01L21/768 , H01L21/302 , C23F1/02 , H01L21/461
CPC分类号： H01L21/31138 , H01L21/76802
摘要： A process for plasma etching of contact and via openings in low-k organic polymer dielectric layers is described which overcomes problems of sidewall bowing and hardmask pattern deterioration by etching the organic layer in a high density plasma etcher with a chlorine/inert gas plasma. By adding chlorine to the oxygen/inert gas plasma, the development of an angular aspect or faceting of the hardmask pattern edges by ion bombardment is abated. Essentially vertical sidewalls are obtained in the openings etched in the organic polymer layer while hardmask pattern integrity is maintained. The addition of a passivating agent such as nitrogen, BCl.sub.3, or CHF.sub.3 to the etchant gas mixture further improves the sidewall profile by reducing bowing through protective polymer formation.
摘要翻译：描述了一种用于等离子体蚀刻低k有机聚合物介电层中的接触和通孔开口的方法，其通过用氯/惰性气体等离子体在高密度等离子体蚀刻机中蚀刻有机层来克服侧壁弯曲和硬掩模图案劣化的问题。通过向氧/惰性气体等离子体中加入氯，减少了通过离子轰击形成硬掩模图案边缘的角度方面或刻面。在保持硬掩模图案完整性的同时，在有机聚合物层中蚀刻的开口中获得基本垂直的侧壁。钝化剂如氮气，BCl3或CHF3添加到蚀刻剂气体混合物中，通过减少通过保护性聚合物形成的弯曲来进一步改善侧壁轮廓。

48. 发明授权

US5694207A Etch rate monitoring by optical emission spectroscopy 失效
标题翻译：通过光发射光谱法进行蚀刻速率监测
公开(公告)号：US5694207A
公开(公告)日：1997-12-02
申请号：US762076
申请日：1996-12-09
申请人： Shu Chi Hung , Hun-Jan Tao
发明人： Shu Chi Hung , Hun-Jan Tao
IPC分类号： G01N21/73 , H01L21/3065 , G01N21/62
CPC分类号： H01L21/3065 , G01N21/73
摘要： The etch rate in a plasma etching system has been monitored in-situ by using optical emission spectroscopy to measure the intensities of two or more peaks in the radiation spectrum and then using the ratio of two such peaks as a direct measure of etch rate. Examples of such peaks occur at 338.5 and 443.7 nm and at 440.6 and 437.6 nm for the fluoride/SOG system. Alternately, the intensities of at least four such peaks may be measured and the product of two ratios may be used. Examples of peaks used in this manner occurred at 440.5, 497.2 and 502.3 nm, also for the fluoride/SOG system. The method is believed to be general and not limited to fluoride/SOG.
摘要翻译：已经通过使用光发射光谱法原位监测等离子体蚀刻系统中的蚀刻速率，以测量辐射光谱中两个或更多个峰的强度，然后使用两个这样的峰的比例作为蚀刻速率的直接测量。对于氟化物/ SOG体系，这些峰的实例在338.5和443.7nm以及440.6和437.6nm处发生。或者，可以测量至少四个这样的峰的强度，并且可以使用两个比率的乘积。以这种方式使用的峰的实例发生在440.5,497.2和502.3nm，也用于氟化物/ SOG体系。该方法被认为是通用的，不限于氟化物/ SOG。

49. 发明授权

US08372755B2 Multilayer hard mask 有权
标题翻译：多层硬掩模
公开(公告)号：US08372755B2
公开(公告)日：2013-02-12
申请号：US12686866
申请日：2010-01-13
申请人： Shiang-Bau Wang , Hun-Jan Tao
发明人： Shiang-Bau Wang , Hun-Jan Tao
IPC分类号： H01L21/302 , H01L29/66
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating a semiconductor device is disclosed. In an embodiment, the method may include providing a semiconductor substrate; forming gate material layers over the semiconductor substrate; forming a multi-layer hard mask layer over the gate material layers, wherein the multi-layer hard mask layer includes a plurality of film stacks, each film stack having a silicon oxide layer and a carbon-containing material layer, each film stack having a thickness equal to or less than about 10 angstrom; patterning the multi-layer hard mask layer, forming an opening of the multi-hard mask layer; etching the gate material layers within the opening of the multi-layer hard mask layer, forming a gate structure; performing a tilt-angle ion implantation process to the semiconductor substrate, wherein a first remaining thickness of the multi-layer hard mask layer is less than a first thickness; and thereafter performing an epitaxy growth to the semiconductor substrate, wherein a second remaining thickness of the multi-layer hard mask layer is greater than a second thickness.
摘要翻译：公开了一种制造半导体器件的方法。在一个实施例中，该方法可以包括提供半导体衬底; 在所述半导体衬底上形成栅极材料层; 在所述栅极材料层上形成多层硬掩模层，其中所述多层硬掩模层包括多个膜堆叠，每个膜堆叠具有氧化硅层和含碳材料层，每个膜堆叠具有厚度等于或小于约10埃; 图案化多层硬掩模层，形成多硬掩模层的开口; 蚀刻多层硬掩模层的开口内的栅极材料层，形成栅极结构; 对所述半导体衬底进行倾斜角度离子注入工艺，其中所述多层硬掩模层的第一剩余厚度小于第一厚度; 然后对所述半导体衬底进行外延生长，其中所述多层硬掩模层的第二剩余厚度大于第二厚度。

50. 发明授权

US07875547B2 Contact hole structures and contact structures and fabrication methods thereof 有权
标题翻译：接触孔结构及接触结构及其制造方法
公开(公告)号：US07875547B2
公开(公告)日：2011-01-25
申请号：US11035325
申请日：2005-01-12
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Peng-Fu Hsu , Hun-Jan Tao
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Peng-Fu Hsu , Hun-Jan Tao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76835
摘要： Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without substantially damaging the substrate. In addition, a conductive layer is formed in the contact hole so as to form a contact structure.
摘要翻译：公开了形成接触孔结构的方法和结构。这些方法首先在衬底上形成基本上无硅的材料层。在基本无硅材料层上形成材料层。在基本无硅的材料层和材料层内形成接触孔，而基本上不损坏衬底。此外，在接触孔中形成导电层以形成接触结构。

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