专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20130234151A1 NITRIDE SEMICONDUCTOR ELEMENT AND NITRIDE SEMICONDUCTOR WAFER 有权
标题翻译：氮化物半导体元件和氮化物半导体晶体管
公开(公告)号：US20130234151A1
公开(公告)日：2013-09-12
申请号：US13602868
申请日：2012-09-04
申请人： Toshiki HIKOSAKA , Yoshiyuki Harada , Hisashi Yoshida , Naoharu Sugiyama , Shinya Nunoue
发明人： Toshiki HIKOSAKA , Yoshiyuki Harada , Hisashi Yoshida , Naoharu Sugiyama , Shinya Nunoue
IPC分类号： H01L29/20
CPC分类号： H01L29/205 , B82Y20/00 , H01L21/02458 , H01L21/02505 , H01L21/0254 , H01L29/2003 , H01L29/365 , H01L29/7783 , H01L33/06 , H01L33/12 , H01L33/32
摘要： According to one embodiment, a nitride semiconductor element includes a foundation layer, a functional layer and a stacked body. The stacked body is provided between the foundation layer and the functional layer. The stacked body includes a first stacked intermediate layer including a first GaN intermediate layer, a first high Al composition layer of Alx1Ga1-x1N (0
摘要翻译：根据一个实施例，氮化物半导体元件包括基底层，功能层和层叠体。层叠体设置在基础层和功能层之间。层叠体包括第一层叠中间层，其包括第一GaN中间层，Al x Ga 1-x N 1的第一高Al组成层（0

42. 发明申请

US20140084296A1 NITRIDE SEMICONDUCTOR WAFER, NITRIDE SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR WAFER 有权
标题翻译：氮化物半导体器件，氮化物半导体器件和制造氮化物半导体器件的方法
公开(公告)号：US20140084296A1
公开(公告)日：2014-03-27
申请号：US13729713
申请日：2012-12-28
申请人： Hisashi YOSHIDA , Toshiki Hikosaka , Yoshiyuki Harada , Naoharu Sugiyama , Shinya Nunoue
发明人： Hisashi YOSHIDA , Toshiki Hikosaka , Yoshiyuki Harada , Naoharu Sugiyama , Shinya Nunoue
IPC分类号： H01L29/20 , H01L21/02
CPC分类号： H01L29/2003 , H01L21/02104 , H01L21/02381 , H01L21/02458 , H01L21/02505 , H01L21/0254 , H01L21/0262 , H01L29/0649 , H01L29/7786 , H01L33/007 , H01L33/12
摘要： A nitride semiconductor wafer includes a silicon substrate, a stacked multilayer unit, a silicon-containing unit, and an upper layer unit. The silicon substrate has a major surface. The stacked multilayer unit is provided on the major surface. The stacked multilayer unit includes N number of buffer layers. The buffer layers include an i-th buffer layer, and an (i+1)-th buffer layer provided on the i-th buffer layer. The i-th buffer layer has an i-th lattice length Wi in a first direction parallel to the major surface. The (i+1)-th buffer layer has an (i+1)-th lattice length W(i+1) in the first direction. A relation that (W(i+1)−Wi)/Wi≦0.008 is satisfied for all the buffer layers. The silicon-containing unit is provided on the stacked multilayer unit. The upper layer unit is provided on the silicon-containing unit.
摘要翻译：氮化物半导体晶片包括硅衬底，堆叠多层单元，含硅单元和上层单元。硅衬底具有主表面。堆叠的多层单元设置在主表面上。堆叠的多层单元包括N个缓冲层。缓冲层包括第i个缓冲层和设置在第i个缓冲层上的第（i + 1）个缓冲层。第i个缓冲层在平行于主表面的第一方向上具有第i个晶格长度Wi。第（i + 1）个缓冲层在第一方向具有第（i + 1）个格子长度W（i + 1）。对于所有缓冲层，满足（W（i + 1）-Wi）/ Wi＆nlE; 0.008的关系。含硅单元设置在堆叠的多层单元上。上层单元设置在含硅单元上。

43. 发明申请

US20130328075A1 SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体发光器件及其制造方法
公开(公告)号：US20130328075A1
公开(公告)日：2013-12-12
申请号：US13727147
申请日：2012-12-26
申请人： Jumpei Tajima , Kotaro Zaima , Hiroshi Ono , Shinji Yamada , Shigeya Kimura , Naoharu Sugiyama , Shinya Nunoue
发明人： Jumpei Tajima , Kotaro Zaima , Hiroshi Ono , Shinji Yamada , Shigeya Kimura , Naoharu Sugiyama , Shinya Nunoue
IPC分类号： H01L33/22
CPC分类号： H01L33/22 , H01L33/0079 , H01L33/382 , H01L33/385 , H01L33/405
摘要： According to one embodiment, a semiconductor light emitting device includes first and second electrodes, first and second semiconductor layers and a light emitting layer. The first electrode includes a first region, a second region, and a third region provided between them. The first semiconductor layer includes a first portion on the first region and a second portion on the second region. The light emitting layer includes a third portion on the first portion and a fourth portion on the second portion. The second semiconductor layer includes a fifth portion on the third portion and a sixth portion on the fourth portion. The insulating layer is provided between the first and second portions on the third region and between the third and fourth portions. The second electrode includes a seventh portion provided on the insulating layer, eighth and ninth portions contacting side surfaces of the fifth and sixth portions.
摘要翻译：根据一个实施例，半导体发光器件包括第一和第二电极，第一和第二半导体层以及发光层。第一电极包括第一区域，第二区域和设置在它们之间的第三区域。第一半导体层包括第一区域上的第一部分和第二区域上的第二部分。发光层包括第一部分上的第三部分和第二部分上的第四部分。第二半导体层包括第三部分上的第五部分和第四部分上的第六部分。绝缘层设置在第三区域上的第一和第二部分之间以及第三和第四部分之间。第二电极包括设置在绝缘层上的第七部分，与第五和第六部分的侧表面接触的第八和第九部分。

44. 发明申请

US20060281234A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060281234A1
公开(公告)日：2006-12-14
申请号：US11449687
申请日：2006-06-09
申请人： Naoharu Sugiyama , Norio Hirashita , Tsutomu Tezuka
发明人： Naoharu Sugiyama , Norio Hirashita , Tsutomu Tezuka
IPC分类号： H01L21/84
CPC分类号： H01L29/78687 , H01L29/045
摘要： A method of manufacturing a semiconductor device. In the method, a substrate is prepared, which includes a buried oxide film and a SiGe layer formed on the buried oxide film. Then, heat treatment is performed on the substrate at a temperature equal to or lower than a first temperature, to form a protective oxide film on a surface of the SiGe layer. Next, the substrate having the protective oxide film is heated in a non-oxidizing atmosphere to a second temperature higher than the first temperature. Further, heat treatment is performed on the substrate thus heated, in an oxidizing atmosphere at a temperature equal to or higher than the second temperature, to form oxide the SiGe layer, make the SiGe layer thinner and increasing Ge concentration in the SiGe layer, thus forming a SiGe layer having the increased Ge concentration.
摘要翻译：一种制造半导体器件的方法。在该方法中，制备了包括掩埋氧化物膜和形成在掩埋氧化膜上的SiGe层的衬底。然后，在等于或低于第一温度的温度下在基板上进行热处理，以在SiGe层的表面上形成保护氧化膜。接着，将具有保护氧化膜的基板在非氧化性气氛中加热至高于第一温度的第二温度。此外，在等于或高于第二温度的氧化气氛中对如此加热的基板进行热处理，以氧化SiGe层，使SiGe层更薄并增加SiGe层中的Ge浓度，从而形成具有增加的Ge浓度的SiGe层。

45. 发明授权

US06369438B1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06369438B1
公开(公告)日：2002-04-09
申请号：US09468923
申请日：1999-12-22
申请人： Naoharu Sugiyama , Atsushi Kurobe
发明人： Naoharu Sugiyama , Atsushi Kurobe
IPC分类号： H01L31117
CPC分类号： H01L21/7624 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L29/1054 , H01L29/157 , H01L29/7842 , H01L31/028
摘要： A method of manufacturing a semiconductor device comprising the steps of forming a first crystal silicon layer doped with oxygen on a single crystal silicon substrate, forming a crystal silicon-germanium layer on the first crystal silicon layer, forming a second crystal silicon layer on the crystal silicon-germanium layer, and imparting strain to the second crystal silicon layer by a thermal treatment.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在单晶硅衬底上形成掺杂有氧的第一晶体硅层，在第一晶体硅层上形成晶体硅 - 锗层，在晶体上形成第二晶体硅层硅锗层，并通过热处理赋予第二晶体硅层的应变。

46. 发明授权

US6060743A Semiconductor memory device having multilayer group IV nanocrystal quantum dot floating gate and method of manufacturing the same 失效
标题翻译：具有多层IV族纳米晶体量子点浮栅的半导体存储器件及其制造方法
公开(公告)号：US6060743A
公开(公告)日：2000-05-09
申请号：US82613
申请日：1998-05-20
申请人： Naoharu Sugiyama , Tsutomu Tezuka , Riichi Katoh , Atsushi Kurobe , Tetsufumi Tanamoto
发明人： Naoharu Sugiyama , Tsutomu Tezuka , Riichi Katoh , Atsushi Kurobe , Tetsufumi Tanamoto
IPC分类号： H01L29/788 , H01L21/336 , H01L29/06 , H01L29/15
CPC分类号： B82Y10/00 , H01L29/7883 , H01L29/7888 , Y10S438/962
摘要： The semiconductor device comprises a first insulating layer formed on the semiconductor substrate, at least one double-deck semiconductor nanocrystal formed on the first insulating layer, the at least one double-deck semiconductor nanocrystal comprising a first semiconductor nanocrystal and a second semiconductor nanocrystal stacked one upon the other via a second insulating layer, and a third insulating layer selectively formed on the first insulating layer so as to cover the at least one double-deck semiconductor nanocrystal.
摘要翻译：所述半导体器件包括形成在所述半导体衬底上的第一绝缘层，形成在所述第一绝缘层上的至少一个双层半导体纳米晶体，所述至少一个双层半导体纳米晶体包括第一半导体纳米晶体和第二半导体纳米晶体，另一方面通过第二绝缘层，以及选择性地形成在第一绝缘层上以覆盖至少一个双层半导体纳米晶体的第三绝缘层。

47. 发明授权

US08174095B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08174095B2
公开(公告)日：2012-05-08
申请号：US13037049
申请日：2011-02-28
申请人： Toshifumi Irisawa , Shinichi Takagi , Naoharu Sugiyama
发明人： Toshifumi Irisawa , Shinichi Takagi , Naoharu Sugiyama
IPC分类号： H01L29/04
CPC分类号： H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/1054 , H01L29/42392 , H01L29/7842 , H01L29/785 , H01L29/78684
摘要： A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a direction.
摘要翻译：半导体器件包括绝缘体层和具有n沟道的n沟道MIS晶体管和具有ap沟道的pMIS晶体管，其形成在绝缘体层上，其中n沟道MIS晶体管的n沟道由Si 层在通道长度方向上具有单轴拉伸应变，p沟道MIS晶体管的p沟道由沟道长度方向上具有单轴压缩应变的SiGe或Ge层形成，并且沟道长度方向 n沟道MIS晶体管和p沟道MIS晶体管是<110>方向。

48. 发明授权

US07759228B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07759228B2
公开(公告)日：2010-07-20
申请号：US11449687
申请日：2006-06-09
申请人： Naoharu Sugiyama , Norio Hirashita , Tsutomu Tezuka
发明人： Naoharu Sugiyama , Norio Hirashita , Tsutomu Tezuka
IPC分类号： H01L21/84 , H01L21/324 , H01L21/20
CPC分类号： H01L29/78687 , H01L29/045
摘要： A method of manufacturing a semiconductor device. In the method, a substrate is prepared, which includes a buried oxide film and a SiGe layer formed on the buried oxide film. Then, heat treatment is performed on the substrate at a temperature equal to or lower than a first temperature, to form a protective oxide film on a surface of the SiGe layer. Next, the substrate having the protective oxide film is heated in a non-oxidizing atmosphere to a second temperature higher than the first temperature. Further, heat treatment is performed on the substrate thus heated, in an oxidizing atmosphere at a temperature equal to or higher than the second temperature, to form oxide the SiGe layer, make the SiGe layer thinner and increasing Ge concentration in the SiGe layer, thus forming a SiGe layer having the increased Ge concentration.
摘要翻译：一种制造半导体器件的方法。在该方法中，制备了包括掩埋氧化物膜和形成在掩埋氧化膜上的SiGe层的衬底。然后，在等于或低于第一温度的温度下在基板上进行热处理，以在SiGe层的表面上形成保护氧化膜。接着，将具有保护氧化膜的基板在非氧化性气氛中加热至高于第一温度的第二温度。此外，在等于或高于第二温度的氧化气氛中对如此加热的基板进行热处理，以氧化SiGe层，使SiGe层更薄并增加SiGe层中的Ge浓度，从而形成具有增加的Ge浓度的SiGe层。

49. 发明授权

US07619239B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07619239B2
公开(公告)日：2009-11-17
申请号：US11437730
申请日：2006-05-22
申请人： Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka , Naoharu Sugiyama , Shinichi Takagi
发明人： Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka , Naoharu Sugiyama , Shinichi Takagi
IPC分类号： H01L29/06
CPC分类号： H01L29/785 , H01L21/84 , H01L29/78687
摘要： A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.
摘要翻译：半导体器件包括形成在绝缘层上的半导体层上的n沟道MIS晶体管和p沟道MIS晶体管，其中n沟道MIS晶体管的沟道由具有双轴拉伸应变的应变Si层形成， p沟道MIS晶体管的沟道由在沟道长度方向上具有单轴压缩应变的应变SiGe层形成。

50. 发明申请

US20060266996A1 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US20060266996A1
公开(公告)日：2006-11-30
申请号：US11437730
申请日：2006-05-22
申请人： Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka , Naoharu Sugiyama , Shinichi Takagi
发明人： Toshifumi Irisawa , Toshinori Numata , Tsutomu Tezuka , Naoharu Sugiyama , Shinichi Takagi
IPC分类号： H01L31/00
CPC分类号： H01L29/785 , H01L21/84 , H01L29/78687
摘要： A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式