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41. 发明授权

US07485516B2 Method of ion implantation of nitrogen into semiconductor substrate prior to oxidation for offset spacer formation 失效
标题翻译：在氧化之前将氮离子注入到半导体衬底中用于偏移间隔物形成的方法
公开(公告)号：US07485516B2
公开(公告)日：2009-02-03
申请号：US11164376
申请日：2005-11-21
申请人： Thomas W. Dyer , Jinhong Li , Zhijiong Luo
发明人： Thomas W. Dyer , Jinhong Li , Zhijiong Luo
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/28247
摘要： A method of formation of integrated circuit devices includes forming a gate electrode stack over a portion of a semiconductor. The stack includes a gate dielectric layer with a gate electrode thereabove. Implant diatomic nitrogen and/or nitrogen atoms into the substrate aside from the stack at a maximum energy less than or equal to 10 keV for diatomic nitrogen and at a maximum energy less than or equal to 5 keV for atomic nitrogen at a temperature less than or equal to 1000° C. for a time of less than or equal to 30 minutes. Then form silicon oxide offset spacers on sidewalls of the stack. Form source/drain extension regions in the substrate aside from the offset spacers. Form nitride sidewall spacers on outer surfaces of the offset spacers over another portion of the nitrogen implanted layer. Then form source/drain regions in the substrate aside from the sidewall spacers.
摘要翻译：形成集成电路器件的方法包括在半导体的一部分上形成栅电极堆叠。堆叠包括其上方具有栅电极的栅介质层。将双原子氮和/或氮原子从堆叠中以最低能量小于或等于10keV的双原子氮并且在小于或等于5keV的最大能量下，在低于或等于等于1000℃，时间小于或等于30分钟。然后在堆叠的侧壁上形成氧化硅偏移间隔物。在偏移间隔物之外的衬底中形成源极/漏极延伸区域。在氮注入层的另一部分上的偏移间隔物的外表面上形成氮化物侧壁间隔物。然后在侧壁间隔物之外形成衬底中的源极/漏极区域。

42. 发明申请

US20090017625A1 Methods For Removing Gate Sidewall Spacers In CMOS Semiconductor Fabrication Processes 有权
标题翻译： CMOS半导体制造工艺中去除栅极侧壁间隔物的方法
公开(公告)号：US20090017625A1
公开(公告)日：2009-01-15
申请号：US11778038
申请日：2007-07-14
申请人： Kyoung Woo Lee , Ja Hum Ku , JunJung Kim , Chong Kwang Chang , Min-Chul Sun , Jong Ho Yang , Thomas W. Dyer
发明人： Kyoung Woo Lee , Ja Hum Ku , JunJung Kim , Chong Kwang Chang , Min-Chul Sun , Jong Ho Yang , Thomas W. Dyer
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/823814 , H01L21/823835 , H01L21/823864
摘要： Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.
摘要翻译：提供半导体制造工艺用于从门结构去除侧壁间隔物，同时减轻或以其他方式预防诸如损坏金属硅化物结构的缺陷机制或以其它方式阻碍或限制后续工艺流程。

43. 发明授权

US07456450B2 CMOS devices with hybrid channel orientations and method for fabricating the same 有权
标题翻译：具有混合信道取向的CMOS器件及其制造方法
公开(公告)号：US07456450B2
公开(公告)日：2008-11-25
申请号：US11307481
申请日：2006-02-09
申请人： Thomas W. Dyer , Xiangdong Chen , James J. Toomey , Haining S. Yang
发明人： Thomas W. Dyer , Xiangdong Chen , James J. Toomey , Haining S. Yang
IPC分类号： H01L29/04
CPC分类号： H01L21/823807 , H01L21/82385 , H01L21/823857
摘要： The present invention relates to a semiconductor substrate comprising at least first and second device regions, wherein the first device region comprises a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and wherein the second device region comprises a second recess having interior surfaces oriented along a second, different set of equivalent crystal planes. A semiconductor device structure can be formed using such a semiconductor substrate. Specifically, at least one n-channel field effect transistor (n-FET) can be formed at the first device region, which comprises a channel that extends along the interior surfaces of the first recess. At least one p-channel field effect transistor (p-FET) can be formed at the second device region, which comprises a channel that extends along the interior surfaces of the second recess.
摘要翻译：本发明涉及包括至少第一和第二器件区域的半导体衬底，其中第一器件区域包括具有沿着第一组等效晶面取向的内表面的第一凹槽，并且其中第二器件区域包括第二凹部，沿着第二不同组的等效晶面取向的内表面。可以使用这种半导体衬底形成半导体器件结构。具体而言，可以在第一器件区域形成至少一个n沟道场效应晶体管（n-FET），该第一器件区域包括沿着第一凹槽的内表面延伸的沟道。至少一个p沟道场效应晶体管（p-FET）可以在第二器件区域形成，该第二器件区域包括沿着第二凹槽的内表面延伸的沟道。

44. 发明申请

US20080246056A1 SILICIDE FORMATION FOR eSiGe USING SPACER OVERLAPPING eSiGe AND SILICON CHANNEL INTERFACE AND RELATED PFET 审中-公开
标题翻译：使用间隔层叠层的硅化物形成和硅氧烷沟道界面及相关PFET
公开(公告)号：US20080246056A1
公开(公告)日：2008-10-09
申请号：US11697806
申请日：2007-04-09
申请人： Victor W. C. Chan , Thomas W. Dyer , Sunfei Fang , Jinghong Li , Teck J. Tang , Henry K. Utomo , Jiang Yan
发明人： Victor W. C. Chan , Thomas W. Dyer , Sunfei Fang , Jinghong Li , Teck J. Tang , Henry K. Utomo , Jiang Yan
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823864 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/665 , H01L29/6653 , H01L29/66636 , H01L29/7843
摘要： Methods of forming a suicide in an embedded silicon germanium (eSiGe) source/drain region using a suicide prevention spacer overlapping an interface between the eSiGe and the silicon channel, and a related PFET with an eSiGe source/drain region and a compressive stress liner in close proximity to a silicon channel thereof, are disclosed. In one embodiment, a method includes providing a gate having a nitrogen-containing spacer adjacent thereto and an epitaxially grown silicon germanium (eSiGe) region adjacent to a silicon channel of the gate; removing the nitrogen-containing spacer that does not extend over the interface between the eSiGe source/drain region and the silicon channel; forming a single silicide prevention spacer about the gate, the single silicide prevention spacer overlapping the interface; and forming the silicide in the eSiGe source/drain region using the single silicide prevention spacer to prevent the silicide from forming in at least an extension area of the silicon channel.
摘要翻译：在嵌入式硅锗（eSiGe）源极/漏极区域中使用与eSiGe和硅沟道之间的界面重叠的防止硅化物的衬垫形成硅化物的方法以及具有eSiGe源极/漏极区域和压应力衬垫的相关PFET 公开了其接近硅通道的方式。在一个实施例中，一种方法包括提供具有与其相邻的含氮隔离物的栅极和与栅极的硅沟道相邻的外延生长的硅锗（eSiGe）区域; 去除不在eSiGe源极/漏极区域和硅沟道之间的界面上延伸的含氮隔离物; 在栅极周围形成单个硅化物防止间隔物，单个硅化物防止间隔物与界面重叠; 以及使用单个硅化物防止间隔物在eSiGe源极/漏极区域中形成硅化物，以防止硅化物在硅沟道的至少延伸区域中形成。

45. 发明授权

US07390745B2 Pattern enhancement by crystallographic etching 有权
标题翻译：通过晶体蚀刻的图案增强
公开(公告)号：US07390745B2
公开(公告)日：2008-06-24
申请号：US11162800
申请日：2005-09-23
申请人： Thomas W. Dyer , Kenneth T. Settlemyer, Jr. , James J. Toomey , Haining Yang
发明人： Thomas W. Dyer , Kenneth T. Settlemyer, Jr. , James J. Toomey , Haining Yang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/30608 , H01L21/32134
摘要： A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.
摘要翻译：与使用本发明的方法形成的结构一起设置在具有基本均匀的直边或边缘以及良好限定的内角和外角的含Si结晶材料中产生预定形状的方法。本发明的方法利用常规的光刻和蚀刻将图案（即形状）转移到含结晶的含Si材料。由于使用了常规处理，所以图案具有圆角的固有限制。使用利用稀释氢氧化铵溶液的选择性蚀刻方法来消除圆角，提供具有基本上直的边或边缘和基本上圆角的最终形状。

46. 发明申请

US20080048297A1 EMBEDDED INTERCONNECTS, AND METHODS FOR FORMING SAME 有权
标题翻译：嵌入式互连及其形成方法
公开(公告)号：US20080048297A1
公开(公告)日：2008-02-28
申请号：US11467712
申请日：2006-08-28
申请人： Haining Yang , Thomas W. Dyer
发明人： Haining Yang , Thomas W. Dyer
IPC分类号： H01L27/082
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive interconnect structure that is embedded in the isolation region and connects the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first conductive interconnect structure cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof. The conductive interconnect preferably comprises doped polysilicon and can be formed by processing steps including photolithographic patterning, etching, and polysilicon deposition.
摘要翻译：本发明涉及一种半导体器件，其包括第一和第二有源器件区域，其位于半导体衬底中并且通过其间的隔离区彼此隔离，而半导体器件包括嵌入在隔离中的第一导电互连结构并且将第一有源器件区域与第二有源器件区域连接。半导体器件优选地包含位于半导体衬底中的至少一个静态随机存取存储器（SRAM）单元，并且第一导电互连结构将SRAM单元的下拉晶体管与其上拉晶体管交叉连接。导电互连优选地包括掺杂多晶硅，并且可以通过包括光刻图案，蚀刻和多晶硅沉积的处理步骤形成。

47. 发明授权

US07023041B2 Trench capacitor vertical structure 有权
标题翻译：沟槽电容器垂直结构
公开(公告)号：US07023041B2
公开(公告)日：2006-04-04
申请号：US10341187
申请日：2003-01-13
申请人： Giuseppe La Rosa , Thomas W. Dyer , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens , Alvin W. Strong
发明人： Giuseppe La Rosa , Thomas W. Dyer , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens , Alvin W. Strong
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L29/945 , H01L27/10861 , H01L27/10894 , H01L29/66181
摘要： A versatile structure is formed, based on a deep trench, vertical transistor DRAM cell, that forms a conductive extension of the trench electrode in an elongated trench that contacts the lower electrode of the vertical transistor. The structure can be used as a capacitor, as a discrete transistor as a single-transistor amplifier or as a building block for more complex circuits.
摘要翻译：基于深沟槽垂直晶体管DRAM单元形成通用结构，其在与垂直晶体管的下电极接触的细长沟槽中形成沟槽电极的导电延伸。该结构可以用作电容器，作为单晶体管放大器的分立晶体管或作为更复杂电路的构建块。

48. 发明授权

US08853746B2 CMOS devices with stressed channel regions, and methods for fabricating the same 有权
标题翻译：具有应力沟道区的CMOS器件及其制造方法
公开(公告)号：US08853746B2
公开(公告)日：2014-10-07
申请号：US11427495
申请日：2006-06-29
申请人： Xiangdong Chen , Thomas W. Dyer , Kenneth Settlemyer , Haining S. Yang
发明人： Xiangdong Chen , Thomas W. Dyer , Kenneth Settlemyer , Haining S. Yang
IPC分类号： H01L29/76 , H01L27/148 , H01L29/66 , H01L29/165 , H01L29/786 , H01L29/78 , H01L27/12 , H01L21/84 , H01L29/04 , H01L29/10 , H01L21/762 , H01L21/8238
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/30604 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/045 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/78 , H01L29/78684 , H01L29/78696
摘要： The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.
摘要翻译：本发明涉及具有应力通道区域的改进的互补金属氧化物半导体（CMOS）器件。具体地，每个改进的CMOS器件包括具有位于半导体器件结构中的沟道区的场效应晶体管（FET），其具有沿着第一组等效晶面中的一个取向的顶表面和沿着第二，不同组的等效晶面。这种附加表面可以通过晶体蚀刻容易地形成。此外，具有固有压缩或拉伸应力的一个或多个应力层位于半导体器件结构的附加表面上，并且被布置和构造成将拉应力或压应力施加到FET的沟道区。这种应力层可以通过具有与半导体器件结构不同的晶格常数的半导体材料的假晶生长来形成。

49. 发明授权

US08765602B2 Doping of copper wiring structures in back end of line processing 有权
标题翻译：在线路处理后端掺杂铜线结构
公开(公告)号：US08765602B2
公开(公告)日：2014-07-01
申请号：US13599256
申请日：2012-08-30
申请人： Thomas W. Dyer , Daniel C. Edelstein , Tze-man Ko , Andrew H. Simon , Wei-tsu Tseng
发明人： Thomas W. Dyer , Daniel C. Edelstein , Tze-man Ko , Andrew H. Simon , Wei-tsu Tseng
IPC分类号： H01L23/52
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76846 , H01L21/76849 , H01L21/76867 , H01L21/76873 , H01L21/76886 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.
摘要翻译：形成金属互连结构的方法包括在层间电介质（ILD）层内形成铜线; 用铜合金材料直接掺杂铜线的顶面; 并在ILD层和铜合金材料上形成介电层; 其中所述铜合金材料用于所述铜线和所述电介质层之间的粘合界面层。

50. 发明申请

US20110237039A1 Methods of Forming P-Channel Field Effect Transistors Having SiGe Source/Drain Regions 有权
标题翻译：形成具有SiGe源极/漏极区域的P沟道场效应晶体管的方法
公开(公告)号：US20110237039A1
公开(公告)日：2011-09-29
申请号：US12729486
申请日：2010-03-23
申请人： Jong-Ho Yang , Hyung-rae Lee , Jin-Ping Han , Chung Woh Lai , Henry K. Utomo , Thomas W. Dyer
发明人： Jong-Ho Yang , Hyung-rae Lee , Jin-Ping Han , Chung Woh Lai , Henry K. Utomo , Thomas W. Dyer
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer is then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.
摘要翻译：形成p沟道MOSFET的方法使用在制造过程中相对较早执行的光晕注入步骤。这些方法包括在半导体衬底上形成其上具有第一侧壁间隔物的栅电极，然后在栅电极上形成牺牲侧壁间隔层。然后在栅极电极上形成掩模层。选择性地蚀刻牺牲侧壁间隔层，以使用图案化掩模层作为蚀刻掩模在第一侧壁间隔物上限定牺牲侧壁间隔物。然后使用牺牲侧壁间隔件作为植入物掩模，将掺杂剂的PFET晕注入物执行到邻近栅电极延伸的部分半导体衬底。在该注入步骤之后，源极和漏极区沟槽在栅电极的相对侧被蚀刻到半导体衬底中。然后通过在其中外延生长SiGe源极和漏极区域来填充这些源极和漏极区沟槽。

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