专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20080046690A1 Processor executing SIMD instructions 审中-公开
公开(公告)号：US20080046690A1
公开(公告)日：2008-02-21
申请号：US11896370
申请日：2007-08-31
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F9/302
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

42. 发明授权

US07185176B2 Processor executing SIMD instructions 有权
标题翻译：处理器执行SIMD指令
公开(公告)号：US07185176B2
公开(公告)日：2007-02-27
申请号：US10449788
申请日：2003-06-02
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Yoshihiro Koga , Manabu Kuroda , Masato Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Shuji Miyasaka
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Yoshihiro Koga , Manabu Kuroda , Masato Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Shuji Miyasaka
IPC分类号： G06F15/80
CPC分类号： G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/3885 , G06F9/3887 , G06F15/8015
摘要： A processor according to the present invention includes a decoding unit, an operation unit and others. When the decoding unit decodes an instruction “vxaddh Rc, Ra, Rb”, an arithmetic and logic/comparison operation unit and others (i) adds the higher 16 bits of a register Ra to the lower 16 bits of the register Rb, stores the result in the higher 16 bits of a register Rc, and in parallel with this, (ii) adds the lower 16 bits of the register Ra to the higher 16 bits of the register Rb, and stores the result in the lower 16 bits of the register Rc.
摘要翻译：根据本发明的处理器包括解码单元，操作单元等。当解码单元解码指令“vxaddh Rc，Ra，Rb”时，算术和逻辑/比较运算单元等（i）将寄存器Ra的高16位加到寄存器Rb的低16位，导致寄存器Rc的高16位，与此并行地，（ii）将寄存器Ra的低16位加到寄存器Rb的较高16位，并将结果存储在寄存器Rc的低16位中注册Rc。

43. 发明申请

US20050216869A1 Compiler 有权
标题翻译：编译器
公开(公告)号：US20050216869A1
公开(公告)日：2005-09-29
申请号：US11087752
申请日：2005-03-24
申请人： Ryoko Miyachi , Tomoo Hamada , Hajime Ogawa , Shohei Michimoto , Yasuhiro Yamamoto , Teruo Kawabata , Hirotetsu Tomita
发明人： Ryoko Miyachi , Tomoo Hamada , Hajime Ogawa , Shohei Michimoto , Yasuhiro Yamamoto , Teruo Kawabata , Hirotetsu Tomita
IPC分类号： G06F17/50
CPC分类号： G06F8/423 , G06F17/505
摘要： A compiler apparatus enabling description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file 24, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unit 30 analyzing syntax of source program 22, an intermediate code converting unit 32 converting the syntactically analyzed source program 22 to an intermediate code and code generating unit 36 converting the intermediate code to the RTL description. The intermediate code converting unit 32 includes a detecting unit 40 detecting a particular hardware defined in the header file 24 out of the source program 22 and a replacing unit 42 replacing the detected particular hardware in the detecting unit 40 with the intermediate code corresponding to a particular hardware.
摘要翻译：尽管在硬件设计中输入编程语言的描述是不可能的，但是使用现有编程语言来描述特定硬件模块的编译器装置。在头文件24中，定义了难以形容的编程语言中的特定硬件。并且编译装置包括分析源程序22的语法的解析器单元30，将语法分析的源程序22转换成将中间代码转换为RTL描述的中间代码和代码生成单元36的中间代码转换单元32。中间代码转换单元32包括检测单元40，其检测来自源程序22中的头文件24中定义的特定硬件;以及替换单元42，用检测单元40中的检测到的特定硬件替换与特定的对应的中间代码硬件。

44. 发明授权

US07350165B2 Compiler 有权
标题翻译：编译器
公开(公告)号：US07350165B2
公开(公告)日：2008-03-25
申请号：US11087752
申请日：2005-03-24
申请人： Ryoko Miyachi , Tomoo Hamada , Hajime Ogawa , Shohei Michimoto , Yasuhiro Yamamoto , Teruo Kawabata , Hirotetsu Tomita
发明人： Ryoko Miyachi , Tomoo Hamada , Hajime Ogawa , Shohei Michimoto , Yasuhiro Yamamoto , Teruo Kawabata , Hirotetsu Tomita
IPC分类号： G06F17/50
CPC分类号： G06F8/423 , G06F17/505
摘要： A compiler apparatus enables description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file 24, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unit 30 analyzing syntax of source program 22, an intermediate code converting unit 32 converting the syntactically analyzed source program 22 to an intermediate code and code generating unit 36 converting the intermediate code to the RTL description. The intermediate code converting unit 32 includes a detecting unit 40 detecting a particular hardware defined in the header file 24 out of the source program 22 and a replacing unit 42 replacing the detected particular hardware in the detecting unit 40 with the intermediate code corresponding to a particular hardware.
摘要翻译：编译装置能够描述现有编程语言中的特定硬件模块，尽管在硬件设计中输入编程语言的描述是不可能的。在头文件24中，定义了难以形容的编程语言中的特定硬件。并且编译装置包括分析源程序22的语法的解析器单元30，将语法分析的源程序22转换成将中间代码转换为RTL描述的中间代码和代码生成单元36的中间代码转换单元32。中间代码转换单元32包括检测单元40，其检测来自源程序22中的头文件24中定义的特定硬件;以及替换单元42，用检测单元40中的检测到的特定硬件替换与特定的对应的中间代码硬件。

45. 发明申请

US20060150135A1 Circuit information generating apparatus and circuit information generating method 审中-公开
标题翻译：电路信息生成装置及电路信息生成方法
公开(公告)号：US20060150135A1
公开(公告)日：2006-07-06
申请号：US11290806
申请日：2005-12-01
申请人： Tomoo Hamada , Hajime Ogawa , Ryoko Miyachi , Shohei Michimoto , Yasuhiro Yamamoto , Teruo Kawabata , Hirotetsu Tomita
发明人： Tomoo Hamada , Hajime Ogawa , Ryoko Miyachi , Shohei Michimoto , Yasuhiro Yamamoto , Teruo Kawabata , Hirotetsu Tomita
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Provided is an apparatus for generating circuit design information automatically clock gated, for the purpose of alleviating the burden of a designer in performing clock gating to a circuit. The apparatus having an obtaining unit operable to obtain functional structure information and execution sequence information from outside, the functional structure information defining a structure of a function and the execution sequence information defining an execution sequence of the function; a structure information generating unit operable to generate, according to the execution sequence information and the functional structure information, circuit structure information in register transfer level which defines a plurality of circuits that execute the function according to the execution sequence; a gated clock information generating unit operable to generate, according to the execution sequence information and the functional structure information, gated clock information in register transfer level which defines a clock control circuit that supplies, to each of at least one of the circuits, a gated clock that is set to halt clock input when the clock input is unnecessary; and an outputting unit operable to output the gated clock information together with the circuit structure information.
摘要翻译：提供了一种用于自动生成电路设计信息时钟门控的装置，用于减轻设计者对电路执行时钟门控的负担。该装置具有可从外部获取功能结构信息和执行序列信息的获取单元，定义功能结构的功能结构信息和定义功能的执行顺序的执行顺序信息; 结构信息生成单元，用于根据执行顺序信息和功能结构信息生成根据执行顺序定义执行功能的多个电路的寄存器传送等级的电路结构信息; 门控时钟信息生成单元，其可操作以根据执行顺序信息和功能结构信息生成寄存器传送级别中的门控时钟信息，其定义时钟控制电路，该时钟控制电路向至少一个电路中的每一个提供门控当不需要时钟输入时，设置为暂停时钟输入的时钟; 以及输出单元，用于将门控时钟信息与电路结构信息一起输出。

46. 发明授权

US06993756B2 Optimization apparatus that decreases delays in pipeline processing of loop and computer-readable storage medium storing optimization program 失效
标题翻译：降低循环流水线处理延迟和存储优化程序的计算机可读存储介质的优化装置
公开(公告)号：US06993756B2
公开(公告)日：2006-01-31
申请号：US09798490
申请日：2001-03-02
申请人： Hajime Ogawa , Shuichi Takayama
发明人： Hajime Ogawa , Shuichi Takayama
IPC分类号： G06F9/45
CPC分类号： G06F8/452 , G06F8/4452
摘要： An optimization apparatus is capable of improving the execution efficiency of a loop that includes a loop carry dependency between consecutive iterations of the loop. For example, a value resulting from one iteration is used in an immediately following iteration. When the arithmetic expression “a[i+1]=a[i]*3+2;” is included in a loop body, and a value resulting from the arithmetic expression “a[i+1]=a[i]*3+2;” in one iteration is used in a following iteration, execution delays occur in pipeline processing of the loop. Here, the arithmetic expression “a[i+1]=a[i]*3+2;” is transformed into the arithmetic expression “a[i+4]=a[i]*81+80;” to expand the dependency distance. By doing so, the execution delays can be decreased.
摘要翻译：优化装置能够提高循环的执行效率，该循环在循环的连续迭代之间包括循环进位依赖性。例如，由一次迭代产生的值在紧随其后的迭代中使用。当算术表达式“a [i + 1] = a [i] * 3 + 2;” 被包含在循环体中，并且由算术表达式“a [i + 1] = a [i] * 3 + 2]得到的值; 在一次迭代中，在下一次迭代中使用，在循环的流水线处理中出现执行延迟。这里，算术表达式“a [i + 1] = a [i] * 3 + 2;” 被转换成算术表达式“a [i + 4] = a [i] * 81 + 80;” 扩大依赖距离。通过这样做，可以减少执行延迟。

47. 发明申请

US20060080643A1 Program processing apparatus 审中-公开
标题翻译：程序处理装置
公开(公告)号：US20060080643A1
公开(公告)日：2006-04-13
申请号：US11233023
申请日：2005-09-23
申请人： Hajime Ogawa , Toshiyuki Sakata
发明人： Hajime Ogawa , Toshiyuki Sakata
IPC分类号： G06F9/44
CPC分类号： G06F8/423 , G06F8/443
摘要： A program processing apparatus, which can correct a source program by automatically inserting hint information so that a satisfactory optimization can be performed even in the case where the user has not given hint information to a compiler, automatically inserts, into the source program, hint information given to the compiler, and includes: a syntax analysis unit which analyzes a syntax of the source program and generates analysis information; and a hint information insertion unit which creates a program by inserting hint information that is logically consistent and that is given to the compiler into the source program based on the analysis information, and outputs the created program.
摘要翻译：一种程序处理装置，其可以通过自动插入提示信息来校正源程序，使得即使在用户没有向编译器提供提示信息的情况下也可以执行令人满意的优化，自动地将其提供给源程序提示信息提供给编译器，并且包括：语法分析单元，其分析源程序的语法并生成分析信息; 以及提示信息插入单元，其通过在逻辑上一致地插入提示信息并且基于分析信息将编译器提供给源程序来创建程序，并输出所创建的程序。

48. 发明授权

US07827542B2 Compiler apparatus 有权
标题翻译：编译器
公开(公告)号：US07827542B2
公开(公告)日：2010-11-02
申请号：US11534719
申请日：2006-09-25
申请人： Hajime Ogawa , Ryoko Miyachi , Toshiyuki Sakata
发明人： Hajime Ogawa , Ryoko Miyachi , Toshiyuki Sakata
IPC分类号： G06F9/45
CPC分类号： G06F8/445
摘要： A compiler apparatus that improves the performance of loop processing. The compiler apparatus translates a C program that includes a loop into a machine language program, and includes: a movement judgment unit that judges whether or not an instruction which is positioned outside of the loop of the C program can be moved into the loop, based on a state of live ranges of variables used in the instruction; a movement execution unit that moves the instruction into the loop in the case where the movement judgment unit judges that the instruction can be moved into the loop, thereby generating an intermediate program; and a translation unit that translates the intermediate program into the machine language program.
摘要翻译：一种提高循环处理性能的编译器。编译装置将包括循环的C程序转换为机器语言程序，并且包括：移动判断单元，其基于C程序的循环以外的指令是否可以移动到循环中在指令中使用的变量的生存范围的状态; 移动执行单元，其在移动判断单元判断该指令可以移动到循环中的情况下将指令移动到循环中，从而生成中间程序; 以及将中间程序转换为机器语言程序的翻译单元。

49. 发明授权

US09304507B2 Tool path display apparatus having display unit for acceleration or jerk of tool tip point 有权
标题翻译：刀具路径显示装置具有用于加工的显示单元或刀尖点的加加速度
公开(公告)号：US09304507B2
公开(公告)日：2016-04-05
申请号：US13532876
申请日：2012-06-26
申请人： Junichi Tezuka , Hajime Ogawa
发明人： Junichi Tezuka , Hajime Ogawa
IPC分类号： G01P7/00 , G01C3/08 , G01M1/38 , G01B5/28 , G05B19/408 , G05B19/4069
CPC分类号： G05B19/408 , G05B19/4069 , G05B2219/35349
摘要： A tool path display apparatus (20) includes a tool coordinate value calculation unit (22) that calculates tool commanded coordinate values and tool actual coordinate values, based on commanded value time series data of position commands for a plurality of axes, detected value time series data of position detected values for the plurality of axes, and the structure of a machine tool, an acceleration calculation unit (23) that calculates accelerations of a tip point of a tool using the tool commanded coordinate values and the tool actual coordinate values, and a display format selection unit (24) that selects display formats of the accelerations of the tool commanded coordinate values and the tool actual coordinate values.
摘要翻译：工具路径显示装置（20）包括：工具坐标值计算部（22），其基于多个轴的位置指令的指令值时间序列数据来计算刀具指令坐标值和刀具实际坐标值，检测值时间序列用于多个轴的位置检测值的数据，以及机床的结构，加速度计算单元（23），其使用所述刀具指令坐标值和所述刀具实际坐标值来计算刀具的尖端的加速度，以及显示格式选择单元（24），其选择工具指令坐标值的加速度和工具实际坐标值的显示格式。

50. 发明授权

US08988032B2 Numerical controller having display function for trajectory of tool 有权
标题翻译：具有工具轨迹显示功能的数字控制器
公开(公告)号：US08988032B2
公开(公告)日：2015-03-24
申请号：US13564989
申请日：2012-08-02
申请人： Yasusuke Iwashita , Hajime Ogawa
发明人： Yasusuke Iwashita , Hajime Ogawa
IPC分类号： G05B19/18 , G05B19/4068
CPC分类号： G05B19/4068 , G05B2219/35349
摘要： A numerical controller capable of visually and accurately analyzing a change of the tool trajectory before and after changing a processing condition, whereby a parameter of a drive axis can be properly adjusted. The numerical controller comprises a numeric controlling part which controls each drive axis based on a predetermined position command; a position data obtaining part which obtains position data of each drive axis controlled by the numerical controlling part; a tool coordinate calculating part which calculates a coordinate of a tool center point based on position feedback or obtained position data of each drive axis and information of a mechanical structure of a machine tool; a tool trajectory storing part which stores the calculated coordinate of the tool center point as a feedback trajectory; and a displaying part which displays the stored feedback trajectory on a display.
摘要翻译：一种数字控制器，其能够在改变处理条件之前和之后视觉上和精确地分析工具轨迹的变化，从而可以适当地调整驱动轴的参数。数值控制器包括：数字控制部，其基于预定位置指令控制各驱动轴; 位置数据获取部，其获取由所述数值控制部控制的各驱动轴的位置数据; 工具坐标计算部，其基于位置反馈或所获得的各驱动轴的位置数据和机床的机械结构的信息来计算刀具中心点的坐标; 工具轨迹存储部，其将所计算的所述工具中心点的坐标存储为反馈轨迹; 以及在显示器上显示存储的反馈轨迹的显示部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式