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41. 发明授权

US06496275B1 Character printing method and device 有权
标题翻译：字符印刷方法和装置
公开(公告)号：US06496275B1
公开(公告)日：2002-12-17
申请号：US09382902
申请日：1999-08-25
申请人： Hiroyasu Kurashina , Minoru Nagata
发明人： Hiroyasu Kurashina , Minoru Nagata
IPC分类号： G06K1502
CPC分类号： B41J11/009 , B41J3/4075
摘要： There are provided a character printing method and device. There are defined print size alternatives to be selectively set to a print size of a printing area of a printing object on which is to be printed part or all of a character group including at least one character. One of the print size alternatives is set to the print size. Print image data is formed by extracting part or all of the character group such that the part or all of the character group is adapted to the print size. A print image is printed on the printing object based on the print image data.
摘要翻译：提供了字符打印方法和装置。存在定义的打印尺寸替代方案，以选择性地设置为打印对象的打印区域的打印尺寸，打印对象的打印部分或全部包括至少一个字符的字符组。其中一种打印尺寸替代方案设置为打印尺寸。通过提取部分或全部的字符组形成打印图像数据，使得该部分或全部字符组适合于打印尺寸。基于打印图像数据将打印图像打印在打印对象上。

42. 发明授权

US6028631A Portable terminal apparatus for multimedia communication 有权
标题翻译：便携式终端设备，用于多媒体通信
公开(公告)号：US6028631A
公开(公告)日：2000-02-22
申请号：US307764
申请日：1999-05-10
申请人： Yuichiro Nakaya , Yukio Fujii , Minoru Nagata , Masanori Maruyama
发明人： Yuichiro Nakaya , Yukio Fujii , Minoru Nagata , Masanori Maruyama
IPC分类号： H04N7/14 , H04N7/26 , H04N7/46 , H04N7/50 , H04N7/12 , H04M11/00
CPC分类号： H04N7/14 , H04N19/42 , H04N19/51 , H04N19/59 , H04N19/61 , H04N2007/145
摘要： The electric power consumption by a terminal used for communication of multimedia information is controlled by changing the quality of transmitted information. The terminal is provided with input means (101, 102, 106 and 107) through which such information as images and sounds is inputted, channel control sections (123 and 124) which output the input information to channels and receive information from the channels, output means (103, 104, 108, 109 and 105) which output the information received from the channels in the form of images, sounds, etc., a codec means (110) which is provided between the input and output means and the control sections, encodes the input information in one of multiple encoding modes in which electric power is differently consumed, and decodes the information inputted from the channels, and a control section (133) which controls the selection of the encoding mode. This terminal can continue information communication for a required period of time at minimum power consumption at the sacrifice of the quality of transmitted information. Therefore, either the power consumption or quality of information can be adequately selected according to the transmission.
摘要翻译：用于多媒体信息通信的终端的电力消耗通过改变发送信息的质量来控制。终端设置有输入图像和声音等信息的输入装置（101,102,106和107），将输入信息输出到信道并从信道接收信息的信道控制部分（123和124），输出输出以图像，声音等形式从信道接收的信息的装置（103,104,108,109和105），设置在输入和输出装置与控制部分之间的编解码装置（110）以不同消耗电力的多个编码模式之一对输入信息进行编码，并对从信道输入的信息进行解码，以及控制编码模式选择的控制部（133）。该终端可以在牺牲所发送的信息的质量的情况下，以最小功耗持续所需时间段的信息通信。因此，可以根据传输来适当地选择功耗或信息质量。

43. 发明授权

US5061645A Method of manufacturing a bipolar transistor 失效
公开(公告)号：US5061645A
公开(公告)日：1991-10-29
申请号：US498489
申请日：1990-03-26
申请人： Kazuo Nakazato , Tohru Nakamura , Masatoshi Matsuda , Takao Miyazaki , Tokuo Kure , Takahiro Okabe , Minoru Nagata
发明人： Kazuo Nakazato , Tohru Nakamura , Masatoshi Matsuda , Takao Miyazaki , Tokuo Kure , Takahiro Okabe , Minoru Nagata
IPC分类号： H01L21/8222 , H01L21/033 , H01L21/3205 , H01L21/331 , H01L27/06 , H01L29/423 , H01L29/70 , H01L29/72 , H01L29/73 , H01L29/732 , H01L29/735
CPC分类号： H01L29/66272 , H01L21/033 , H01L29/42304 , H01L29/72 , H01L29/732 , H01L29/735
摘要： A method of manufacturing a bipolar transistor semiconductor device wherein the active regions of a transistor are formed in an opening provided in an insulating film, electrodes are led out by a polycrystalline silicon film formed on the insulating film, and the upper surfaces of the emitter and base electrodes and the exposed surface of the insulating film are substantially even.

44. 发明授权

US5019523A Process for making polysilicon contacts to IC mesas 失效
标题翻译：使多晶硅接触到IC台面的工艺
公开(公告)号：US5019523A
公开(公告)日：1991-05-28
申请号：US501964
申请日：1990-03-30
申请人： Tohru Nakamura , Takao Miyazaki , Susumu Takahashi , Ichiro Imaizumi , Takahiro Okabe , Minoru Nagata , Masao Kawamura
发明人： Tohru Nakamura , Takao Miyazaki , Susumu Takahashi , Ichiro Imaizumi , Takahiro Okabe , Minoru Nagata , Masao Kawamura
IPC分类号： H01L21/20 , H01L21/285 , H01L21/331 , H01L21/8226 , H01L23/532 , H01L27/02 , H01L27/06 , H01L27/082 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/45 , H01L29/73
CPC分类号： H01L29/0847 , H01L21/02381 , H01L21/02532 , H01L21/02546 , H01L21/28525 , H01L23/53271 , H01L27/0233 , H01L27/06 , H01L29/1004 , H01L29/42304 , H01L29/456 , H01L29/7317 , H01L2924/0002 , Y10S438/965
摘要： Disclosed is a process for making a bipolar transistor which comprises an n-type Si semiconductor body having a convex portion, an insulation film covering the surface of the semiconductor body other than the convex portion, and a p-type polycrystalline Si layer formed on the insulation film. A p-type region formed in the convex portion serves as an intrinsic base region, the polycrystalline Si layer serves as an extrinic base region, an n-type region formed in the intrinsic base region serves as an emitter region, and the body serves as a collector region.

45. 发明授权

US4819055A Semiconductor device having a PN junction formed on an insulator film 失效
标题翻译：具有形成在绝缘膜上的PN结的半导体器件
公开(公告)号：US4819055A
公开(公告)日：1989-04-04
申请号：US189382
申请日：1988-05-02
申请人： Kazuo Nakazato , Tohru Nakamura , Takao Miyazaki , Nobuyoshi Natsuaki , Masahiko Ogirima , Minoru Nagata
发明人： Kazuo Nakazato , Tohru Nakamura , Takao Miyazaki , Nobuyoshi Natsuaki , Masahiko Ogirima , Minoru Nagata
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L29/72 , H01L29/732 , H01L27/12 , H01L29/04 , H01L29/06
CPC分类号： H01L29/66272 , H01L21/8222 , H01L29/72 , H01L29/7325
摘要： The invention deals with a semiconductor device which comprises a semiconductor substrate of a first conductivity type, a semiconductor region formed on said substrate, and a first insulation film provided between said semiconductor region and said semiconductor substrate, wherein said semiconductor substrate is isolated by said insulation film from a polycrystalline silicon layer formed in the periphery of said semiconductor region thereby to reduce the parasitic capacitance, and wherein said insulation film is stretched and arranged on the lower side of said semiconductor region.
摘要翻译：本发明涉及一种半导体器件，其包括第一导电类型的半导体衬底，形成在所述衬底上的半导体区域和设置在所述半导体区域和所述半导体衬底之间的第一绝缘膜，其中所述半导体衬底被所述绝缘体隔离从形成在所述半导体区域的周围的多晶硅层形成的膜，从而减小寄生电容，并且其中所述绝缘膜被拉伸并布置在所述半导体区域的下侧。

46. 发明授权

US4543499A I.sup.2 L circuitry having operating current supplied by higher-voltage circuitry fabricated on same chip 失效
标题翻译： I2L电路具有由在同一芯片上制造的较高电压电路提供的工作电流
公开(公告)号：US4543499A
公开(公告)日：1985-09-24
申请号：US366784
申请日：1982-04-08
申请人： Kenji Kaneko , Minoru Nagata , Makoto Furihata , Setsuo Ogura , Takahiro Okabe , Mitsuya Sato
发明人： Kenji Kaneko , Minoru Nagata , Makoto Furihata , Setsuo Ogura , Takahiro Okabe , Mitsuya Sato
IPC分类号： H01L21/8226 , H01L27/02 , H01L27/06 , H01L27/082 , H03K19/091 , H03K19/092
CPC分类号： H01L27/0244 , H01L27/06
摘要： A semiconductor integrated circuit includes low voltage operation circuitries such as I.sup.2 L and high voltage operation circuitries operating at a higher voltage than the low voltage operation circuitries. Both of the low and high voltage operation circuitries are implemented in a single semiconductor chip in coexistence with each other. The low voltage operation circuitries are disposed in constant current paths in the high voltage operation circuitries so that the currents once used by the high voltage operation circuits are utilized again by the low voltage operation circuitries. Power dissipation of the whole integrated circuit is thus reduced significantly.
摘要翻译：半导体集成电路包括低电压操作电路，例如I2L和高电压工作电路，工作电压高于低电压工作电路。低电压和高电压操作电路都可以在单个半导体芯片中实现，彼此共存。低电压工作电路在高电压工作电路中以恒定电流通路设置，使得高电压操作电路一度使用的电流被低压操作电路再利用。因此整个集成电路的功耗显着降低。

47. 发明授权

US4429326A I.sup.2 L Memory with nonvolatile storage 失效
标题翻译： I2L带非易失性存储器的内存
公开(公告)号：US4429326A
公开(公告)日：1984-01-31
申请号：US96388
申请日：1979-11-21
申请人： Tomoyuki Watanabe , Kenji Kaneko , Tohru Nakamura , Yutaka Okada , Takahiro Okabe , Minoru Nagata , Yokichi Itoh , Toru Toyabe
发明人： Tomoyuki Watanabe , Kenji Kaneko , Tohru Nakamura , Yutaka Okada , Takahiro Okabe , Minoru Nagata , Yokichi Itoh , Toru Toyabe
IPC分类号： G11C11/411 , G11C14/00 , G11C16/04 , H01L27/02 , H01L27/07 , H01L27/102 , G11C11/40 , H01L27/04 , H01L29/78 , H03K19/091
CPC分类号： H01L27/0711 , G11C11/4113 , G11C14/00 , G11C16/0433 , G11C16/0466 , H01L27/0233 , H01L27/1022
摘要： An I.sup.2 L type nonvolatile memory of this invention has a structure wherein a floating gate is disposed through an insulating film on the surface of a semiconductor layer in the vicinity of a base region of an NPN transistor in an I.sup.2 L. The I.sup.2 L type nonvolatile memory of this invention controls current to flow through the base region of the NPN transistor of the I.sup.2 L, by means of charges to be stored in the floating gate. That is, the collector output current of the NPN transistor of the I.sup.2 L is modulated in dependence on the presence or absence of a channel underneath the floating gate as is generated depending on the presence or absence of charges within the floating gate and the polarity of the charges. As a result, the variation of the base current appears as an output signal at a collector terminal of the NPN transistor of the I.sup.2 L, and data stored in the floating gate can be read out.
摘要翻译：本发明的I2L型非易失性存储器具有这样的结构，其中浮置栅极通过I2L中的NPN晶体管的基极区附近的半导体层的表面上的绝缘膜设置。本发明的I2L型非易失性存储器通过要存储在浮动栅极中的电荷来控制电流流过I2L的NPN晶体管的基极区域。也就是说，I2L的NPN晶体管的集电极输出电流根据浮置栅极下面的通道的存在或不存在而被调制，这取决于浮置栅极内的电荷的存在或不存在以及浮置栅极的极性收费。结果，基极电流的变化在I2L的NPN晶体管的集电极端子处显示为输出信号，并且可以读出存储在浮动栅极中的数据。

48. 发明授权

US4015281A MIS-FETs isolated on common substrate 失效
标题翻译：在公共基板上隔离的MIS-FET
公开(公告)号：US4015281A
公开(公告)日：1977-03-29
申请号：US121375
申请日：1971-03-05
申请人： Minoru Nagata , Toshiaki Masuhara , Masaharu Kubo , Norikazu Hashimoto
发明人： Minoru Nagata , Toshiaki Masuhara , Masaharu Kubo , Norikazu Hashimoto
IPC分类号： H01L21/765 , H01L27/088 , H01L29/51 , H01L27/02
CPC分类号： H01L29/511 , H01L21/765 , H01L27/0883
摘要： An enhancement-type and a depletion-type metal-insulator-semiconductor field effect transistor are formed on a common substrate of silicon and are electrically isolated from each other by a plurality of layers including, for example, a first layer of SiO.sub.2, a second layer of Al.sub.2 O.sub.3 capable of inducing holes in the surface portion of the substrate, and a third layer of SiO.sub.2, and the relation between the thicknesses of these layers is suitably selected for attaining the satisfactory isolation between these transistors.
摘要翻译：增强型和耗尽型金属 - 绝缘体 - 半导体场效应晶体管形成在公共的硅衬底上，并且通过多个层彼此电隔离，所述多个层包括例如第一SiO 2层，第二层能够在衬底的表面部分中引入空穴的Al 2 O 3层和SiO 3层，并且适当地选择这些层的厚度之间的关系以获得这些晶体管之间的令人满意的隔离。

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