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41. 发明授权

US5158898A Self-aligned under-gated thin film transistor and method of formation 失效
标题翻译：自对准底栅薄膜晶体管及其形成方法
公开(公告)号：US5158898A
公开(公告)日：1992-10-27
申请号：US794279
申请日：1991-11-19
申请人： James D. Hayden , Bich-Yen Nguyen , Kent J. Cooper
发明人： James D. Hayden , Bich-Yen Nguyen , Kent J. Cooper
IPC分类号： H01L29/78 , H01L21/336 , H01L21/84 , H01L29/786
CPC分类号： H01L29/66765 , H01L21/84 , H01L29/78678
摘要： A self-aligned, under-gated TFT device (10). A base layer (14) is formed. A conductive layer (16) is formed overlying the base layer (14). A dielectric layer (18) is formed overlying the conductive layer (16). A sacrificial layer (20) is formed overlying the dielectric layer (18). The layers (16, 18, and 20) are etched to form a "pillar" region. A dielectric layer (22) and a planar layer (24), which both overlie the "pillar" region, are etched back to form a substantially planar surface and expose a top portion of the sacrificial layer (20). The sacrificial layer (20) is removed and a conductive layer (28) is formed overlying conductive region (16) and planar layer (22). Conductive layer (28) is used to form a self-aligned TFT device (10) via the formation of a source region (33) and a drain region (34) adjacent an aligned plug region (32).
摘要翻译：一种自对准的下栅极TFT器件（10）。形成基层（14）。形成在基底层（14）上方的导电层（16）。形成在导电层（16）上方的电介质层（18）。形成覆盖在电介质层（18）上的牺牲层（20）。层（16,18和20）被蚀刻以形成“柱”区域。将覆盖在“柱”区域上的电介质层（22）和平面层（24）被回蚀刻以形成基本上平坦的表面并且暴露牺牲层（20）的顶部部分。去除牺牲层（20），并且形成覆盖导电区域（16）和平面层（22）的导电层（28）。导电层（28）用于通过形成邻近对准的插塞区域（32）的源区（33）和漏区（34）来形成自对准TFT器件（10）。

42. 发明授权

US4987102A Process for forming high purity thin films 失效
标题翻译：形成高纯度薄膜的方法
公开(公告)号：US4987102A
公开(公告)日：1991-01-22
申请号：US445220
申请日：1989-12-04
申请人： Bich-Yen Nguyen , Jen-Jiang Lee , Hoang K. Nguyen , Young Limb , Philip J. Tobin
发明人： Bich-Yen Nguyen , Jen-Jiang Lee , Hoang K. Nguyen , Young Limb , Philip J. Tobin
IPC分类号： H01L21/31 , H01L21/316 , H01L21/318
CPC分类号： H01L21/02164 , H01L21/02129 , H01L21/0217 , H01L21/02183 , H01L21/02186 , H01L21/022 , H01L21/02205 , H01L21/02274 , H01L21/31608 , H01L21/31612 , H01L21/318 , H01L21/3185
摘要： A method is described for the formation of high purity thin films on a semiconductor substrate. In the preferred embodiment of the invention a thin film is formed on a semiconductor substrate in a plasma enhanced chemical vapor deposition system. Energized silicon ions are obtained by mass analysis and are accelerated into a hydrogen-free plasma. A reaction occurs between energized atoms within the plasma and the energized silicon ions resulting in the deposition of a thin film on the semiconductor substrate.

43. 发明授权

US09496877B2 Pseudo-inverter circuit with multiple independent gate transistors 有权
标题翻译：具有多个独立栅极晶体管的伪逆变器电路
公开(公告)号：US09496877B2
公开(公告)日：2016-11-15
申请号：US14346270
申请日：2011-09-30
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： H03K19/20 , G11C8/08 , G11C11/408
CPC分类号： H03K19/20 , G11C8/08 , G11C11/4085
摘要： The invention relates to a circuit including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors being a multiple gate transistor having at least a first (G1P, G1N) and a second (G2P, G2N) independent control gates, characterized in that at least one of the transistors is configured for operating in a depletion mode under the action of a second gate signal applied to its second control gate (G2p, G2N).
摘要翻译：本发明涉及一种电路，其包括与用于施加电源电位的第一和第二端子之间的第二类型沟道的晶体管串联的第一类型沟道的晶体管，每个晶体管是至少具有多栅极晶体管第一（G1P，G1N）和第二（G2P，G2N）独立控制门，其特征在于，至少一个晶体管被配置为在施加到其第二控制栅极的第二栅极信号的作用下以耗尽模式工作（G2p，G2N）。

44. 发明申请

US20140225648A1 PSEUDO-INVERTER CIRCUIT WITH MULTIPLE INDEPENDENT GATE TRANSISTORS 有权
标题翻译：具有多个独立栅极晶体管的PSEUDO-INVERTER电路
公开(公告)号：US20140225648A1
公开(公告)日：2014-08-14
申请号：US14346270
申请日：2011-09-30
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： H03K19/20
CPC分类号： H03K19/20 , G11C8/08 , G11C11/4085
摘要： The invention relates to a a circuit including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors being a multiple gate transistor having at least a first (G1P, G1N) and a second (G2P, G2N) independent control gates, characterized in that at least one of the transistors is configured for operating in a depletion mode under the action of a second gate signal applied to its second control gate (G2p, G2N).
摘要翻译：本发明涉及一种电路，包括与用于施加电源电位的第一和第二端子之间的第二类型沟道的晶体管串联的第一类型沟道的晶体管，每个晶体管是至少具有多栅极晶体管第一（G1P，G1N）和第二（G2P，G2N）独立控制门，其特征在于，至少一个晶体管被配置为在施加到其第二控制栅极的第二栅极信号的作用下以耗尽模式工作（G2p，G2N）。

45. 发明授权

US08728863B2 Methods of forming bonded semiconductor structures including interconnect layers having one or more of electrical, optical, and fluidic interconnects therein, and bonded semiconductor structures formed using such methods 有权
标题翻译：形成键合半导体结构的方法包括其中具有电，光和流体互连中的一个或多个的互连层，以及使用这种方法形成的结合的半导体结构
公开(公告)号：US08728863B2
公开(公告)日：2014-05-20
申请号：US13206242
申请日：2011-08-09
申请人： Bich-Yen Nguyen , Mariam Sadaka
发明人： Bich-Yen Nguyen , Mariam Sadaka
IPC分类号： H01L21/50 , H01L21/48 , H01L21/44 , H01L23/52 , H01L23/48 , H01L23/538
CPC分类号： H01L23/147 , H01L21/6835 , H01L23/473 , H01L23/49827 , H01L23/5385 , H01L23/5389 , H01L24/80 , H01L25/0652 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2221/68372 , H01L2224/08146 , H01L2224/08225 , H01L2224/24 , H01L2224/80004 , H01L2224/80204 , H01L2224/80895 , H01L2224/80896 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06534 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/1434 , H01L2924/15311 , H01L2924/00
摘要： Methods of forming bonded semiconductor structures include providing a substrate structure including a relatively thinner layer of material on a thicker substrate body, and forming a plurality of through wafer interconnects through the layer of material. A first semiconductor structure may be bonded over the thin layer of material, and at least one conductive feature of the first semiconductor structure may be electrically coupled with at least one of the through wafer interconnects. A transferred layer of material may be provided over the first semiconductor structure on a side thereof opposite the first substrate structure, and at least one of an electrical interconnect, an optical interconnect, and a fluidic interconnect may be formed in the transferred layer of material. A second semiconductor structure may be provided over the transferred layer of material on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are fabricated using such methods.
摘要翻译：形成键合的半导体结构的方法包括在较厚的衬底主体上提供包括相对较薄的材料层的衬底结构，以及通过该材料层形成多个通过晶片互连。第一半导体结构可以结合在材料的薄层上，并且第一半导体结构的至少一个导电特征可以与透晶片互连中的至少一个电耦合。转移的材料层可以在与第一衬底结构相对的一侧上设置在第一半导体结构上，并且可以在转移的材料层中形成电互连，光互连和流体互连中的至少一个。第二半导体结构可以设置在与第一半导体结构相对的一侧上的转移的材料层上。使用这种方法制造粘合的半导体结构。

46. 发明授权

US08652887B2 Multi-layer structures and process for fabricating semiconductor devices 有权
标题翻译：用于制造半导体器件的多层结构和工艺
公开(公告)号：US08652887B2
公开(公告)日：2014-02-18
申请号：US13416813
申请日：2012-03-09
申请人： Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
发明人： Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/76254 , H01L21/02238 , H01L21/32 , H01L21/84 , H01L27/1203
摘要： The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing.
摘要翻译：本发明涉及一种提供绝缘体上硅（SOI）堆叠的方法，其包括衬底层，衬底层上的第一氧化物层和第一氧化物层（BOX层）上的硅层。该方法包括提供SOI堆叠的至少一个第一区域，其中通过热氧化硅层的一部分并提供SOI堆叠的至少一个第二区域来减薄硅层，其中第一氧化物层（BOX层）被稀释通过退火。

47. 发明申请

US20130037960A1 METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES IN 3D INTEGRATION PROCESSES USING RECOVERABLE SUBSTRATES, AND BONDED SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS 有权
标题翻译：使用可恢复基板在3D集成工艺中形成结合的半导体结构的方法和通过这种方法形成的结合的半导体结构
公开(公告)号：US20130037960A1
公开(公告)日：2013-02-14
申请号：US13206280
申请日：2011-08-09
申请人： Mariam Sadaka , Bich-Yen Nguyen
发明人： Mariam Sadaka , Bich-Yen Nguyen
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L21/486 , H01L21/561 , H01L21/6835 , H01L21/76898 , H01L23/147 , H01L23/49827 , H01L24/06 , H01L24/08 , H01L24/80 , H01L24/97 , H01L25/0652 , H01L25/50 , H01L2221/68345 , H01L2224/05009 , H01L2224/08146 , H01L2224/08235 , H01L2224/80099 , H01L2224/80203 , H01L2224/80895 , H01L2224/80896 , H01L2224/9202 , H01L2224/97 , H01L2225/06541 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/1461 , H01L2924/15311 , H01L2924/1816 , H01L2224/80 , H01L2224/03 , H01L2924/00
摘要： Methods of forming bonded semiconductor structures include forming through wafer interconnects through a layer of material of a first substrate structure, bonding one or more semiconductor structures over the layer of material, and electrically coupling the semiconductor structures with the through wafer interconnects. A second substrate structure may be bonded over the processed semiconductor structures on a side thereof opposite the first substrate structure. A portion of the first substrate structure then may be removed, leaving the layer of material with the through wafer interconnects therein attached to the processed semiconductor structures. At least one through wafer interconnects then may be electrically coupled to a conductive feature of another structure, after which the second substrate structure may be removed. Bonded semiconductor structures are formed using such methods.
摘要翻译：形成键合的半导体结构的方法包括通过晶片互连通过第一衬底结构的材料层形成，在材料层上结合一个或多个半导体结构，以及将半导体结构与贯穿晶片互连电连接。第二衬底结构可以在与第一衬底结构相对的一侧上结合在经处理的半导体结构上。然后可以去除第一衬底结构的一部分，留下其中附着有经处理的半导体结构的贯穿晶片互连的材料层。然后至少一个贯穿晶片互连可以电耦合到另一结构的导电特征，之后可以去除第二衬底结构。使用这种方法形成结合的半导体结构。

48. 发明申请

US20130037959A1 METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES INCLUDING INTERCONNECT LAYERS HAVING ONE OR MORE OF ELECTRICAL, OPTICAL, AND FLUIDIC INTERCONNECTS THEREIN, AND BONDED SEMICONDUCTOR STRUCTURES FORMED USING SUCH METHODS 有权
标题翻译：形成粘结半导体结构的方法，其中包括具有电气，光学和流体互连的一个或多个的互连层，以及使用这种方法形成的结合的半导体结构
公开(公告)号：US20130037959A1
公开(公告)日：2013-02-14
申请号：US13206242
申请日：2011-08-09
申请人： Bich-Yen Nguyen , Mariam Sadaka
发明人： Bich-Yen Nguyen , Mariam Sadaka
IPC分类号： H01L21/50 , H01L23/538
CPC分类号： H01L23/147 , H01L21/6835 , H01L23/473 , H01L23/49827 , H01L23/5385 , H01L23/5389 , H01L24/80 , H01L25/0652 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2221/68372 , H01L2224/08146 , H01L2224/08225 , H01L2224/24 , H01L2224/80004 , H01L2224/80204 , H01L2224/80895 , H01L2224/80896 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06534 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/1434 , H01L2924/15311 , H01L2924/00
摘要： Methods of forming bonded semiconductor structures include providing a substrate structure including a relatively thinner layer of material on a thicker substrate body, and forming a plurality of through wafer interconnects through the layer of material. A first semiconductor structure may be bonded over the thin layer of material, and at least one conductive feature of the first semiconductor structure may be electrically coupled with at least one of the through wafer interconnects. A transferred layer of material may be provided over the first semiconductor structure on a side thereof opposite the first substrate structure, and at least one of an electrical interconnect, an optical interconnect, and a fluidic interconnect may be formed in the transferred layer of material. A second semiconductor structure may be provided over the transferred layer of material on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are fabricated using such methods.
摘要翻译：形成键合的半导体结构的方法包括在较厚的衬底主体上提供包括相对较薄的材料层的衬底结构，以及通过该材料层形成多个通过晶片互连。第一半导体结构可以结合在材料的薄层上，并且第一半导体结构的至少一个导电特征可以与透晶片互连中的至少一个电耦合。转移的材料层可以在与第一衬底结构相对的一侧上设置在第一半导体结构上，并且可以在转移的材料层中形成电互连，光互连和流体互连中的至少一个。第二半导体结构可以设置在与第一半导体结构相对的一侧上的转移的材料层上。使用这种方法制造粘合的半导体结构。

49. 发明申请

US20120250444A1 PSEUDO-INVERTER CIRCUIT ON SeOI 有权
标题翻译： PSOUD上的PSEUDO-INVERTER电路
公开(公告)号：US20120250444A1
公开(公告)日：2012-10-04
申请号：US13495632
申请日：2012-06-13
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： G11C8/08 , G05F3/02
CPC分类号： G11C8/08 , G11C11/4085 , G11C2211/4016
摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
摘要翻译：在绝缘体上半导体衬底上制成的电路。该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

50. 发明申请

US20120231606A1 MULTI-LAYER STRUCTURES AND PROCESS FOR FABRICATING SEMICONDUCTOR DEVICES 有权
标题翻译：用于制造半导体器件的多层结构和工艺
公开(公告)号：US20120231606A1
公开(公告)日：2012-09-13
申请号：US13416813
申请日：2012-03-09
申请人： Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
发明人： Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
IPC分类号： H01L21/762
CPC分类号： H01L21/76254 , H01L21/02238 , H01L21/32 , H01L21/84 , H01L27/1203
摘要： The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing.
摘要翻译：本发明涉及一种提供绝缘体上硅（SOI）堆叠的方法，其包括衬底层，衬底层上的第一氧化物层和第一氧化物层（BOX层）上的硅层。该方法包括提供SOI堆叠的至少一个第一区域，其中通过热氧化硅层的一部分并提供SOI堆叠的至少一个第二区域来减薄硅层，其中第一氧化物层（BOX层）被稀释通过退火。

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