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41. 发明授权

US06288954B1 Integrated circuit having an on-board reference generator 有权
标题翻译：具有板载参考发生器的集成电路
公开(公告)号：US06288954B1
公开(公告)日：2001-09-11
申请号：US09233774
申请日：1999-01-19
申请人： Troy Manning
发明人： Troy Manning
IPC分类号： G11C2900
CPC分类号： G11C29/12
摘要： An integrated circuit includes a differential amplifier having a first terminal that is operable to receive an input signal and having a second terminal. The integrated circuit also includes a reference circuit that generates a reference signal on the second terminal of the amplifier. During testing of the integrated circuit, the reference circuit can be activated to generate the reference signal such that a tester need not supply it as a test signal. During normal operation, however, either the reference circuit can generate the reference signal or the reference signal can be supplied by an external source.
摘要翻译：集成电路包括具有可操作以接收输入信号并具有第二端子的第一端子的差分放大器。集成电路还包括在放大器的第二端子上产生参考信号的参考电路。在集成电路测试期间，可以激活参考电路以产生参考信号，使得测试仪不需要将其作为测试信号提供。然而，在正常操作期间，参考电路可以产生参考信号，或者参考信号可以由外部源提供。

42. 发明授权

US6108251A Method and apparatus for remapping memory addresses for redundancy 有权
标题翻译：用于重新映射存储器地址以用于冗余的方法和装置
公开(公告)号：US6108251A
公开(公告)日：2000-08-22
申请号：US364947
申请日：1999-07-30
申请人： Troy Manning
发明人： Troy Manning
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/76 , G11C29/808 , G11C29/81
摘要： A semiconductor memory device includes a memory array having first and second columns, each column having a plurality of memory locations associated therewith and being identified by first and second column addresses, respectively. Column address decoding circuitry receives column address signals and selects at least one column memory array. The column address decoding circuitry is programmable such that the first column may be identified by the second column address and the second column may be identified by the first column address.
摘要翻译：半导体存储器件包括具有第一和第二列的存储器阵列，每列具有与其相关联的多个存储器位置，并且分别由第一和第二列地址识别。列地址解码电路接收列地址信号并选择至少一个列存储器阵列。列地址解码电路是可编程的，使得第一列可以由第二列地址识别，第二列可以由第一列地址来标识。

43. 发明授权

US5910734A Voltage level translator 失效
公开(公告)号：US5910734A
公开(公告)日：1999-06-08
申请号：US803343
申请日：1997-02-20
申请人： Troy Manning
发明人： Troy Manning
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/00361
摘要： A translator includes an initial circuit device configured to charge a translator output to a first voltage level in response to a change in an input signal. The translator further includes a sensing device configured to detect the output's potential approaching the first voltage level and smoothly shift charging functions over to a secondary circuit device, which will continue to charge the output up to a second voltage level.

44. 发明授权

US5793692A Integrated circuit memory with back end mode disable 失效
标题翻译：集成电路存储器，后端模式禁用
公开(公告)号：US5793692A
公开(公告)日：1998-08-11
申请号：US826276
申请日：1997-03-27
申请人： Todd Merritt , Troy Manning
发明人： Todd Merritt , Troy Manning
IPC分类号： G11C11/401 , G11C7/10 , G11C7/00
CPC分类号： G11C7/1045
摘要： A memory circuit is described which can operate in one of a number of operating modes. The operating mode of the memory circuit can be changed in a non-volatile manner after the memory circuit is packaged to reduce production scrap or meet market demands. Disable circuitry is described which includes an anti-fuse that can be externally selectively blown to disable an operating mode. Control circuitry included in the memory circuit enables a new operating mode after the first operating mode is disable. A method of selectively disabling an operating mode is described. A hierarchical scheme is also described for enabling a new operating mode from a group of operating modes, for example page-mode, extended data output (EDO), or burst EDO.
摘要翻译：描述了可以以多种操作模式之一操作的存储器电路。在存储器电路被封装以减少生产废料或满足市场需求之后，可以以非易失性的方式改变存储器电路的工作模式。描述禁止电路，其包括可以从外部选择性地吹制以禁用操作模式的反熔丝。包含在存储器电路中的控制电路在第一操作模式被禁用之后启用新的操作模式。描述了选择性地禁用操作模式的方法。还描述了分层方案，用于从一组操作模式启用新的操作模式，例如页面模式，扩展数据输出（EDO）或突发EDO。

45. 发明授权

US5587671A Semiconductor device having an output buffer which reduces signal degradation due to leakage of current 失效
标题翻译：具有输出缓冲器的半导体器件，其减少由于电流泄漏引起的信号劣化
公开(公告)号：US5587671A
公开(公告)日：1996-12-24
申请号：US238972
申请日：1994-05-05
申请人： Paul Zagar , Troy Manning
发明人： Paul Zagar , Troy Manning
IPC分类号： G11C11/417 , G11C11/409 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0944
CPC分类号： H03K19/01742 , H03K19/00361
摘要： To compensate for leakage current resulting from parasitic resistance, an integrated circuit device includes a boosting current pump to continuously boost the input of an NMOS output circuit so long as the output circuit is providing a logic high output signal. The NMOS output circuit has an input for receiving an input signal and an output for driving at least one output signal line. An oscillation circuit provides an oscillating digital signal to the boosting current pump. The pump responds to the oscillating digital signal and to the input signal being in one of two predetermined states to provide additional current at the input of the NMOS output circuit to compensate for the leakage current.
摘要翻译：为了补偿由寄生电阻引起的泄漏电流，集成电路器件包括升压电流泵，以在输出电路提供逻辑高输出信号时连续升压NMOS输出电路的输入。 NMOS输出电路具有用于接收输入信号的输入和用于驱动至少一个输出信号线的输出。振荡电路向升压电流泵提供振荡数字信号。泵响应振荡数字信号和输入信号处于两个预定状态之一，以在NMOS输出电路的输入处提供额外的电流来补偿漏电流。

46. 发明授权

US08838876B2 Translation layer in a solid state storage device 有权
标题翻译：翻译层在固态存储设备中
公开(公告)号：US08838876B2
公开(公告)日：2014-09-16
申请号：US12250043
申请日：2008-10-13
申请人： Troy Manning
发明人： Troy Manning
IPC分类号： G06F12/00 , G11C16/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F12/0292 , G06F2212/1044 , G06F2212/1048 , G06F2212/2022 , G06F2212/7201 , G06F2212/7208 , G11C16/102 , Y02D10/13
摘要： Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable, logical unit, and plane for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication.
摘要翻译：公开了用于闪存转换层的固态存储设备和方法。在一个这样的翻译层中，通过并行单元查找表将扇区指示转换为存储器位置，由初始化时的存储器设备枚举填充。每个表条目由发现的每个操作存储器件的通信信道，芯片使能，逻辑单元和平面组成。当接收到扇区指示时，模函数对查找表的条目进行操作，以便确定与扇区指示相关联的存储器位置。

47. 发明申请

US20130013981A1 TEMPORARY MIRRORING, LOGICAL SEGREGATION, AND REDUNDANT PROGRAMMING OR ADDRESSING FOR SOLID STATE DRIVE OPERATION 有权
标题翻译：暂时的镜像，逻辑划分和冗余编程或寻址用于固态驱动操作
公开(公告)号：US20130013981A1
公开(公告)日：2013-01-10
申请号：US13618771
申请日：2012-09-14
申请人： Troy Manning
发明人： Troy Manning
IPC分类号： G11C29/04 , G06F11/08
CPC分类号： G06F3/065 , G06F3/0619 , G06F3/0679 , G06F11/2069 , G06F11/2087 , G06F12/0246 , G11C16/349 , G11C29/74
摘要： The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that data associated with a programming operation is programmed to two or more locations in memory of the solid state drive. The method also includes ceasing to mirror programming operations upon an occurrence of a particular event.
摘要翻译：本公开包括用于操作固态驱动器的方法和装置。一种方法实施例包括镜像编程操作，使得与编程操作相关联的数据被编程到固态驱动器的存储器中的两个或多个位置。该方法还包括在发生特定事件时停止镜像编程操作。

48. 发明申请

US20080089158A1 Memory device and method having data path with multiple prefetch I/O configurations 失效
标题翻译：具有多个预取I / O配置的数据路径的存储器件和方法
公开(公告)号：US20080089158A1
公开(公告)日：2008-04-17
申请号：US11999383
申请日：2007-12-04
申请人： Brent Keeth , Brian Johnson , Troy Manning
发明人： Brent Keeth , Brian Johnson , Troy Manning
IPC分类号： G11C7/00
CPC分类号： G11C7/1072 , G11C7/1006 , G11C7/1018 , G11C7/1027 , G11C7/1045 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C11/4093 , G11C11/4096 , G11C2207/107
摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.
摘要翻译：存储器件可以在高模式或低速模式下操作。在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线终端。在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个巴士总站。

49. 发明申请

US20080037342A1 APPARATUS AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY 有权
标题翻译：用于修复半导体存储器的装置和方法
公开(公告)号：US20080037342A1
公开(公告)日：2008-02-14
申请号：US11876477
申请日：2007-10-22
申请人： Chris Martin , Troy Manning , Brent Keeth
发明人： Chris Martin , Troy Manning , Brent Keeth
IPC分类号： G11C7/00 , G11C17/18
CPC分类号： G11C17/165 , G11C29/4401 , G11C29/789 , G11C29/802 , G11C29/808 , G11C2029/4402
摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.
摘要翻译：用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。当第一存储器访问对应于第一缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。

50. 发明申请

US20070153595A1 Apparatus and method for repairing a semiconductor memory 有权
公开(公告)号：US20070153595A1
公开(公告)日：2007-07-05
申请号：US11714979
申请日：2007-03-07
申请人： Chris Martin , Troy Manning , Brent Keeth
发明人： Chris Martin , Troy Manning , Brent Keeth
IPC分类号： G11C29/00
CPC分类号： G11C17/165 , G11C29/4401 , G11C29/789 , G11C29/802 , G11C29/808 , G11C2029/4402
摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

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