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41. 发明授权

US5179673A Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline 失效
标题翻译：使用环形缓冲器的SUBROUTINE返回预测机制，并与实际地址进行比较以预测地址以验证或冲洗管道
公开(公告)号：US5179673A
公开(公告)日：1993-01-12
申请号：US451943
申请日：1989-12-18
申请人： Simon C. Steely, Jr. , David J. Sager
发明人： Simon C. Steely, Jr. , David J. Sager
IPC分类号： G06F9/32 , G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/322 , G06F9/4426
摘要： A method and arrangement for producing a predicted subroutine return address in response to entry of a subroutine return instruction in a computer pipeline that has a ring pointer counter and a ring buffer coupled to the ring pointer counter. The ring pointer counter contains a ring pointer that is changed when either a subroutine call instruction or return instruction enters the computer pipeline. The ring buffer has buffer locations which store a value present at its input into the buffer location pointed to by the ring pointer when a subroutine call instruction enters the pipeline. The ring buffer provides a value from the buffer location pointed to by the ring pointer when a subroutine return instruction enters the computer pipeline, this provided value being the predicted subroutine return address.

42. 发明授权

US10102124B2 High bandwidth full-block write commands 有权
公开(公告)号：US10102124B2
公开(公告)日：2018-10-16
申请号：US13993716
申请日：2011-12-28
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer , Samantika Subramaniam
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer , Samantika Subramaniam
IPC分类号： G06F13/00 , G06F12/0808 , G06F13/28
摘要： A micro-architecture may provide a hardware and software of a high bandwidth write command. The micro-architecture may invoke a method to perform the high bandwidth write command. The method may comprise sending a write request from a requester to a record keeping structure. The write request may have a memory address of a memory that stores requested data. The method may further determine copies of the requested data being present in a distributed cache system outside the memory, sending invalidation requests to elements holding copies of the requested data in the distributed cache system, sending a notification to the requester to inform presence of copies of the requested data and sending a write response message after a latest value of the requested data and all invalidation acknowledgements have been received.

43. 发明授权

US09418016B2 Method and apparatus for optimizing the usage of cache memories 有权
标题翻译：用于优化高速缓存存储器的使用的方法和装置
公开(公告)号：US09418016B2
公开(公告)日：2016-08-16
申请号：US12974907
申请日：2010-12-21
申请人： Simon C. Steely, Jr. , Joel S. Emer , William C. Hasenplaugh
发明人： Simon C. Steely, Jr. , Joel S. Emer , William C. Hasenplaugh
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0815 , G06F2212/1028 , Y02D10/13
摘要： A method and apparatus to reduce unnecessary write backs of cached data to a main memory and to optimize the usage of a cache memory tag directory. In one embodiment of the invention, the power consumption of a processor can be saved by eliminating write backs of cache memory lines that has information that has reached its end-of-life. In one embodiment of the invention, when a processing unit is required to clear one or more cache memory lines, it uses a write-zero command to clear the one or more cache memory lines. The processing unit does not perform a write operation to move or pass data values of zero to the one or more cache memory lines. By doing so, it reduces the power consumption of the processing unit.
摘要翻译：一种减少对主存储器的缓存数据的不必要的回写并优化高速缓存存储器标签目录的使用的方法和装置。在本发明的一个实施例中，通过消除具有已经达到其使用寿命的信息的高速缓冲存储器线的写回，可以节省处理器的功耗。在本发明的一个实施例中，当需要处理单元来清除一个或多个高速缓存存储器线时，它使用写入零命令来清除一个或多个高速缓存存储器线。处理单元不执行写入操作以将数据值0移动或传递给一个或多个高速缓存存储器线。通过这样做，它降低了处理单元的功耗。

44. 发明授权

US08301844B2 Consistency evaluation of program execution across at least one memory barrier 有权
标题翻译：至少一个记忆障碍的程序执行的一致性评估
公开(公告)号：US08301844B2
公开(公告)日：2012-10-30
申请号：US10756534
申请日：2004-01-13
申请人： Simon C. Steely, Jr. , Gregory Edward Tierney
发明人： Simon C. Steely, Jr. , Gregory Edward Tierney
IPC分类号： G06F13/38
CPC分类号： G06F12/0808
摘要： Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system including a processor that executes program instructions across at least one memory barrier. A request engine may provide an updated data fill corresponding to an invalid cache line. The invalid cache line may be associated with at least one executed load instruction. A load compare component may compare the invalid cache line to the updated data fill to evaluate the consistency of the at least one executed load instruction.
摘要翻译：公开了多处理器系统和方法。一个实施例可以包括多处理器系统，其包括跨越至少一个存储器屏障执行程序指令的处理器。请求引擎可以提供对应于无效高速缓存行的更新的数据填充。无效高速缓存行可以与至少一个执行的加载指令相关联。负载比较组件可以将无效高速缓存行与更新的数据填充进行比较，以评估至少一个执行的加载指令的一致性。

45. 发明授权

US07406565B2 Multi-processor systems and methods for backup for non-coherent speculative fills 失效
标题翻译：用于非相干投机填充的多处理器系统和备份方法
公开(公告)号：US07406565B2
公开(公告)日：2008-07-29
申请号：US10756637
申请日：2004-01-13
申请人： Simon C. Steely, Jr. , Gregory Edward Tierney
发明人： Simon C. Steely, Jr. , Gregory Edward Tierney
IPC分类号： G06F9/00 , G06F9/38 , G06F13/00
CPC分类号： G06F9/383 , G06F9/384 , G06F9/3842 , G06F9/3863 , G06F12/0815
摘要： Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in response to a source request, and a backup system that retains information associated with a previous processor execution state corresponding to an instruction associated with the speculative fill. The backup system may initiate a backup of the processor pipeline to the previous processor execution state if the speculative fill is determined to be non-coherent, and the processor pipeline may continue execution of program instructions if the speculative fill is determined to be coherent.
摘要翻译：公开了多处理器系统和方法。一个实施例可以包括多处理器系统，其包括具有处理器流水线的处理器，处理器流水线通过响应于源请求而提供的来自推测填充的数据执行程序指令，以及备份系统，其保留与先前处理器执行状态相关联的信息对应于与投机填充相关联的指令。如果确定推测填充是非相干的，则备用系统可以启动处理器管线的备份到先前的处理器执行状态，并且如果确定推测填充是相干的，则处理器流水线可以继续执行程序指令。

46. 发明授权

US5953747A Apparatus and method for serialized set prediction 失效
公开(公告)号：US5953747A
公开(公告)日：1999-09-14
申请号：US668316
申请日：1996-06-26
申请人： Simon C. Steely, Jr. , Joseph Dominic Macri
发明人： Simon C. Steely, Jr. , Joseph Dominic Macri
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： A prediction mechanism for improving direct-mapped cache performance is shown to include a direct-mapped cache, partitioned into a plurality of pseudo-banks. Prediction means are employed to provide a prediction index which is appended to the cache index to provide the entire address for addressing the direct mapped cache. One embodiment of the prediction means includes a prediction cache which is advantageously larger than the pseudo-banks of the direct-mapped cache and is used to store the prediction index for each cache location. A second embodiment includes a plurality of partial tag stores, each including a predetermined number of tag bits for the data in each bank. A comparison of the tags generates a match in one of the plurality of tag stores, and is used in turn to generate a prediction index. A third embodiment for use with a direct mapped cache divided into two partitions includes a distinguishing bit ram, which is used to provide the bit number of any bit which differs between the tags at the same location in the different banks. The bit number is used in conjunction with a complement signal to provide the prediction index for addressing the direct-mapped cache.

47. 发明授权

US5828874A Past-history filtered branch prediction 失效
标题翻译：过去历史过滤分支预测
公开(公告)号：US5828874A
公开(公告)日：1998-10-27
申请号：US626868
申请日：1996-06-05
申请人： Simon C. Steely, Jr. , David J. Sager
发明人： Simon C. Steely, Jr. , David J. Sager
IPC分类号： G06F9/30 , G06F9/312 , G06F9/38 , G06F9/40
CPC分类号： G06F9/3806 , G06F9/30043 , G06F9/3012 , G06F9/30134 , G06F9/30141 , G06F9/3836 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A branch prediction apparatus includes a predicted past history device, and a a branch prediction device. The predicted past history device is operable to receive an indication of a branch instruction and to output a pattern of past predictions of branch directions for the indicated branch instruction. The pattern of past predictions includes at least one prediction of a branch direction for which the correctness of the prediction has not been determined The branch prediction device is operable to receive the pattern of past predictions of branch directions for the indicated branch instruction and to output a predicted branch direction for the indicated branch instruction based on the received pattern of past predictions.
摘要翻译：分支预测装置包括预测的过去历史装置和分支预测装置。预测的过去历史装置可操作以接收分支指令的指示并输出针对所指示的分支指令的分支方向的过去预测的模式。过去预测的模式包括尚未确定预测的正确性的分支方向的至少一个预测。分支预测装置可操作以接收针对所指示的分支指令的分支方向的过去预测的模式，并输出基于接收到的过去预测模式，为指示的分支指令预测分支方向。

48. 发明授权

US5581719A Multiple block line prediction 失效
标题翻译：多块线预测
公开(公告)号：US5581719A
公开(公告)日：1996-12-03
申请号：US401656
申请日：1995-03-10
申请人： Simon C. Steely, Jr. , David J. Sager
发明人： Simon C. Steely, Jr. , David J. Sager
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3863 , G06F9/30054 , G06F9/3012 , G06F9/30141 , G06F9/3806 , G06F9/3814 , G06F9/3848
摘要： A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by said set of instructions, to reorder the issuance of said set of instructions from said instruction processor. The mapped register operand fields are associated with the corresponding instructions of said reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.
摘要翻译：流水线处理器包括指令盒，其包括寄存器映射器，映射一组指令的寄存器操作数字段和由所述指令组馈送的指令调度器，以从所述指令处理器重新排序所述指令集的发布。映射的寄存器操作数字段在指令发布之前与所述重新排序的指令集的相应指令相关联。处理器还包括分支预测表，其将与分支指令相关联的过去历史的存储模式映射到分支指令的更可能的预测方向。处理器还包括与指令调度器相关联的存储器参考标记存储器，使得调度器可以在不知道由存储器参考指令寻址的实际存储器位置的情况下重新排序存储器参考指令。

49. 发明授权

US08769209B2 Method and apparatus for achieving non-inclusive cache performance with inclusive caches 有权
标题翻译：用于通过包含缓存实现非包容性缓存性能的方法和装置
公开(公告)号：US08769209B2
公开(公告)日：2014-07-01
申请号：US12973051
申请日：2010-12-20
申请人： Aamer Jaleel , Simon C. Steely, Jr. , Eric R. Borch , Malini K. Bhandaru , Joel S. Emer
发明人： Aamer Jaleel , Simon C. Steely, Jr. , Eric R. Borch , Malini K. Bhandaru , Joel S. Emer
IPC分类号： G06F12/12
CPC分类号： G06F12/0813 , G06F12/128
摘要： An apparatus and method for improving cache performance in a computer system having a multi-level cache hierarchy. For example, one embodiment of a method comprises: selecting a first line in a cache at level N for potential eviction; querying a cache at level M in the hierarchy to determine whether the first cache line is resident in the cache at level M, wherein M
摘要翻译：一种用于在具有多级高速缓存层级的计算机系统中提高高速缓存性能的装置和方法。例如，方法的一个实施例包括：在级别N的高速缓存中选择潜在驱逐的第一行; 查询层级中的级别M的高速缓存，以确定第一高速缓存行是否驻留在级别M的高速缓存中，其中M

50. 发明授权

US07725657B2 Dynamic quality of service (QoS) for a shared cache 有权
标题翻译：共享缓存的动态服务质量（QoS）
公开(公告)号：US07725657B2
公开(公告)日：2010-05-25
申请号：US11726238
申请日：2007-03-21
申请人： William C. Hasenplaugh , Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell , Aamer Jaleel , Simon C. Steely, Jr.
发明人： William C. Hasenplaugh , Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell , Aamer Jaleel , Simon C. Steely, Jr.
IPC分类号： G06F12/06
CPC分类号： G06F12/084 , G06F12/0842
摘要： In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory by a core to indicate a priority level of a first thread, and associating a second priority indicator with data stored in a second entry of the shared cache memory by a graphics engine to indicate a priority level of a second thread. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于将第一优先级指示符与存储在共享高速缓冲存储器的第一条目中的数据相关联以指示第一线程的优先级，并且将第二优先级指示符与存储的数据相关联的方法在图形引擎的共享高速缓冲存储器的第二条目中指示第二线程的优先级。描述和要求保护其他实施例。

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