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1. 发明申请

US20130326147A1 SHORT CIRCUIT OF PROBES IN A CHAIN 有权
标题翻译：链中探针的短路
公开(公告)号：US20130326147A1
公开(公告)日：2013-12-05
申请号：US13996012
申请日：2011-12-29
申请人： Simon C. Steely, JR. , Samantika Subramaniam , William C. Hasenplaugh , Joel S. Emer
发明人： Simon C. Steely, JR. , Samantika Subramaniam , William C. Hasenplaugh , Joel S. Emer
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/082
摘要： A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining that a local last accessor of the memory address may have a copy of the requested data up to date with the memory. The local last accessor may be within a local domain that the requester belongs to. The method may further comprise sending a cache probe to the local last accessor and retrieving a latest value of the requested data from the local last accessor to the requester.
摘要翻译：多核处理装置可以提供高速缓存探针和数据检索方法。该方法可以包括将请求者的存储器请求发送到记录保存结构。存储器请求可以具有存储请求的数据的存储器的存储器地址。该方法还可以包括确定存储器地址的本地最后访问器可以具有与存储器一起的所请求数据的副本。本地最后一个访问者可能在请求者所属的本地域内。该方法还可以包括向本地最后一个访问器发送高速缓存探测器，并且从本地最后一个访问器检索所请求的数据的最新值到请求者。

2. 发明授权

US10102124B2 High bandwidth full-block write commands 有权
公开(公告)号：US10102124B2
公开(公告)日：2018-10-16
申请号：US13993716
申请日：2011-12-28
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer , Samantika Subramaniam
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer , Samantika Subramaniam
IPC分类号： G06F13/00 , G06F12/0808 , G06F13/28
摘要： A micro-architecture may provide a hardware and software of a high bandwidth write command. The micro-architecture may invoke a method to perform the high bandwidth write command. The method may comprise sending a write request from a requester to a record keeping structure. The write request may have a memory address of a memory that stores requested data. The method may further determine copies of the requested data being present in a distributed cache system outside the memory, sending invalidation requests to elements holding copies of the requested data in the distributed cache system, sending a notification to the requester to inform presence of copies of the requested data and sending a write response message after a latest value of the requested data and all invalidation acknowledgements have been received.

3. 发明授权

US09201792B2 Short circuit of probes in a chain 有权
标题翻译：探针在链中短路
公开(公告)号：US09201792B2
公开(公告)日：2015-12-01
申请号：US13996012
申请日：2011-12-29
申请人： Simon C. Steely, Jr. , Samantika Subramaniam , William C. Hasenplaugh , Joel S. Emer
发明人： Simon C. Steely, Jr. , Samantika Subramaniam , William C. Hasenplaugh , Joel S. Emer
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/082
摘要： A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining that a local last accessor of the memory address may have a copy of the requested data up to date with the memory. The local last accessor may be within a local domain that the requester belongs to. The method may further comprise sending a cache probe to the local last accessor and retrieving a latest value of the requested data from the local last accessor to the requester.
摘要翻译：多核处理装置可以提供高速缓存探针和数据检索方法。该方法可以包括将请求者的存储器请求发送到记录保存结构。存储器请求可以具有存储请求的数据的存储器的存储器地址。该方法还可以包括确定存储器地址的本地最后访问器可以具有与存储器一起的所请求数据的副本。本地最后一个访问者可能在请求者所属的本地域内。该方法还可以包括向本地最后一个访问器发送高速缓存探测器，并且从本地最后一个访问器检索所请求的数据的最新值到请求者。

4. 发明授权

US09418016B2 Method and apparatus for optimizing the usage of cache memories 有权
标题翻译：用于优化高速缓存存储器的使用的方法和装置
公开(公告)号：US09418016B2
公开(公告)日：2016-08-16
申请号：US12974907
申请日：2010-12-21
申请人： Simon C. Steely, Jr. , Joel S. Emer , William C. Hasenplaugh
发明人： Simon C. Steely, Jr. , Joel S. Emer , William C. Hasenplaugh
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0815 , G06F2212/1028 , Y02D10/13
摘要： A method and apparatus to reduce unnecessary write backs of cached data to a main memory and to optimize the usage of a cache memory tag directory. In one embodiment of the invention, the power consumption of a processor can be saved by eliminating write backs of cache memory lines that has information that has reached its end-of-life. In one embodiment of the invention, when a processing unit is required to clear one or more cache memory lines, it uses a write-zero command to clear the one or more cache memory lines. The processing unit does not perform a write operation to move or pass data values of zero to the one or more cache memory lines. By doing so, it reduces the power consumption of the processing unit.
摘要翻译：一种减少对主存储器的缓存数据的不必要的回写并优化高速缓存存储器标签目录的使用的方法和装置。在本发明的一个实施例中，通过消除具有已经达到其使用寿命的信息的高速缓冲存储器线的写回，可以节省处理器的功耗。在本发明的一个实施例中，当需要处理单元来清除一个或多个高速缓存存储器线时，它使用写入零命令来清除一个或多个高速缓存存储器线。处理单元不执行写入操作以将数据值0移动或传递给一个或多个高速缓存存储器线。通过这样做，它降低了处理单元的功耗。

5. 发明申请

US20140052920A1 DOMAIN STATE 有权
标题翻译：域名
公开(公告)号：US20140052920A1
公开(公告)日：2014-02-20
申请号：US13995991
申请日：2011-12-29
申请人： Simon C. Steely, JR. , William C. Hasenplaugh , Joel S. Emer
发明人： Simon C. Steely, JR. , William C. Hasenplaugh , Joel S. Emer
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F12/0811 , G06F12/0817 , G06F13/00
摘要： Method and apparatus to efficiently maintain cache coherency by reading/writing a domain state field associated with a tag entry within a cache tag directory. A value may be assigned to a domain state field of a tag entry in a cache tag directory. The cache tag directory may belong to a hierarchy of cache tag directories.Each tag entry may be associated with a cache line from a cache belonging to a first domain. The first domain may contain multiple caches. The value of the domain state field may indicate whether its associated cache line can be read or changed.
摘要翻译：通过读/写与缓存标签目录中的标签条目相关联的域状态字段来有效地维持高速缓存一致性的方法和装置。可以将值分配给缓存标签目录中的标签条目的域状态字段。缓存标签目录可能属于高速缓存标签目录的层次结构。每个标签条目可以与来自属于第一域的高速缓存行相关联。第一个域可能包含多个缓存。域状态字段的值可以指示其相关联的高速缓存行是否可以被读取或改变。

6. 发明授权

US09262327B2 Signature based hit-predicting cache 有权
标题翻译：基于签名的命中预测缓存
公开(公告)号：US09262327B2
公开(公告)日：2016-02-16
申请号：US13538390
申请日：2012-06-29
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Aamer Jaleel , Joel S. Emer , Carole-Jean Wu
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Aamer Jaleel , Joel S. Emer , Carole-Jean Wu
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： An apparatus may comprise a cache file having a plurality of cache lines and a hit predictor. The hit predictor may contain a table of counter values indexed with signatures that are associated with the plurality of cache lines. The apparatus may fill cache lines into the cache file with either low or high priority. Low priority lines may be chosen to be replaced by a replacement algorithm before high priority lines. In this way, the cache naturally may contain more high priority lines than low priority ones. This priority filling process may improve the performance of most replacement schemes including the best known schemes which are already doing better than LRU.
摘要翻译：装置可以包括具有多个高速缓存行和命中预测器的高速缓存文件。命中预测器可以包含用与多个高速缓存行相关联的签名索引的计数器值的表。该装置可以以低优先级或高优先级将高速缓存行填充到高速缓存文件中。低优先级行可以被选择为在高优先级行之前由替换算法代替。以这种方式，高速缓存当然可以包含比优先级更高的优先级更高的行。该优先填充过程可以改善大多数替换方案的性能，包括已经比LRU更好的已知方案。

7. 发明授权

US09588889B2 Domain state 有权
标题翻译：域状态
公开(公告)号：US09588889B2
公开(公告)日：2017-03-07
申请号：US13995991
申请日：2011-12-29
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0802 , G06F12/0811 , G06F12/0817 , G06F13/00
摘要： Method and apparatus to efficiently maintain cache coherency by reading/writing a domain state field associated with a tag entry within a cache tag directory. A value may be assigned to a domain state field of a tag entry in a cache tag directory. The cache tag directory may belong to a hierarchy of cache tag directories. Each tag entry may be associated with a cache line from a cache belonging to a first domain. The first domain may contain multiple caches. The value of the domain state field may indicate whether its associated cache line can be read or changed.
摘要翻译：通过读/写与缓存标签目录中的标签条目相关联的域状态字段来有效地维持高速缓存一致性的方法和装置。可以将值分配给缓存标签目录中的标签条目的域状态字段。缓存标签目录可能属于高速缓存标签目录的层次结构。每个标签条目可以与来自属于第一域的高速缓存行相关联。第一个域可能包含多个缓存。域状态字段的值可以指示其相关联的高速缓存行是否可以被读取或改变。

8. 发明申请

US20120159077A1 METHOD AND APPARATUS FOR OPTIMIZING THE USAGE OF CACHE MEMORIES 有权
标题翻译：优化缓存使用的方法和设备
公开(公告)号：US20120159077A1
公开(公告)日：2012-06-21
申请号：US12974907
申请日：2010-12-21
申请人： SIMON C. STEELY, JR. , Joel S. Emer , William C. Hasenplaugh
发明人： SIMON C. STEELY, JR. , Joel S. Emer , William C. Hasenplaugh
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0815 , G06F2212/1028 , Y02D10/13
摘要： A method and apparatus to reduce unnecessary write backs of cached data to a main memory and to optimize the usage of a cache memory tag directory. In one embodiment of the invention, the power consumption of a processor can be saved by eliminating write backs of cache memory lines that has information that has reached its end-of-life. In one embodiment of the invention, when a processing unit is required to clear one or more cache memory lines, it uses a write-zero command to clear the one or more cache memory lines. The processing unit does not perform a write operation to move or pass data values of zero to the one or more cache memory lines. By doing so, it reduces the power consumption of the processing unit.
摘要翻译：一种减少对主存储器的缓存数据的不必要的回写并优化高速缓存存储器标签目录的使用的方法和装置。在本发明的一个实施例中，通过消除具有已经达到其使用寿命的信息的高速缓冲存储器线的写回，可以节省处理器的功耗。在本发明的一个实施例中，当需要处理单元来清除一个或多个高速缓存存储器线时，它使用写入零命令来清除一个或多个高速缓存存储器线。处理单元不执行写入操作以将数据值0移动或传递给一个或多个高速缓存存储器线。通过这样做，它降低了处理单元的功耗。

9. 发明授权

US09146871B2 Retrieval of previously accessed data in a multi-core processor 有权
标题翻译：在多核处理器中检索以前访问过的数据
公开(公告)号：US09146871B2
公开(公告)日：2015-09-29
申请号：US13995283
申请日：2011-12-28
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer
IPC分类号： G06F13/00 , G06F12/08 , G06F13/38 , G06F13/10
CPC分类号： G06F12/0822 , G06F12/0817 , G06F12/0846 , G06F13/00 , G06F13/10 , G06F13/385
摘要： A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining a last accessor of the memory address, sending a cache probe to the last accessor, determining the last accessor no longer has a copy of the line; and sending a request for the previously accessed version of the line. The request may bypass the tag-directories and obtain the requested data from memory.
摘要翻译：多核处理装置可以提供高速缓存探针和数据检索方法。该方法可以包括将请求者的存储器请求发送到记录保存结构。存储器请求可以具有存储请求的数据的存储器的存储器地址。该方法还可以包括确定存储器地址的最后存取器，向最后一个存取器发送高速缓存探测器，确定最后一个访问器不再具有该行的副本; 并发送对先前访问版本的行的请求。该请求可以绕过标签目录并从存储器获取所请求的数据。

10. 发明授权

US09037804B2 Efficient support of sparse data structure access 有权
标题翻译：有效支持稀疏数据结构访问
公开(公告)号：US09037804B2
公开(公告)日：2015-05-19
申请号：US13995209
申请日：2011-12-29
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer
IPC分类号： G06F13/00 , G06F12/08
CPC分类号： G06F12/0891 , G06F12/0895
摘要： Method and apparatus to efficiently organize data in caches by storing/accessing data of varying sizes in cache lines. A value may be assigned to a field indicating the size of usable data stored in a cache line. If the field indicating the size of the usable data in the cache line indicates a size less than the maximum storage size, a value may be assigned to a field in the cache line indicating which subset of the data in the field to store data is usable data. A cache request may determine whether the size of the usable data in a cache line is equal to the maximum data storage size. If the size of the usable data in the cache line is equal to the maximum data storage size the entire stored data in the cache line may be returned.
摘要翻译：通过在高速缓存行中存储/访问不同大小的数据来高效地组织高速缓存中的数据的方法和装置。可以将值分配给指示存储在高速缓存行中的可用数据的大小的字段。如果指示高速缓存行中的可用数据的大小的字段指示小于最大存储大小的大小，则可以将值分配给高速缓存行中的字段，指示字段中存储数据的数据的哪个子集是可用的数据。缓存请求可以确定高速缓存行中的可用数据的大小是否等于最大数据存储大小。如果高速缓存行中的可用数据的大小等于最大数据存储大小，则可以返回高速缓存行中的整个存储数据。

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