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41. 发明申请

US20050042538A1 Antireflective hardmask and uses thereof 有权
标题翻译：防反射硬质掩模及其用途
公开(公告)号：US20050042538A1
公开(公告)日：2005-02-24
申请号：US10646307
申请日：2003-08-22
申请人： Katherina Babich , Elbert Huang , Arpan Mahorowala , David Medeiros , Dirk Pfeiffer , Karen Temple
发明人： Katherina Babich , Elbert Huang , Arpan Mahorowala , David Medeiros , Dirk Pfeiffer , Karen Temple
IPC分类号： G03F7/11 , G03F7/00 , G03F7/004 , G03F7/075 , G03F7/09 , H01L21/027 , H01L21/32 , H01L21/3205 , H01L21/3213
CPC分类号： G03F7/091 , G03F7/0045 , G03F7/0757 , H01L21/0274 , H01L21/32139 , Y10S430/106 , Y10S430/115 , Y10S430/143 , Y10S430/151
摘要： Antireflective hardmask compositions and techniques for the use of antireflective hardmask compositions for processing of semiconductor devices are provided. In one aspect of the invention, an antireflective hardmask layer for lithography is provided. The antireflective hardmask layer comprises a carbosilane polymer backbone comprising at least one chromophore moiety and at least one transparent moiety; and a crosslinking component. In another aspect of the invention, a method for processing a semiconductor device is provided. The method comprises the steps of: providing a material layer on a substrate; forming an antireflective hardmask layer over the material layer. The antireflective hardmask layer comprises a carbosilane polymer backbone comprising at least one chromophore moiety and at least one transparent moiety; and a crosslinking component.
摘要翻译：提供了用于半导体器件加工的抗反射硬掩模组合物的抗反射硬掩模组合物和技术。在本发明的一个方面，提供了用于光刻的抗反射硬掩模层。抗反射硬掩模层包含含有至少一个发色团部分和至少一个透明部分的碳硅烷聚合物主链; 和交联组分。在本发明的另一方面，提供一种用于处理半导体器件的方法。该方法包括以下步骤：在衬底上提供材料层; 在材料层上形成抗反射硬掩模层。抗反射硬掩模层包含含有至少一个发色团部分和至少一个透明部分的碳硅烷聚合物主链; 和交联组分。

42. 发明申请

US20090200683A1 INTERCONNECT STRUCTURES WITH PARTIALLY SELF ALIGNED VIAS AND METHODS TO PRODUCE SAME 审中-公开
标题翻译：具有部分自对准VIAS的互连结构及其生产方法
公开(公告)号：US20090200683A1
公开(公告)日：2009-08-13
申请号：US12030756
申请日：2008-02-13
申请人： Matthew Earl Colburn , Nicholas C. Fuller , Elbert Huang , Satyanarayana V. Nitta
发明人： Matthew Earl Colburn , Nicholas C. Fuller , Elbert Huang , Satyanarayana V. Nitta
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76811 , H01L21/76813
摘要： An interconnect structure having partially self aligned vias with an interlayer dielectric layer on a substrate, containing at least two conducting metal lines that traverse parallel to the substrate and at least two conducting metal vias that are orthogonal to the substrate. A method of producing the self aligned vias by depositing an interlayer dielectric layer onto a substrate, depositing at least one hardmask onto the interlayer dielectric layer, lithographically forming a via pattern with elongated via features and lithographically forming a line pattern in either order, then either transferring the line patterns first into the interlayer dielectric layer forming line features or transferring the via pattern first into the interlayer dielectric layer as long as the patterns overlap to forming self aligned via features, depositing conducting metals and filling regions corresponding to the line and via features, and planarizing and removing excess metal from the line and via features.
摘要翻译：具有部分自对准的通孔的互连结构，其中在衬底上具有层间电介质层，其包含至少两条横穿平行于衬底的导电金属线和至少两个与衬底正交的导电金属通孔。一种通过在衬底上沉积层间电介质层来生产自对准通孔的方法，将至少一个硬掩模沉积到层间电介质层上，以光刻方式形成具有细长通孔特征的通孔图案，并以任何顺序光刻形成线图案，然后只要图案重叠以形成自对准的通孔特征，沉积导电金属和对应于该线的通孔特征的填充区域，首先将线图案首先转移到层间介质层形成线的特征中或者将该通孔图案转移到层间电介质层中并且从线和通孔特征平坦化和去除多余的金属。

43. 发明申请

US20080220615A1 METHOD FOR PRODUCING SELF-ALIGNED MASK, ARTICLES PRODUCED BY SAME AND COMPOSITION FOR SAME 有权
标题翻译：用于生产自对准掩模的方法，由其生产的制品及其组合物
公开(公告)号：US20080220615A1
公开(公告)日：2008-09-11
申请号：US12107889
申请日：2008-04-23
申请人： Timothy A. Brunner , Matthew E. Colburn , Elbert Huang , Muthumanickam Sankarapandian
发明人： Timothy A. Brunner , Matthew E. Colburn , Elbert Huang , Muthumanickam Sankarapandian
IPC分类号： H01L21/027
CPC分类号： H01L21/76834 , G03F7/0035 , G03F7/2022 , H01L21/76849 , Y10S430/146
摘要： A method for forming a self-aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material being either photo or thermally sensitive; performing a blanket exposure of the substrate; and allowing at least a portion of the masking material to preferential develop in a fashion that is replicates the existing pattern of the substrate. The existing pattern may be comprised of a first set of regions of the substrate having a first reflectivity and a second set of regions of the substrate having a second reflectivity different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. Structures made in accordance with the method.
摘要翻译：一种用于在衬底上的现有图案上形成自对准图案的方法，包括在载体中涂覆含有掩蔽材料的溶液的涂层，所述掩蔽材料是光敏的或热敏感的; 进行基板的覆盖曝光; 并且允许至少一部分掩模材料以复制衬底的现有图案的方式优先显影。现有图案可以由具有第一反射率的第一组基底区域和第二组区域组成，该第二组区域具有不同于第一组成的第二反射率。第一组区域可以包括一个或多个金属元件，并且第二组区域可以包括电介质。按照该方法制造的结构。

44. 发明授权

US07214603B2 Method for fabricating interconnect structures with reduced plasma damage 有权
标题翻译：制造具有降低的等离子体损伤的互连结构的方法
公开(公告)号：US07214603B2
公开(公告)日：2007-05-08
申请号：US10908931
申请日：2005-06-01
申请人： Ronald Dellaguardia , Elbert Huang , Qinghuang Lin , Robert Miller
发明人： Ronald Dellaguardia , Elbert Huang , Qinghuang Lin , Robert Miller
IPC分类号： H01L21/44 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/76835 , H01L21/76808 , H01L21/76829
摘要： Methods to form interconnect structures utilizing sacrificial filling material layers are described herein. Utilizing the sacrificial filling material makes it possible to reduce damage to interlayer dielectric layers that result in enhanced device performance and/or increased reliability.
摘要翻译：本文描述了利用牺牲填充材料层形成互连结构的方法。利用牺牲填充材料使得可以减少导致增强的器件性能和/或增加的可靠性的层间电介质层的损伤。

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