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41. 发明授权

US07030688B2 Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit 失效
标题翻译：用于PLL，锁相环和半导体集成电路的低通滤波器
公开(公告)号：US07030688B2
公开(公告)日：2006-04-18
申请号：US10500875
申请日：2003-05-22
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
IPC分类号： H03K5/00
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/0893 , H03L7/0896 , H03L7/093
摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.
摘要翻译：本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311）电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

42. 发明授权

US06424184B1 FREQUENCY-VOLTAGE CONVERSION CIRCUIT, DELAY AMOUNT JUDGEMENT CIRCUIT, SYSTEM HAVING FREQUENCY-VOLTAGE CONVERSION CIRCUIT, METHOD OF ADJUSTING INPUT/OUTPUT CHARACTERISTICS OF FREQUENCY-VOLTAGE CONVERSION CIRCUIT, AND APPARATUS FOR AUTOMATICALLY ADJUSTING INPUT 失效
标题翻译：频率转换电路，延迟量判定电路，具有电压转换电路的系统，调整频率转换电路的输入/输出特性的方法以及用于自动调整输入的装置
公开(公告)号：US06424184B1
公开(公告)日：2002-07-23
申请号：US09269315
申请日：1999-03-24
申请人： Akira Yamamoto , Shiro Sakiyama , Hiroyuki Nakahira , Masaru Fukuda , Akira Matsuzawa , Shiro Dosho , Shinichi Yamamoto
发明人： Akira Yamamoto , Shiro Sakiyama , Hiroyuki Nakahira , Masaru Fukuda , Akira Matsuzawa , Shiro Dosho , Shinichi Yamamoto
IPC分类号： H03D300
CPC分类号： G01R23/06 , G06F1/3203 , Y02D10/126
摘要： A frequency-voltage conversion circuit 21 receives a clock CLK as an input and provides a voltage IVdd in accordance with the frequency of the clock as an output. The input and output characteristic of the frequency-voltage conversion circuit 21 is adjusted to substantially match a given input and output characteristic.
摘要翻译：频率电压转换电路21接收时钟CLK作为输入，并根据时钟的频率提供电压IVdd作为输出。频率电压转换电路21的输入和输出特性被调节以基本匹配给定的输入和输出特性。

43. 发明授权

US5699064A Oversampling D/A converter using a bidirectional shift register 失效
标题翻译：使用双向移位寄存器的过采样D / A转换器
公开(公告)号：US5699064A
公开(公告)日：1997-12-16
申请号：US509665
申请日：1995-07-31
申请人： Shiro Sakiyama , Shiro Dosho , Masakatsu Maruyama , George Hayashi , Seizo Inagaki , Akira Matsuzawa
发明人： Shiro Sakiyama , Shiro Dosho , Masakatsu Maruyama , George Hayashi , Seizo Inagaki , Akira Matsuzawa
IPC分类号： H03M3/04 , H03M1/78
CPC分类号： H03M3/376 , H03M3/50
摘要： In an interpolative modulator, a signal which varies by only .+-.1 with one clock from a 1-bit quantizer is used as a shift-direction control signal. The shift-direction control signal is given to a bidirectional shift register. The bidirectional shift register shifts data based on the value of the shift-direction control signal that has been received. The output from the bidirectional shift register is given as a control signal to a resistive-ladder-type D/A converter. The resistive-ladder-type D/A converter outputs an analog potential corresponding to a switch selected by the above control signal. Therefore, if a delay difference occurs between any two bits, two adjacent switches are simply selected simultaneously, so that the output from the resistive-ladder-type D/A converter varies continuously. Consequently, there can be provided an oversampling D/A converter of resistive-ladder type with high accuracy and an increased yield, which is free from glitch (transiently generated noise).
摘要翻译：在内插调制器中，使用从1比特量化器的一个时钟仅变化+/- 1的信号作为移位方向控制信号。移位方向控制信号被提供给双向移位寄存器。双向移位寄存器基于接收到的移位方向控制信号的值来移位数据。来自双向移位寄存器的输出作为电阻梯型D / A转换器的控制信号给出。电阻梯型D / A转换器输出与由上述控制信号选择的开关相对应的模拟电位。因此，如果任意两位之间发生延迟差，则两个相邻的开关被简单地同时选择，使得电阻梯型D / A转换器的输出连续变化。因此，可以提供具有高精度和增加的产量的电梯梯型的过采样D / A转换器，其没有毛刺（瞬时产生的噪声）。

44. 发明申请

US20070096961A1 Signal processing device 审中-公开
标题翻译：信号处理装置
公开(公告)号：US20070096961A1
公开(公告)日：2007-05-03
申请号：US10580842
申请日：2004-10-14
申请人： Shiro Sakiyama , Masayoshi Kinoshita , Shiro Dosho
发明人： Shiro Sakiyama , Masayoshi Kinoshita , Shiro Dosho
IPC分类号： H03M7/30
CPC分类号： G10L21/04
摘要： In a signal processing device which performs data compression, a thinning circuit 1 generates thinned data by thinning input PCM data. For example, when a sampling rate fs of the PCM data (original data) is fs=10 Hz, thinned data of fs=1 Hz is generated. The determination circuit 2 controls the selection circuit 4 so that, based on the following expression: TOTAL1=|X(n)−X(n−1)|+|X(n−1)−X(n−2)|+ . . . +|X(n−8)−X(n−9)| if TOTAL1>C1, the input PCM data is selected, and if otherwise the thinned data is selected. The selected data and the determination result information of the determination circuit 2 are written into a memory 3. Therefore, data compression is performed with respect to original data with a simple circuit configuration and without losing required information of the original data.
摘要翻译：在执行数据压缩的信号处理装置中，细化电路1通过稀释输入PCM数据来生成稀疏数据。例如，当PCM数据（原始数据）的采样率fs为fs = 10Hz时，产生fs = 1Hz的稀疏数据。确定电路2控制选择电路4，使得基于以下表达式：<？in-line-formula description =“In-line formula”end =“lead”？> TOTAL1 = | X（n）-X（ n-1）| + | X（n-1）-X（n-2）| +。。。 + | X（n-8）-X（n-9）| <？in-line-formula description =“内联公式”end =“tail”？>如果TOTAL 1> C 1，输入的PCM数据选择，如果否则选择了稀疏数据。所选择的数据和确定电路2的确定结果信息被写入存储器3。因此，利用简单的电路配置对原始数据执行数据压缩，并且不丢失原始数据的所需信息。

45. 发明授权

US07498865B2 Semiconductor integrated circuit with reduced speed variations 有权
标题翻译：半导体集成电路具有降低的速度变化
公开(公告)号：US07498865B2
公开(公告)日：2009-03-03
申请号：US10511165
申请日：2004-02-19
申请人： Shiro Sakiyama , Masayoshi Kinoshita , Masaya Sumita
发明人： Shiro Sakiyama , Masayoshi Kinoshita , Masaya Sumita
IPC分类号： H03K3/01
CPC分类号： G05F1/565 , H03K19/00384
摘要： In a semiconductor integrated circuit of the present invention, the main circuit 2 includes MOS transistors in which the source and the substrate are separated from each other. The substrate potential control circuit 1 controls the substrate potential of the MOS transistors of the main circuit 2 so that the actual saturation current value of the MOS transistors of the main circuit 2 is equal to the target saturation current value Ids under the operating power supply voltage Vdd of the main circuit 2. Therefore, it is possible to suppress variations in the operation speed even if the operating power supply voltage of the semiconductor integrated circuit is reduced.
摘要翻译：在本发明的半导体集成电路中，主电路2包括源极和基板彼此分离的MOS晶体管。基板电位控制电路1控制主电路2的MOS晶体管的基板电位，使得主电路2的MOS晶体管的实际饱和电流值等于工作电源电压下的目标饱和电流值Ids Vdd。因此，即使半导体集成电路的工作电源电压降低，也可以抑制操作速度的变化。

46. 发明授权

US06686782B2 Power supply voltage detection circuit 有权
标题翻译：电源电压检测电路
公开(公告)号：US06686782B2
公开(公告)日：2004-02-03
申请号：US10053552
申请日：2002-01-24
申请人： Masayoshi Kinoshita , Jun Kajiwara , Shiro Sakiyama
发明人： Masayoshi Kinoshita , Jun Kajiwara , Shiro Sakiyama
IPC分类号： H03K1722
CPC分类号： G01R19/16538 , H03K17/223
摘要： A power supply voltage detection circuit includes a voltage division circuit for linearly dividing a power supply voltage, a reference voltage circuit for providing a reference voltage, and a comparison circuit for comparing the output voltage from the voltage division circuit and the reference voltage from the reference voltage circuit. The power supply voltage detection circuit outputs a signal upon detecting that the power supply voltage is equal to or higher than the reference voltage. A PMOS transistor is provided between the voltage division circuit and the comparison circuit. The PMOS transistor includes a source terminal connected to an output terminal of the voltage division circuit, a drain terminal connected to an input terminal of the comparison circuit, and a gate terminal connected to the ground. Until the output voltage from the comparison circuit is higher than the threshold voltage of the PMOS transistor, the PMOS transistor remains OFF, thereby canceling the input of the output voltage signal from the voltage division circuit to the comparison circuit. Thus, without using external components, the signal is prevented from being erroneously output due to the output voltage from the voltage division circuit rising over, without crossing, the reference voltage from the reference voltage circuit during a sharp rise of the power supply voltage.
摘要翻译：电源电压检测电路包括用于线性分割电源电压的分压电路，用于提供参考电压的参考电压电路和用于比较来自分压电路的输出电压和参考电压的参考电压的比较电路电压电路。电源电压检测电路在检测到电源电压等于或高于参考电压时输出信号。在分压电路和比较电路之间设置PMOS晶体管。 PMOS晶体管包括连接到分压电路的输出端的源极端子，连接到比较电路的输入端子的漏极端子和连接到地的栅极端子。在比较电路的输出电压高于PMOS晶体管的阈值电压之前，PMOS晶体管保持截止状态，从而消除从分压电路到比较电路的输出电压信号的输入。因此，在不使用外部部件的情况下，由于来自分压电路的输出电压在电源电压的急剧上升期间不与基准电压电路交叉而不会交叉，所以不会错误地输出信号。

47. 发明授权

US06531856B2 Power source system for reducing power consumption in an intermittent mode of operation 失效
标题翻译：电源系统，用于在间歇运行模式下降低功耗
公开(公告)号：US06531856B2
公开(公告)日：2003-03-11
申请号：US09920670
申请日：2001-08-03
申请人： Shiro Sakiyama , Jun Kajiwara , Masayoshi Kinoshita
发明人： Shiro Sakiyama , Jun Kajiwara , Masayoshi Kinoshita
IPC分类号： G05F140
CPC分类号： H02M1/15 , H02J7/345
摘要： During an intermittent operation mode, a switch is normally opened and a capacitor with a large capacitance is isolated from a circuit. Under this condition, a power source voltage is intermittently supplied to a driven device. Since a charge/discharge current of the capacitor during the intermittent operation mode is limited to the charge/discharge current of the capacitor with a small capacitance, the power consumption can be lowered. In addition, since no switch exists in the current path from a power source voltage conversion circuit to the driven device, there is no drop, due to a switch, in the voltage supplied from the power source voltage conversion circuit to the driven device. On the other hand, during a continuous operation mode in which power source voltage is continuously provided to the driven device, the switch is normally closed and a capacitor with a large capacitance is connected to the power source system. Then the noise level in the supplied power is lowered.
摘要翻译：在间歇操作模式期间，开关通常被打开，并且具有大电容的电容器与电路隔离。在这种情况下，电源电压被间歇地供给到被驱动装置。由于在间歇操作模式期间电容器的充电/放电电流被限制为具有小电容的电容器的充电/放电电流，所以可以降低功耗。此外，由于在从电源电压转换电路到被驱动装置的电流路径中不存在开关，因此从电源电压转换电路向被驱动装置提供的电压不会由于开关而下降。另一方面，在向被驱动装置连续提供电源电压的连续运转模式中，开关常闭，电容器电容器与电源系统连接。然后降低供电电源中的噪声电平。

48. 发明授权

US06490715B1 Cell library database and design aiding system 有权
标题翻译：细胞库数据库和设计辅助系统
公开(公告)号：US06490715B1
公开(公告)日：2002-12-03
申请号：US09550352
申请日：2000-04-14
申请人： Toshiyuki Moriwaki , Shiro Sakiyama , Hiroo Yamamoto , Jun Kajiwara , Masayoshi Kinoshita
发明人： Toshiyuki Moriwaki , Shiro Sakiyama , Hiroo Yamamoto , Jun Kajiwara , Masayoshi Kinoshita
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A cell library database includes function information of standard cells which are basic circuits forming a logical device, each of the standard cell comprising at least one of power supply terminal as logical terminals, the function information of the standard cell containing logical information or delay information of the power supply terminal relative to an output terminal, or function information of macro cells which are functional circuits forming a logical device, each of the macro cell comprising at least one of power supply terminals as logical terminals, the function information of the macro cell containing logical information or delay information of said power supply terminals relative to an output terminal. A design aiding system uses the cell library database to execute logical simulation, etc.
摘要翻译：单元库数据库包括作为形成逻辑装置的基本电路的标准单元的功能信息，标准单元中的每一个包括作为逻辑端的电源端子中的至少一个，包含逻辑信息或延迟信息的标准单元的功能信息所述电源端子相对于输出端子，或作为形成逻辑装置的功能电路的宏电池的功能信息，所述宏电池单元包括作为逻辑端子的电源端子中的至少一个，所述宏单元的功能信息包含所述电源端子相对于输出端子的逻辑信息或延迟信息。设计辅助系统使用单元库数据库执行逻辑仿真等。

49. 发明授权

US5452402A Neural network circuit for adaptively controlling the coupling of neurons 失效
标题翻译：用于自适应控制神经元耦合的神经网络电路
公开(公告)号：US5452402A
公开(公告)日：1995-09-19
申请号：US155865
申请日：1993-11-23
申请人： Shiro Sakiyama , Masakatsu Maruyama , Hiroyuki Nakahira , Toshiyuki Kouda , Susumu Maruno
发明人： Shiro Sakiyama , Masakatsu Maruyama , Hiroyuki Nakahira , Toshiyuki Kouda , Susumu Maruno
IPC分类号： G06F15/18 , G06N3/04 , G06N3/08 , G06N99/00 , G06T7/00 , G06F15/00
CPC分类号： G06K9/62 , G06N3/08 , G06N3/082
摘要： In a multi-layered neural network circuit provided with an input layer having input vectors, an intermediate layer having networks in tree-like structure whose outputs are necessarily determined by the values of the input vectors and whose number corresponds to the number of the input vectors of the input layer, and an output layer having plural output units for integrating all outputs of the intermediate layer, provided are learning-time memories for memorizing the numbers of times at learning in paths between the intermediate layer and the respective output units, threshold processing circuits for threshold-processing the outputs of the leaning-time memories, and connection control circuits to be controlled by the outputs of the threshold processing circuits for controlling connection of paths between the intermediate layer and the output units. The outputs of the intermediate layer connected by the connection control circuits are summed in each output unit. Thus, the neural network circuit for recognizing an image or the like can execute recognition and learning of data to be recognized at high speed with small circuit size, and the recognition accuracy for unlearned data is high.
摘要翻译：在设置有具有输入向量的输入层的多层神经网络电路中，具有树状结构的网络的中间层，其输出必须由输入向量的值决定，其数量对应于输入向量的数量以及输出层，具有用于积分中间层的所有输出的多个输出单元，所述输出层是用于存储中间层和各个输出单元之间的路径中学习次数的学习时间存储器，阈值处理用于对倾斜时间存储器的输出进行阈值处理的电路和由用于控制中间层和输出单元之间的路径连接的阈值处理电路的输出来控制的连接控制电路。由连接控制电路连接的中间层的输出在每个输出单元中相加。因此，用于识别图像等的神经网络电路可以以较小的电路尺寸执行高速识别的数据的识别和学习，并且未被读取的数据的识别精度高。

50. 发明授权

US07257801B2 Cell library database and timing verification and withstand voltage verification systems for integrated circuit using the same 有权
标题翻译：电池库数据库和定时验证和耐压验证系统的集成电路使用相同
公开(公告)号：US07257801B2
公开(公告)日：2007-08-14
申请号：US10630803
申请日：2003-07-31
申请人： Shiro Sakiyama , Kouji Mochizuki
发明人： Shiro Sakiyama , Kouji Mochizuki
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： In a cell library database, timing verification is conducted on an LSI which exists in a variable power supply system capable of changing the source voltage arbitrarily and which includes logic delay information associated with a plurality of source voltages. The database is configured, for example, so that the voltage information V of the source is represented in multiple bits V [1:0] and delay times Alh (Vlh) to Bhl (Vhh) between the time input signals A and B are each changed and the time the output signal Y changes are described for respective pieces of source voltage information LH (1.2 V), HL (1.5 V) and HH (1.8 V). This allows timing verification in the variable source system which operates with the source voltage changed dynamically.
摘要翻译：在单元库数据库中，对存在于能够任意地改变源极电压的可变电源系统中的LSI进行定时验证，其中包括与多个源极电压相关联的逻辑延迟信息。数据库例如被配置为使得源的电压信息V以多位V [1：0]表示，时间输入信号A和B之间的延迟时间Alh（Vhh）至Bhl（Vhh）分别为对于各个源电压信息LH（1.2V），HL（1.5V）和HH（1.8V）描述输出信号Y改变的时间。这允许在源电压动态改变的可变源系统中进行定时验证。

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