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41. 发明授权

US07297564B1 Fabrication of vertical sidewalls on (110) silicon substrates for use in Si/SiGe photodetectors 有权
标题翻译：在Si / SiGe光电探测器中用于（110）硅衬底上的垂直侧壁的制造
公开(公告)号：US07297564B1
公开(公告)日：2007-11-20
申请号：US11416985
申请日：2006-05-02
申请人： Douglas J. Tweet , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
发明人： Douglas J. Tweet , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L31/1812 , Y02E10/50
摘要： A method of fabricating vertical sidewalls on silicon (110) substrates for use in Si/SiGe photodetectors includes preparing a silicon (110) layer wherein the silicon (110) plane is parallel to an underlying silicon wafer surface. Masking the silicon (110) layer with mask sidewalls parallel to a silicon (111) layer plane and etching the silicon (110) layer to remove an un-masked portion thereof, leaving a patterned silicon (110) layer having vertical silicon (111) sidewalls. Removing the mask; growing SiGe-containing layers on the patterned silicon (110) layer; and fabricating a photodetector.
摘要翻译：在Si / SiGe光电探测器中使用的在硅（110）衬底上制造垂直侧壁的方法包括制备硅（110）层，其中硅（110）平面平行于下面的硅晶片表面。屏蔽具有平行于硅（111）层平面的掩模侧壁的硅（110）层并蚀刻硅（110）层以去除其未掩蔽部分，留下具有垂直硅（111）的图案化硅（110）层，侧壁取下面罩; 在图案化的硅（110）层上生长含SiGe的层; 并制造光电检测器。

42. 发明授权

US07157300B2 Fabrication of thin film germanium infrared sensor by bonding to silicon wafer 有权
标题翻译：通过粘合到硅晶片制造薄膜锗红外传感器
公开(公告)号：US07157300B2
公开(公告)日：2007-01-02
申请号：US10993533
申请日：2004-11-19
申请人： Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu , Douglas J. Tweet
发明人： Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu , Douglas J. Tweet
IPC分类号： H01L21/00
CPC分类号： H01L31/1804 , H01L21/187 , H01L21/76254 , H01L27/1443 , H01L31/02327 , H01L31/105 , Y02E10/547 , Y02P70/521
摘要： A method of fabricating a thin film germanium photodetector includes preparing a silicon substrate; fabricating a CMOS device on the silicon substrate; preparing a germanium substrate; preparing surfaces of each substrate for bonding; bonding the germanium substrate to the CMOS-bearing silicon substrate to form a bonded structure; removing a portion of the germanium substrate from the bonded structure; forming a PIN diode in the germanium substrate; removing a portion of the germanium layer by etching; and completing the germanium photo detector.
摘要翻译：制造薄膜锗光电探测器的方法包括制备硅衬底; 在硅衬底上制造CMOS器件; 制备锗衬底; 准备每个基板的表面以进行接合; 将锗衬底结合到具有CMOS的硅衬底以形成结合结构; 从结合结构去除锗衬底的一部分; 在锗衬底中形成PIN二极管; 通过蚀刻去除锗层的一部分; 并完成锗光电检测器。

43. 发明授权

US07115945B2 Strained silicon fin structure 有权
公开(公告)号：US07115945B2
公开(公告)日：2006-10-03
申请号：US11327092
申请日：2006-01-06
申请人： Jong-Jan Lee , Sheng Teng Hsu , Douglas J. Tweet , Jer-Shen Maa
发明人： Jong-Jan Lee , Sheng Teng Hsu , Douglas J. Tweet , Jer-Shen Maa
IPC分类号： H01L29/786
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/66795 , H01L29/78687
摘要： Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.

44. 发明授权

US07067430B2 Method of making relaxed silicon-germanium on insulator via layer transfer with stress reduction 失效
标题翻译：通过层压转移在绝缘体上制备松弛硅锗的方法
公开(公告)号：US07067430B2
公开(公告)日：2006-06-27
申请号：US10677005
申请日：2003-09-30
申请人： Jer-Shen Maa , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jer-Shen Maa , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L21/302
CPC分类号： H01L21/76254
摘要： A method of forming a silicon-germanium layer on an insulator includes depositing a layer of silicon-germanium on a silicon substrate to form a silicon/silicon-germanium portion; implanting hydrogen ions into the silicon substrate between about 500 Å to 1 μm below a silicon-germanium/silicon interface; bonding the silicon/silicon-germanium portion to an insulator substrate to form a couplet; thermally annealing the couplet in a first thermal annealing step to split the couplet; patterning and etching the silicon-germanium-on-insulator portion to remove portions of the silicon and SiGe layers; etching the silicon-germanium-on-insulator portion to remove the remaining silicon layer; thermally annealing the silicon-germanium-on-insulator portion in a second annealing step to relaxed the SiGe layer; and depositing a layer of strained silicon about the SiGe layer.
摘要翻译：在绝缘体上形成硅 - 锗层的方法包括在硅衬底上沉积硅 - 锗层以形成硅/硅 - 锗部分; 在硅 - 锗/硅界面之下的约500埃至1微米处将氢离子注入到硅衬底中; 将硅/硅锗部分接合到绝缘体基板上以形成对联体; 在第一热退火步骤中对联接件进行热退火以分离联接件; 图案化和蚀刻绝缘体上硅部分以去除部分硅和SiGe层; 蚀刻绝缘体上硅部分以除去剩余的硅层; 在第二退火步骤中对绝缘体上硅部分进行热退火以松弛SiGe层; 以及在SiGe层周围沉积一层应变硅。

45. 发明授权

US07045832B2 Vertical optical path structure for infrared photodetection 有权
标题翻译：用于红外光电检测的垂直光路结构
公开(公告)号：US07045832B2
公开(公告)日：2006-05-16
申请号：US10755567
申请日：2004-01-12
申请人： Douglas J. Tweet , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
发明人： Douglas J. Tweet , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L29/732 , G01J5/20
CPC分类号： H01L31/105 , H01L21/02381 , H01L21/0243 , H01L21/0245 , H01L21/02532 , H01L21/02639 , H01L27/14627 , H01L27/14643 , H01L31/02327 , H01L31/028 , H01L31/035281 , H01L31/108 , H01L31/109 , H01L31/1812 , Y02E10/547
摘要： Provided are a SiGe vertical optical path and a method for selectively forming a SiGe optical path normal structure for IR photodetection. The method comprises: forming a Si substrate surface; forming a Si feature, normal with respect to the Si substrate surface, such as a trench, via, or pillar; and, selectively forming a SiGe optical path overlying the Si normal feature. In some aspects, the Si substrate surface is formed a first plane and the Si normal feature has walls (sidewalls), normal with respect to the Si substrate surface, and a surface in a second plane, parallel to the first plane. Then, selectively forming a SiGe optical path overlying the Si normal feature includes forming a SiGe vertical optical path overlying the normal feature walls.
摘要翻译：提供了SiGe垂直光路和用于选择性地形成用于IR光电检测的SiGe光路法线结构的方法。该方法包括：形成Si衬底表面; 形成Si特征，相对于诸如沟槽，通孔或支柱的Si衬底表面是正常的; 并且选择性地形成覆盖Si正常特征的SiGe光路。在一些方面，Si衬底表面形成第一平面，并且Si正常特征具有相对于Si衬底表面法线的壁（侧壁）和平行于第一平面的第二平面中的表面。然后，选择性地形成覆盖Si正常特征的SiGe光路包括形成覆盖正常特征壁的SiGe垂直光路。

46. 发明授权

US07045401B2 Strained silicon finFET device 有权
标题翻译：应变硅finFET器件
公开(公告)号：US07045401B2
公开(公告)日：2006-05-16
申请号：US10602436
申请日：2003-06-23
申请人： Jong-Jan Lee , Sheng Teng Hsu , Douglas J. Tweet , Jer-Shen Maa
发明人： Jong-Jan Lee , Sheng Teng Hsu , Douglas J. Tweet , Jer-Shen Maa
IPC分类号： H01L21/00 , H01L21/338
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/66795 , H01L29/78687
摘要： Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.
摘要翻译：公开了一种应变硅finFET器件，其具有双栅极finFET结构中的应变硅鳍通道。所公开的finFET器件是由用于抑制短沟道效应和增强驱动电流的自对准双栅极控制的硅鳍通道组成的双栅极MOSFET。所公开的finFET器件的硅鳍通道是应变硅鳍通道，包括沉积在具有不同晶格常数的种子鳍上的应变硅层，例如沉积在硅锗晶种鳍上的硅层或碳掺杂硅层沉积在硅种子翅片上。除了在finFET器件中固有的短沟道效应降低特性之外，硅层和种子鳍之间的晶格失配在所公开的finFET器件中产生应变硅鳍通道，以改善空穴和电子迁移率增强。

47. 发明授权

US06793731B2 Method for recrystallizing an amorphized silicon germanium film overlying silicon 失效
标题翻译：将硅非晶硅化硅膜再结晶的方法
公开(公告)号：US06793731B2
公开(公告)日：2004-09-21
申请号：US10098757
申请日：2002-03-13
申请人： Sheng Teng Hsu , Jong-Jan Lee , Jer-shen Maa , Douglas J. Tweet
发明人： Sheng Teng Hsu , Jong-Jan Lee , Jer-shen Maa , Douglas J. Tweet
IPC分类号： C30B3302
CPC分类号： H01L21/26506 , C30B1/023 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/0251 , H01L21/02513 , H01L21/02532 , H01L21/02694
摘要： A method is provided for forming a relaxed single-crystal silicon germanium film on a silicon substrate. Also provided is a film structure with a relaxed layer of graded silicon germanium on a silicon substrate. The method comprises: providing a silicon (Si) substrate with a top surface; growing a graded layer of strained single-crystal Si1−xGex having a bottom surface overlying the Si substrate top surface and a top surface, where x increases with the Si1−xGex layer thickness in the range between 0.03 and 0.5, wherein the Si1−xGex layer has a thickness in the range of 2500 Å to 5000 Å; implanting hydrogen ions; penetrating the Si substrate with the hydrogen ions a depth in the range of 300 Å to 1000 Å; implanting heavy ions, such as Si or Ge, into the Si1−xGex; in response to the heavy ion implantation, amorphizing a first region of the Si1−xGex layer adjacent the Si substrate; annealing; in response to the annealing, forming a hydrogen platelets layer between the Si substrate and the Si1−xGex layer; forming a silicon layer with a high density of hydrogen underlying the hydrogen platelets layer; and, forming a relaxed single-crystal Si1−xGex region, free of defects.
摘要翻译：提供了一种在硅衬底上形成松弛的单晶硅锗膜的方法。还提供了在硅衬底上具有缓和的渐变硅锗层的膜结构。该方法包括：提供具有顶表面的硅（Si）衬底; 生长具有覆盖Si衬底顶表面的底表面和顶表面的应变单晶Si1-xGex的分级层，其中x随着Si1-xGex层厚度在0.03和0.5之间的范围增加，其中Si1-xGex 层的厚度在2500埃至5000埃的范围内; 植入氢离子; 用氢离子穿透Si衬底，深度在300埃至1000埃的范围内; 将诸如Si或Ge的重离子注入到Si1-xGex中; 响应于重离子注入，使与Si衬底相邻的Si1-xGex层的第一区域非晶化; 退火; 响应于退火，在Si衬底和Si1-xGex层之间形成氢血小板层; 在氢薄膜层下形成具有高密度氢的硅层; 并形成松弛的单晶Si1-xGex区域，没有缺陷。

48. 发明授权

US06583000B1 Process integration of Si1-xGex CMOS with Si1-xGex relaxation after STI formation 失效
标题翻译： STI形成后Si1-xGex CMOS与Si1-xGex弛豫过程的整合
公开(公告)号：US06583000B1
公开(公告)日：2003-06-24
申请号：US10072183
申请日：2002-02-07
申请人： Sheng Teng Hsu , Jong-Jan Lee , Jer-shen Maa , Douglas James Tweet
发明人： Sheng Teng Hsu , Jong-Jan Lee , Jer-shen Maa , Douglas James Tweet
IPC分类号： H01L218238
CPC分类号： H01L21/823807 , H01L21/76224 , H01L21/823878
摘要： A method of forming a CMOS device includes preparing a silicon substrate, including forming plural device regions on the substrate; epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40%; forming a silicon cap layer epitaxially on the SiGe layer; depositing a gate oxide layer; depositing a first polysilicon layer; implanting H+ ions to a depth below the SiGe layer; forming a trench by shallow trench isolation which extends into the substrate; annealing the structure at a temperature of between about 700° C. to 900° C. for between about five minutes to sixty minutes; depositing an oxide layer and a second polysilicon layer, thereby filling the trench; planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench; and completing the CMOS device.
摘要翻译：形成CMOS器件的方法包括制备硅衬底，包括在衬底上形成多个器件区域; 在衬底上外延地形成应变SiGe层，其中SiGe层的锗含量在约20％和40％之间; 在SiGe层上外延地形成硅帽层; 沉积栅氧化层; 沉积第一多晶硅层; 将H +离子注入SiGe层以下的深度; 通过延伸到衬底中的浅沟槽隔离形成沟槽; 在约700℃至900℃的温度下退火结构约5分钟至60分钟; 沉积氧化物层和第二多晶硅层，从而填充沟槽; 将结构平面化到位于沟槽中的第二多晶硅层的部分的顶部的顶部; 并完成CMOS设备。

49. 发明授权

US07378309B2 Method of fabricating local interconnects on a silicon-germanium 3D CMOS 有权
标题翻译：在硅 - 锗3D CMOS上制造局部互连的方法
公开(公告)号：US07378309B2
公开(公告)日：2008-05-27
申请号：US11376542
申请日：2006-03-15
申请人： Jong-Jan Lee , Paul J. Schuele , Sheng Teng Hsu , Jer-Shen Maa
发明人： Jong-Jan Lee , Paul J. Schuele , Sheng Teng Hsu , Jer-Shen Maa
IPC分类号： H01L21/8234
CPC分类号： H01L21/823871 , H01L21/02532 , H01L21/02667 , H01L21/28525 , H01L21/76895 , H01L27/11 , H01L27/1108
摘要： A method of fabricating local interconnect on a silicon-germanium 3D CMOS includes fabricating an active silicon CMOS device on a silicon substrate. An insulator layer is deposited on the silicon substrate and a seed window is opened through the insulator layer to the silicon substrate and to a silicon CMOS device gate. A germanium thin film is deposited on the insulator layer and into windows, forming a contact between the germanium thin film and the silicon device. The germanium thin film is encapsulated in a dielectric material. The wafer is heated at a temperature sufficient to flow the germanium, while maintaining the other layers in a solid condition. The wafer is cooled to solidify the germanium as single crystal germanium and as polycrystalline germanium, which provides local interconnects. Germanium CMOS devices may be fabricated on the single crystal germanium thin film.
摘要翻译：在硅 - 锗3D CMOS上制造局部互连的方法包括在硅衬底上制造有源硅CMOS器件。绝缘体层沉积在硅衬底上，并且晶种窗通过绝缘体层向硅衬底和硅CMOS器件栅极打开。在绝缘体层和窗口上沉积锗薄膜，形成锗薄膜和硅器件之间的接触。锗薄膜被封装在电介质材料中。在足以使锗流动的温度下加热晶片，同时将其它层保持在固体状态。将晶片冷却以将锗固化为单晶锗和作为多晶锗，其提供局部互连。可以在单晶锗薄膜上制造锗CMOS器件。

50. 发明授权

US07226504B2 Method to form thick relaxed SiGe layer with trench structure 失效
标题翻译：形成具有沟槽结构的厚松弛SiGe层的方法
公开(公告)号：US07226504B2
公开(公告)日：2007-06-05
申请号：US10062336
申请日：2002-01-31
申请人： Jer-Shen Maa , Douglas James Tweet , Tingkai Li , Jong-Jan Lee , Sheng Teng Hsu
发明人： Jer-Shen Maa , Douglas James Tweet , Tingkai Li , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： C30B33/02
CPC分类号： H01L21/3247 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02694 , H01L21/324
摘要： A method of forming a SiGe layer having a relatively high germanium content and a relatively low threading dislocation density includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the germanium content of the SiGe layer is greater than 20%, by atomic ratio; implanting H+ ions into the SiGe layer at a dose of between about 1·1016 cm−2 to 5·1016 cm−2, at an energy of between about 20 keV to 45 keV; patterning the SiGe layer with photoresist; plasma etching the structure to form trenches about regions; removing the photoresist; and thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 950° C. for between about 30 seconds and 30 minutes.
摘要翻译：形成具有较高锗含量和较低穿透位错密度的SiGe层的方法包括制备硅衬底; 将SiGe层沉积至约100nm至500nm的厚度，其中SiGe层的锗含量按原子比大于20％; 将H +离子以约1.10×16cm -2至0.0010±0.2cm的剂量注入SiGe层中， SUP>，在约20keV至45keV之间的能量; 用光致抗蚀剂图案化SiGe层; 等离子体蚀刻结构以形成关于区域的沟槽; 去除光致抗蚀剂; 以及对基板和SiGe层进行热退火，以在惰性气氛中在约650℃至950℃的温度下放置SiGe层约30秒至30分钟。

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