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41. 发明申请

US20090161447A1 SEMICONDUCTOR MEMORY INPUT/OUTPUT DEVICE 有权
标题翻译：半导体存储器输入/输出设备
公开(公告)号：US20090161447A1
公开(公告)日：2009-06-25
申请号：US12339389
申请日：2008-12-19
申请人： Sung-Joo Ha , Ho-Youb Cho
发明人： Sung-Joo Ha , Ho-Youb Cho
IPC分类号： G11C7/10
CPC分类号： G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1078 , G11C7/1084 , G11C7/1093 , G11C7/22
摘要： A semiconductor memory input/output device includes selection pads used to input and output signals for multiple operation modes and having multiple functions, a control signal generator for outputting setting signals and a mask control signal, a lower input/output unit including a lower output buffer for outputting a read data strobe signal to a selection pad and a lower input buffer for receiving a lower data mask signal from the selection pad, and selecting one operation of the lower output buffer and the lower input buffer, and an upper input/output unit including an upper output buffer for outputting an inverted read data strobe signal to the second selection pad and an upper input buffer for receiving an upper data mask signal from the second selection pad, and selecting one operation of the upper output buffer and the upper input buffer.
摘要翻译：半导体存储器输入/输出装置包括用于输入和输出用于多个操作模式的信号并具有多个功能的选择焊盘，用于输出设置信号的控制信号发生器和掩模控制信号，包括下部输出缓冲器用于将选择焊盘的读取数据选通信号输出到选择焊盘的下部数据屏蔽信号，以及选择下部输出缓冲器和下部输入缓冲器的一个动作，以及上部输入输出部包括用于向第二选择焊盘输出反转的读数据选通信号的上输出缓冲器和用于从第二选择焊盘接收上数据掩码信号的上输入缓冲器，以及选择上输出缓冲器和上输入缓冲器的一个操作。

42. 发明申请

US20090147597A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090147597A1
公开(公告)日：2009-06-11
申请号：US12366357
申请日：2009-02-05
申请人： Ho-Youb Cho
发明人： Ho-Youb Cho
IPC分类号： G11C7/00 , G11C8/08
CPC分类号： G11C7/1078 , G11C7/1039 , G11C7/1045 , G11C7/1087 , G11C7/1093 , G11C7/1096 , G11C2207/107
摘要： A first input buffer receives sequentially inputted first data. A first data selector selectively transfers the first data from the first input buffer in accordance with a data input mode. A first data alignment circuit aligns and outputs the data from the first data selector. A second input buffer receives sequentially inputted second data in accordance with the data input mode. A second data selector selectively transfers the data of the first input buffer or of the second input buffer, in accordance with the data input mode. A first data alignment circuit aligns and outputs the data from the second data selector.
摘要翻译：第一输入缓冲器接收顺序输入的第一数据。第一数据选择器根据数据输入模式选择性地传送来自第一输入缓冲器的第一数据。第一数据对准电路对准并输出来自第一数据选择器的数据。第二输入缓冲器根据数据输入模式接收顺序输入的第二数据。第二数据选择器根据数据输入模式选择性地传送第一输入缓冲器或第二输入缓冲器的数据。第一数据对准电路对准并输出来自第二数据选择器的数据。

43. 发明授权

US07502266B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07502266B2
公开(公告)日：2009-03-10
申请号：US11645987
申请日：2006-12-27
申请人： Ho-Youb Cho
发明人： Ho-Youb Cho
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1039 , G11C7/1045 , G11C7/1087 , G11C7/1093 , G11C7/1096 , G11C2207/107
摘要： A first input buffer receives sequentially inputted first data. A first data selector selectively transfers the first data from the first input buffer in accordance with a data input mode. A first data alignment circuit aligns and outputs the data from the first data selector. A second input buffer receives sequentially inputted second data in accordance with the data input mode. A second data selector selectively transfers the data of the first input buffer or of the second input buffer, in accordance with the data input mode. A first data alignment circuit aligns and outputs the data from the second data selector.
摘要翻译：第一输入缓冲器接收顺序输入的第一数据。第一数据选择器根据数据输入模式选择性地传送来自第一输入缓冲器的第一数据。第一数据对准电路对准并输出来自第一数据选择器的数据。第二输入缓冲器根据数据输入模式接收顺序输入的第二数据。第二数据选择器根据数据输入模式选择性地传送第一输入缓冲器或第二输入缓冲器的数据。第一数据对准电路对准并输出来自第二数据选择器的数据。

44. 发明申请

US20080285373A1 ADDRESS RECEIVING CIRCUIT FOR A SEMICONDUCTOR APPARATUS 有权
标题翻译：地址接收电路用于半导体器件
公开(公告)号：US20080285373A1
公开(公告)日：2008-11-20
申请号：US11961963
申请日：2007-12-20
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C8/00 , G11C8/18
CPC分类号： G11C8/06
摘要： An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal.
摘要翻译：一种用于半导体装置的地址接收电路包括控制器，响应于半导体装置初始化命令，产生具有对应于半导体装置初始化命令的周期时间标准的激活周期的控制信号，以及地址缓冲器，根据控制信号接收地址。

45. 发明授权

US07450440B2 Circuit for initializing a pipe latch unit in a semiconductor memory device 有权
标题翻译：用于在半导体存储器件中初始化管道锁存单元的电路
公开(公告)号：US07450440B2
公开(公告)日：2008-11-11
申请号：US11478123
申请日：2006-06-30
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C7/00
CPC分类号： G11C7/20 , G11C7/1039
摘要： A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches for latching data. An input controller controls input timing of data transmitted from data line to the pipe latch unit. An output controller controls output timing of data latched in the pipe latch unit. An initialization controller controls the input controller and the output controller to thereby initialize the pipe latch unit in response to a read/write flag signal which is activated during a write operation.
摘要翻译：一种半导体存储器件包括具有用于锁存数据的多个管道锁存器的管道锁存单元。输入控制器控制从数据线发送到管道锁存单元的数据的输入定时。输出控制器控制锁存在管道锁存单元中的数据的输出定时。初始化控制器控制输入控制器和输出控制器，从而响应于在写操作期间被激活的读/写标志信号来初始化管锁存单元。

46. 发明申请

US20080240327A1 Semiconductor memory device capable of controlling tAC timing and method for operating the same 失效
标题翻译：能够控制tAC定时的半导体存储器件及其操作方法
公开(公告)号：US20080240327A1
公开(公告)日：2008-10-02
申请号：US12003549
申请日：2007-12-28
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： H03D3/24
CPC分类号： G11C16/32 , H03L7/0812
摘要： A semiconductor memory device is capable of controlling a tAC with a timing margin in an output data process. The semiconductor memory device includes a delay locked loop circuit, a tAC control unit, a reference signal generating unit, and a data output block. The delay locked loop circuit produces delay locked clock signals through a delay locking operation. The tAC control unit adjusts a delay value of the delay locked clock signals in order to control a tAC timing, thereby generating output reference signals. The reference signal generating unit produces a latch reference signal in response to the delay locked clock signals. The data output block latches data in response to the latch reference signal and for outputting the latched data in response to the output reference signals.
摘要翻译：半导体存储器件能够在输出数据处理中以定时裕度来控制tAC。半导体存储器件包括延迟锁定环电路，tAC控制单元，参考信号生成单元和数据输出块。延迟锁定环电路通过延迟锁定操作产生延迟锁定时钟信号。 tAC控制单元调整延迟锁定时钟信号的延迟值，以便控制tAC定时，从而产生输出参考信号。参考信号产生单元响应于延迟锁定时钟信号产生锁存参考信号。数据输出块根据锁存参考信号锁存数据，并根据输出参考信号输出锁存数据。

47. 发明申请

US20080205186A1 Semiconductor memory device and method for driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20080205186A1
公开(公告)日：2008-08-28
申请号：US11987832
申请日：2007-12-05
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C8/06 , G11C8/10
CPC分类号： G11C8/06 , G11C7/22 , G11C7/222
摘要： A semiconductor memory device includes a pulse signal generator configured to combine a plurality of external command signals to generate a normal register control signal and an extended register control signal in response to a clock signal; a reset signal generator configured to receive operating information of a delay locked loop (DLL) circuit from an outside to generate a reset signal for a reset operation of the DLL circuit in response to the normal register control signal or the extended register control signal; and the DLL circuit configured to perform a reset operation in response to the reset signal
摘要翻译：半导体存储器件包括：脉冲信号发生器，被配置为组合多个外部命令信号以响应于时钟信号产生正常寄存器控制信号和扩展寄存器控制信号; 复位信号发生器，被配置为响应于所述正常寄存器控制信号或所述扩展寄存器控制信号，从外部接收延迟锁定环路（DLL）电路的操作信息以产生用于所述DLL电路的复位操作的复位信号; 以及DLL电路，被配置为响应于复位信号执行复位操作

48. 发明授权

US07099209B2 Semiconductor memory device having repair circuit 失效
标题翻译：具有修复电路的半导体存储器件
公开(公告)号：US07099209B2
公开(公告)日：2006-08-29
申请号：US11015419
申请日：2004-12-20
申请人： Sang-Hee Kang , Sung-Joo Ha , Ho-Youb Cho
发明人： Sang-Hee Kang , Sung-Joo Ha , Ho-Youb Cho
IPC分类号： G11C7/00
CPC分类号： G11C29/808
摘要： A semiconductor memory device, including: a plurality of banks each of which includes a plurality of memory cells, a plurality of redundancy memory cells for replacing a defective memory cell and a repair circuit, having a plurality of fuse sets, for substituting an address to thereby access the redundancy memory cell instead of the defective memory cell; and a common repair circuit, having a plurality of fuse sets, for substituting the address in order to replace the defective memory cell with the redundancy memory cell included in any of the plurality of banks.
摘要翻译：一种半导体存储器件，包括：多个存储体，每个存储体包括多个存储单元，用于替换有缺陷存储单元的多个冗余存储单元和具有多个熔丝组的修复电路，用于将地址替换为从而访问冗余存储单元而不是有缺陷的存储单元; 以及具有多个熔丝组的通用修复电路，用于代替所述地址以便用所述多个存储体中的任一个中包含的所述冗余存储单元替换所述有缺陷的存储单元。

49. 发明授权

US06477094B2 Memory repair circuit using antifuse of MOS structure 有权
标题翻译：内存修复电路采用反熔丝MOS结构
公开(公告)号：US06477094B2
公开(公告)日：2002-11-05
申请号：US09737871
申请日：2000-12-18
申请人： Phil-Jung Kim , Jae-Kyung Wee , Chang-Hyuk Lee , Young-Ho Seol , Jin-Keun Oh , Ho-Youb Cho
发明人： Phil-Jung Kim , Jae-Kyung Wee , Chang-Hyuk Lee , Young-Ho Seol , Jin-Keun Oh , Ho-Youb Cho
IPC分类号： G11C700
CPC分类号： G11C29/785 , G11C17/18
摘要： A memory repair circuit uses an antifuse of MOS structure, capable of repairing defective cells by constructing the antifuse by MOS transistors and programming the antifuse circuit properly. The memory repair circuit comprises a plurality of antifuse devices, each programmed when a power voltage and a negative voltage are supplied respectively to a first electrode and a second electrode thereof; a latch for detecting and latching program states of the antifuse devices; and a redundancy block for replacing a defect cell with a redundancy cell depending on the output of the latch.
摘要翻译：存储器修复电路使用MOS结构的反熔丝，能够通过由MOS晶体管构成反熔丝并且适当地编程反熔丝电路来修复有缺陷的单元。存储器修复电路包括多个反熔断器件，每个反熔丝器件分别在将电源电压和负电压提供给第一电极和第二电极时被编程; 用于检测和锁存反熔丝装置的程序状态的锁存器; 以及用于根据锁存器的输出用冗余单元替换缺陷单元的冗余块。

50. 发明授权

US06456558B1 Column decoding apparatus for use in a semiconductor memory device 失效
公开(公告)号：US06456558B1
公开(公告)日：2002-09-24
申请号：US09895882
申请日：2001-06-29
申请人： Ho-Youb Cho
发明人： Ho-Youb Cho
IPC分类号： G11C800
CPC分类号： G11C8/10
摘要： A column decoding apparatus in a semiconductor memory device of the present invention is capable of improving the rise/fall time of a column selecting signal by reducing the number of load transistors of the column decoder by enabling the column selecting signal of a selected block. In a semiconductor memory device that has a plurality of memory cell arrays, bit line sense amplifier arrays and block controlling units, a column decoder, and column selecting transistors formed between the plurality of bit line sense amplifier arrays and a data line, a column decoding apparatus of the present invention includes column selecting signal generating units, each of which receives a control signal of the block controlling units and the output signal of the column decoder for generating a column selecting signal activated only within a selected block to drive the column selecting transistors.

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