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1. 发明授权

US07830731B2 Circuit for initializing a pipe latch unit in a semiconductor memory device 有权
标题翻译：用于在半导体存储器件中初始化管道锁存单元的电路
公开(公告)号：US07830731B2
公开(公告)日：2010-11-09
申请号：US12260298
申请日：2008-10-29
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C7/00
CPC分类号： G11C7/20 , G11C7/1039
摘要： A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches for latching data. An input controller controls input timing of data transmitted from data line to the pipe latch unit. An output controller controls output timing of data latched in the pipe latch unit. An initialization controller controls the input controller and the output controller to thereby initialize the pipe latch unit in response to a read/write flag signal which is activated during a write operation.
摘要翻译：一种半导体存储器件包括具有用于锁存数据的多个管道锁存器的管道锁存单元。输入控制器控制从数据线发送到管道锁存单元的数据的输入定时。输出控制器控制锁存在管道锁存单元中的数据的输出定时。初始化控制器控制输入控制器和输出控制器，从而响应于在写操作期间被激活的读/写标志信号来初始化管锁存单元。

2. 发明授权

US07755969B2 Address receiving circuit for a semiconductor apparatus 有权
标题翻译：半导体装置的地址接收电路
公开(公告)号：US07755969B2
公开(公告)日：2010-07-13
申请号：US11961963
申请日：2007-12-20
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C8/00
CPC分类号： G11C8/06
摘要： An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal.
摘要翻译：一种用于半导体装置的地址接收电路包括控制器，响应于半导体装置初始化命令，产生具有对应于半导体装置初始化命令的周期时间标准的激活周期的控制信号，以及地址缓冲器，根据控制信号接收地址。

3. 发明授权

US07652939B2 Semiconductor memory device and method for driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US07652939B2
公开(公告)日：2010-01-26
申请号：US11987832
申请日：2007-12-05
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C7/00
CPC分类号： G11C8/06 , G11C7/22 , G11C7/222
摘要： A semiconductor memory device includes a pulse signal generator configured to combine a plurality of external command signals to generate a normal register control signal and an extended register control signal in response to a clock signal; a reset signal generator configured to receive operating information of a delay locked loop (DLL) circuit from an outside to generate a reset signal for a reset operation of the DLL circuit in response to the normal register control signal or the extended register control signal; and the DLL circuit configured to perform a reset operation in response to the reset signal.
摘要翻译：半导体存储器件包括：脉冲信号发生器，被配置为组合多个外部命令信号以响应于时钟信号产生正常寄存器控制信号和扩展寄存器控制信号; 复位信号发生器，被配置为响应于所述正常寄存器控制信号或所述扩展寄存器控制信号，从外部接收延迟锁定环路（DLL）电路的操作信息以产生用于所述DLL电路的复位操作的复位信号; 以及DLL电路，被配置为响应于复位信号执行复位操作。

4. 发明申请

US20070070715A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070070715A1
公开(公告)日：2007-03-29
申请号：US11478123
申请日：2006-06-30
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C7/10
CPC分类号： G11C7/20 , G11C7/1039
摘要： A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches for latching data. An input controller controls input timing of data transmitted from data line to the pipe latch unit. An output controller controls output timing of data latched in the pipe latch unit. An initialization controller controls the input controller and the output controller to thereby initialize the pipe latch unit in response to a read/write flag signal which is activated during a write operation.
摘要翻译：一种半导体存储器件包括具有用于锁存数据的多个管道锁存器的管道锁存单元。输入控制器控制从数据线发送到管道锁存单元的数据的输入定时。输出控制器控制锁存在管道锁存单元中的数据的输出定时。初始化控制器控制输入控制器和输出控制器，从而响应于在写操作期间被激活的读/写标志信号来初始化管锁存单元。

5. 发明授权

US07715253B2 Semiconductor memory device and method for operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US07715253B2
公开(公告)日：2010-05-11
申请号：US12164984
申请日：2008-06-30
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1072 , G11C7/222 , G11C29/022 , G11C29/023
摘要： Semiconductor memory device and method for operating the same comprise an auxiliary driver configured to output an internal strobe signals generated corresponding to a read command as a plurality of auxiliary strobe signal in response to a control signal, wherein the auxiliary driver bypass a first output auxiliary strobe signal, and delay to output the rest of the auxiliary strobe signal among the outputted auxiliary strobe signal and a strobe signal generator for driving the auxiliary strobe signal to output the delayed auxiliary strobe signal as a data strobe signals.
摘要翻译：半导体存储器件及其操作方法包括：辅助驱动器，被配置为响应于控制信号输出与读命令相对应的内部选通信号作为多个辅助选通信号，其中辅助驱动器绕过第一输出辅助选通信号和延迟以输出辅助选通信号中的其余的辅助选通信号和选通信号发生器，用于驱动辅助选通信号，以输出延迟的辅助选通信号作为数据选通信号。

6. 发明授权

US07446579B2 Semiconductor memory device having delay locked loop 有权
标题翻译：具有延迟锁定环路的半导体存储器件
公开(公告)号：US07446579B2
公开(公告)日：2008-11-04
申请号：US11477530
申请日：2006-06-30
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G11C7/1072 , G11C7/222
摘要： A semiconductor memory device has a delay locked loop (DLL) with low power consumption. The semiconductor memory device includes a DLL for receiving an external clock to generate a DLL clock, an idle detector for detecting an idle state in which a command for driving a device is not supplied, and an output controller for controlling the output of the DLL through the idle state whether or not data is output.
摘要翻译：半导体存储器件具有低功耗的延迟锁定环（DLL）。半导体存储器件包括用于接收外部时钟以生成DLL时钟的DLL，用于检测未提供用于驱动器件的命令的空闲状态的空闲检测器，以及用于控制DLL的输出的输出控制器空闲状态是否输出数据。

7. 发明申请

US20070069774A1 Semiconductor memory device having delay locked loop 有权
标题翻译：半导体存储器件具有延迟锁定环
公开(公告)号：US20070069774A1
公开(公告)日：2007-03-29
申请号：US11477530
申请日：2006-06-30
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G11C7/1072 , G11C7/222
摘要： A semiconductor memory device has a delay locked loop (DLL) with low power consumption. The semiconductor memory device includes a DLL for receiving an external clock to generate a DLL clock, an idle detector for detecting an idle state in which a command for driving a device is not supplied, and an output controller for controlling the output of the DLL through the idle state whether or not data is output.
摘要翻译：半导体存储器件具有低功耗的延迟锁定环（DLL）。半导体存储器件包括用于接收外部时钟以生成DLL时钟的DLL，用于检测未提供用于驱动器件的命令的空闲状态的空闲检测器，以及用于控制DLL的输出的输出控制器空闲状态是否输出数据。

8. 发明授权

US08059483B2 Address receiving circuit for a semiconductor apparatus 有权
标题翻译：半导体装置的地址接收电路
公开(公告)号：US08059483B2
公开(公告)日：2011-11-15
申请号：US12834429
申请日：2010-07-12
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C8/00
CPC分类号： G11C8/06
摘要： An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal.
摘要翻译：一种用于半导体装置的地址接收电路包括控制器，响应于半导体装置初始化命令，产生具有对应于半导体装置初始化命令的周期时间标准的激活周期的控制信号，以及地址缓冲器，根据控制信号接收地址。

9. 发明申请

US20100278004A1 ADDRESS RECEIVING CIRCUIT FOR A SEMICONDUCTOR APPARATUS 有权
标题翻译：地址接收电路用于半导体器件
公开(公告)号：US20100278004A1
公开(公告)日：2010-11-04
申请号：US12834429
申请日：2010-07-12
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C8/06
CPC分类号： G11C8/06
摘要： An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal.
摘要翻译：一种用于半导体装置的地址接收电路包括控制器，响应于半导体装置初始化命令，产生具有对应于半导体装置初始化命令的周期时间标准的激活周期的控制信号，以及地址缓冲器，根据控制信号接收地址。

10. 发明授权

US07515482B2 Pipe latch device of semiconductor memory device 有权
标题翻译：半导体存储器件的锁闩装置
公开(公告)号：US07515482B2
公开(公告)日：2009-04-07
申请号：US11477384
申请日：2006-06-30
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C7/00
CPC分类号： G11C19/28 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/222 , G11C11/4076 , G11C11/4096
摘要： A pipe latch device includes an output controller for outputting first and second output control signal groups based on a DLL clock signal and a driving signal; an input controller for generating an input control signal group; and a pipe latch unit for latching data on a data line when a corresponding input control signal is activated, and outputting latched data when a corresponding output control signal is activated, wherein the output controller includes a plurality of shifters, each for delaying an input data signal by half clock and one clock to output a first and second output signals in synchronization with the DLL clock signal and the driving signal; and a plurality of output control signal drivers for outputting the first and second output control signal groups based on the first and second output signals.
摘要翻译：管闩锁装置包括：输出控制器，用于基于DLL时钟信号和驱动信号输出第一和第二输出控制信号组; 用于产生输入控制信号组的输入控制器; 以及管锁存单元，用于当相应的输入控制信号被激活时将数据锁存在数据线上，并且当相应的输出控制信号被激活时输出锁存的数据，其中输出控制器包括多个移位器，每个移位器用于延迟输入数据信号通过半时钟和一个时钟与DLL时钟信号和驱动信号同步地输出第一和第二输出信号; 以及多个输出控制信号驱动器，用于基于第一和第二输出信号输出第一和第二输出控制信号组。

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