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41. 发明授权

US07447725B2 Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units 失效
标题翻译：用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置
公开(公告)号：US07447725B2
公开(公告)日：2008-11-04
申请号：US10982110
申请日：2004-11-05
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： An apparatus for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译：公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

42. 发明授权

US07406589B2 Processor having efficient function estimate instructions 失效
标题翻译：处理器具有有效的功能估计指令
公开(公告)号：US07406589B2
公开(公告)日：2008-07-29
申请号：US11127848
申请日：2005-05-12
申请人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/552 , G06F7/544 , G06F7/38
CPC分类号： G06F7/483 , G06F7/535 , G06F7/5443 , G06F7/5525 , G06F9/30014 , G06F2207/5356
摘要： High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.
摘要翻译：高精度浮点函数估计分为两个指令：低精度表查找指令和线性插值指令。可以使用该方案来实现不同功能的估计：为每个不同的功能提供单独的表查找指令，而仅需要单个插补指令，因为单个内插指令可以执行任何功能的内插步骤估计。因此，与专用硬件相比，产生的开销大大降低，同时仍保持统一的FPU延迟，这允许更简单的控制逻辑。

43. 发明授权

US07237163B2 Leakage current reduction system and method 有权
标题翻译：漏电流减少系统及方法
公开(公告)号：US07237163B2
公开(公告)日：2007-06-26
申请号：US10982111
申请日：2004-11-05
申请人： Sang Hoo Dhong , Hwa-Joon Oh , Silvia Melitta Mueller , Joel Silberman
发明人： Sang Hoo Dhong , Hwa-Joon Oh , Silvia Melitta Mueller , Joel Silberman
IPC分类号： G01R31/28
CPC分类号： G06F11/267 , G01R31/3008
摘要： An apparatus, a method and a computer program are provided to reduce leakage current in a processor. Traditionally, extra logic is employed to reduce leakage currents. However, reducing leakage current without sacrificing fine grain operations and speed can be difficult. Achieving such a goal can be accomplished by incorporating a multiplexer (mux) into the scan-in path of scan registers so that units or sub-units of the processor can be powered down individually. Additionally, the muxes are not incorporated into time paths, so speed can be preserved.
摘要翻译：提供了一种装置，方法和计算机程序以减少处理器中的泄漏电流。传统上，采用额外的逻辑来减少漏电流。然而，减少泄漏电流而不牺牲精细的晶粒操作和速度可能是困难的。可以通过将多路复用器（多路复用器）复用到扫描寄存器的扫描路径中来实现这一目标，从而可以单独关闭处理器的单元或子单元。此外，多路复用器并不并入时间路径，因此可以保留速度。

44. 发明授权

US07149877B2 Byte execution unit for carrying out byte instructions in a processor 失效
标题翻译：用于在处理器中执行字节指令的字节执行单元
公开(公告)号：US07149877B2
公开(公告)日：2006-12-12
申请号：US10621908
申请日：2003-07-17
申请人： Sang Hoo Dhong , Hwa-Joon Oh , Brad William Michael , Silvia Melitta Mueller , Kevin D. Tran
发明人： Sang Hoo Dhong , Hwa-Joon Oh , Brad William Michael , Silvia Melitta Mueller , Kevin D. Tran
IPC分类号： G06F15/76
CPC分类号： G06F9/30014 , G06F9/30036
摘要： A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation. In one embodiment, the byte execution unit includes multiple byte units. Each byte unit includes multiple population counters, two compressor units, adder input multiplexer logic, adder logic, and result multiplexer logic. A data processing system is described including a processor coupled to a memory system. The processor includes the byte execution unit. The memory system includes a byte instruction, wherein the byte instruction specifies either the count ones in bytes operation, the average bytes operation, the absolute differences of bytes operation, or the sum bytes into halfwords operation.
摘要翻译：公开的字节执行单元接收字节指令信息和两个操作数，并且在一个或两个操作数上执行由字节指令信息指定的操作，从而产生结果。字节指令指定以字节为单位的计数值，平均字节操作，字节操作的绝对差值，或字节字节到半字操作。在一个实施例中，字节执行单元包括多个字节单元。每个字节单元包括多个总体计数器，两个压缩器单元，加法器输入复用器逻辑，加法器逻辑和结果复用器逻辑。描述了包括耦合到存储器系统的处理器的数据处理系统。处理器包括字节执行单元。存储器系统包括一个字节指令，其中字节指令指定字节操作中的计数值，平均字节操作，字节操作的绝对差值，或字节数字到半字操作。

45. 发明授权

US06829682B2 Destructive read architecture for dynamic random access memories 有权
标题翻译：用于动态随机存取存储器的破坏性读取架构
公开(公告)号：US06829682B2
公开(公告)日：2004-12-07
申请号：US09843504
申请日：2001-04-26
申请人： Toshiaki Kirihata , Sang Hoo Dhong , Hwa-Joon Oh , Matthew Wordeman
发明人： Toshiaki Kirihata , Sang Hoo Dhong , Hwa-Joon Oh , Matthew Wordeman
IPC分类号： G06F1200
CPC分类号： G06F12/0893 , G11C7/1006 , G11C2207/2245
摘要： A method for controlling the operation of a dynamic random access memory (DRAM) system, the DRAM system having a plurality of memory cells organized into rows and columns, is disclosed. In an exemplary embodiment of the invention, the method includes enabling a destructive read mode, the destructive read mode for destructively reading a bit of information stored within an addressed DRAM memory cell. The destructively read bit of information is temporarily stored into a temporary storage device. A delayed write back mode is enabled, the delayed write back mode for restoring the bit of information back to the addressed DRAM memory cell at a later time. The execution of the delayed write back mode is then scheduled, depending upon the availability of space within the temporary storage device.
摘要翻译：公开了一种用于控制动态随机存取存储器（DRAM）系统的操作的方法，该DRAM系统具有被组织成行和列的多个存储单元。在本发明的示例性实施例中，该方法包括启用破坏性读取模式，该破坏性读取模式用于破坏性地读取存储在寻址的DRAM存储器单元中的位的位。信息的破坏性读取位被临时存储到临时存储设备中。延迟回写模式被使能，延迟回写模式用于将信息位在稍后的时间恢复到寻址的DRAM存储器单元。然后根据临时存储设备内的空间的可用性来调度延迟写回模式的执行。

46. 发明授权

US06594679B1 Leading-zero anticipator having an independent sign bit determination module 有权
标题翻译：具有独立符号位确定模块的前零预测器
公开(公告)号：US06594679B1
公开(公告)日：2003-07-15
申请号：US09531850
申请日：2000-03-20
申请人： Kyung Tek Lee , Kevin John Nowka , Sang Hoo Dhong
发明人： Kyung Tek Lee , Kevin John Nowka , Sang Hoo Dhong
IPC分类号： G06F1500
CPC分类号： G06F7/74 , G06F7/485 , G06F7/49936 , G06F7/5443
摘要： A leading-zero anticipator having an independent sign bit determination module is disclosed. An apparatus for anticipating leading zeros for an adder within a floating-point processor includes a leading-zero anticipator and a sign determination module. The leading-zero anticipator generates a leading zeros string and a leading ones string by examining carry propagates, generates, and kills of two adjacent bits of two input operands of the adder. The leading zeros string is intended for a positive sum, and the leading ones string is intended for a negative sum. Independent of the leading-zero anticipator, the sign determination module determines a sign of the output of the adder in concurrence with the operations within the leading-zero anticipator.
摘要翻译：公开了一种具有独立符号位确定模块的前置零预测器。用于预测浮点处理器内的加法器的前导零的装置包括前置零预测器和符号确定模块。前导零预测器通过检查进位传播，产生和杀死加法器的两个输入操作数的两个相邻位来产生前导零字符串和前导字符串。前导零字符串用于正和，并且前导字符串用于负和。独立于前置零预测器，符号确定模块根据前置零预测器中的操作来确定加法器的输出的符号。

47. 发明授权

US06519174B2 Early write DRAM architecture with vertically folded bitlines 有权
标题翻译：早期写入具有垂直折叠位线的DRAM架构
公开(公告)号：US06519174B2
公开(公告)日：2003-02-11
申请号：US09859145
申请日：2001-05-16
申请人： Toshiaki K. Kirihata , Sang Hoo Dhong
发明人： Toshiaki K. Kirihata , Sang Hoo Dhong
IPC分类号： G11C506
CPC分类号： G11C11/4097
摘要： A memory cell system for a dynamic random access memory (DRAM) array is disclosed. In an exemplary embodiment of the invention, the system includes a plurality of data storage elements arranged in rows and columns. A plurality of wordlines corresponds to the columns, and a plurality of lower bit lines corresponds to the rows, with each of the plurality of lower bitlines further being associated with a plurality of upper, complementary bitlines thereto. The plurality of upper bitlines are vertically aligned with the plurality of lower bitlines, thereby defining a plurality of vertically folded bitline pairs. Further, a plurality of sense amplifiers are arranged in the rows, with each of said plurality of sense amplifiers having one of said plurality of vertically folded bitline pairs as inputs thereto. When one of the plurality of wordlines is activated, a subset of the rows corresponding to the vertically folded bitline pairs is activated.
摘要翻译：公开了一种用于动态随机存取存储器（DRAM）阵列的存储单元系统。在本发明的示例性实施例中，系统包括以行和列排列的多个数据存储元件。多个字线对应于列，并且多个下位线对应于行，多个下位线中的每一个还与其上的多个上互补位线相关联。多个上位线与多个下位线垂直对准，从而限定多个垂直折叠的位线对。此外，多行读出放大器布置在行中，所述多个读出放大器中的每一个具有所述多个垂直折叠的位线对中的一个作为其输入。当多个字线中的一个被激活时，对应于垂直折叠的位线对的行的子集被激活。

48. 发明授权

US06282557B1 Low latency fused multiply-adder 失效
标题翻译：低延迟融合乘法加法器
公开(公告)号：US06282557B1
公开(公告)日：2001-08-28
申请号：US09207483
申请日：1998-12-08
申请人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
发明人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G06F748
CPC分类号： G06F7/5443 , G06F7/5318
摘要： A low latency fused multiply-adder for adding a product of a first binary number and a second binary number to a third binary number is disclosed. The low latency fused multiply-adder includes a partial product generation module, a partial product reduction module, and a carry propagate adder. The partial product generation module generates a set of partial products from the first binary number and the second binary number. Coupled to the partial product generation module, the partial product reduction module combines the set of partial products with the third binary number to produce a redundant Sum and a redundant Carry. Finally, the carry propagate adder adds the redundant Sum and the redundant Carry to yield a Sum Total.
摘要翻译：公开了一种用于将第一二进制数和第二二进制数的乘积加到第三个二进制数的低延迟融合乘法加法器。低延迟融合乘法器包括部分乘积生成模块，部分乘积减少模块和进位传播加法器。部分乘积生成模块从第一二进制数和第二二进制数生成一组部分乘积。与部分产品生成模块相结合，部分产品减少模块将部分产品集合与第三个二进制数组合，以产生冗余Sum和冗余进位。最后，进位传播加法器将冗余Sum和冗余Carry相加，得到Sum Total。

49. 发明授权

US06268660B1 Silicon packaging with through wafer interconnects 有权
标题翻译：通过晶圆互连的硅封装
公开(公告)号：US06268660B1
公开(公告)日：2001-07-31
申请号：US09263032
申请日：1999-03-05
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Michael Jay Shapiro
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Michael Jay Shapiro
IPC分类号： H01L2348
CPC分类号： H01L23/5384 , H01L23/481 , H01L2224/16 , H01L2924/01322 , H01L2924/10253 , H01L2924/00
摘要： A package for integrated circuit chips. The package contains a silicon substrate having a top surface and a bottom surface. The package also contains a first means for electrically connecting the integrated circuits to the substrate attached to the top surface of the substrate. A multilevel wiring is located at the top surface and is coupled to the first connecting means and serves as a communication link among a plurality of the first connecting means to enable multi-chip processing. A via containing means for coupling the multilevel wiring at the top surface to the bottom surface runs through the substrate from the bottom surface to the top surface. A second means is also present for connecting the coupling means at the bottom surface of the substrate with external components.
摘要翻译：集成电路芯片封装。该封装包含具有顶表面和底表面的硅衬底。封装还包含用于将集成电路电连接到附接到衬底顶表面的衬底的第一装置。多层布线位于顶表面并且耦合到第一连接装置，并且用作多个第一连接装置之间的通信链路，以实现多芯片处理。用于将上表面的多层布线耦合到底表面的通孔容纳装置从底表面到顶表面穿过基底。还存在用于将基板的底表面处的耦合装置与外部部件连接的第二装置。

50. 发明授权

US06237085B1 Processor and method for generating less than (LT), Greater than (GT), and equal to (EQ) condition code bits concurrent with a logical or complex operation 失效
标题翻译：用于生成小于（LT），大于（GT）和等于（EQ）条件码位的处理器和方法与逻辑或复杂操作并发
公开(公告)号：US06237085B1
公开(公告)日：2001-05-22
申请号：US09207482
申请日：1998-12-08
申请人： Jeffrey Burns , Sang Hoo Dhong , Kevin John Nowka
发明人： Jeffrey Burns , Sang Hoo Dhong , Kevin John Nowka
IPC分类号： G06F9305
CPC分类号： G06F9/30094 , G06F7/026 , G06F9/3875
摘要： A processor includes execution resources and condition code logic. The execution resources execute an arithmetic or logical instruction by arithmetically or logically combining at least two operands. Concurrent with the execution of the arithmetic or logical instruction by the execution resources, the condition code logic determines less than, greater than, and equal to condition code bits associated with the result of the arithmetic or logical instruction. In one embodiment, the condition code logic includes a single computation stage that receives as inputs individual bit values of bit positions within first and second operands and logically combines the individual bit values. The single computation stage outputs, for each bit position, propagate, generate, and kill signals that collectively indicate values for the less than, greater than, and equal to condition code bits. One or more merging stages coupled to the computation stage then merge the propagate, generate, and kill signals into output signals that set the condition code bits. The condition code logic is also capable of receiving externally computed condition code bits associated with complex instructions and utilizing such condition code bits to produce the output signals.
摘要翻译：处理器包括执行资源和条件代码逻辑。执行资源通过算术或逻辑地组合至少两个操作数来执行算术或逻辑指令。与执行资源执行算术或逻辑指令同时，条件代码逻辑确定小于，大于和等于与算术或逻辑指令的结果相关联的条件码位。在一个实施例中，条件码逻辑包括单个计算阶段，其接收第一和第二操作数中的比特位置的各个比特值作为输入，并逻辑地组合各个比特值。对于每个位位置，单个计算级输出传播，产生和去除共同指示小于，大于和等于条件码位的值的信号。耦合到计算阶段的一个或多个合并阶段然后将传播，生成和终止信号合并到设置条件码位的输出信号中。条件代码逻辑还能够接收与复杂指令相关联的外部计算的条件码位，并利用这些条件码位产生输出信号。

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