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41. 发明申请

US20120047321A1 Address Scheduling Methods For Non-Volatile Memory Devices With Three-Dimensional Memory Cell Arrays 审中-公开
标题翻译：用于具有三维存储器单元阵列的非易失性存储器件的地址调度方法
公开(公告)号：US20120047321A1
公开(公告)日：2012-02-23
申请号：US13213806
申请日：2011-08-19
申请人： Chi Weon Yoon , Dong Hyuk Chae , Sang-Wan Nam , Jung-Yun Yun
发明人： Chi Weon Yoon , Dong Hyuk Chae , Sang-Wan Nam , Jung-Yun Yun
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G06F12/0646 , G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F2212/2022 , G11C5/025 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483
摘要： At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
摘要翻译：至少一个地址调度方法包括选择第一位线，选择连接到第一位线的第一串，在第一串中的每个多电平单元的N页上从底部字线到顶部执行地址调度字线，并且在完成第一串中的所有字线上的地址调度之后，以与对第一字符串执行的相同的方式依次执行第二至第K个字符串的地址调度，其中“k”为2或自然数大于2。

42. 发明申请

US20120039130A1 Nonvolatile Memory Devices, Channel Boosting Methods Thereof, Programming Methods Thereof, And Memory Systems Including The Same 有权
标题翻译：非易失性存储器件，其通道升压方法，其编程方法和包括其的存储器系统
公开(公告)号：US20120039130A1
公开(公告)日：2012-02-16
申请号：US13152776
申请日：2011-06-03
申请人： ChiWeon Yoon , Donghyuk Chae , Sang-Wan Nam , Sung-Won Yun
发明人： ChiWeon Yoon , Donghyuk Chae , Sang-Wan Nam , Sung-Won Yun
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3418 , H01L27/11556 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings.
摘要翻译：非易失性存储器件通道升压方法，其中至少两个串连接到一个位线，所述通道升压方法包括将初始通道电压施加到所选存储器块中的串的通道，每个具有未编程的浮动禁止串字符串之间的单元格，以及浮动禁止字符串的增强通道。

43. 发明申请

US20080112229A1 Sense Amplifiers Including Multiple Precharge Circuits and Associated Memory Devices and Sensing Methods 有权
标题翻译：包括多个预充电电路和相关存储器件和检测方法的检测放大器
公开(公告)号：US20080112229A1
公开(公告)日：2008-05-15
申请号：US11563746
申请日：2006-11-28
申请人： Ji-ho Cho , Sang-Wan Nam
发明人： Ji-ho Cho , Sang-Wan Nam
IPC分类号： G11C16/06 , G11C7/00 , G11C11/34
CPC分类号： G11C16/24 , G11C7/067 , G11C7/12 , G11C16/26
摘要： A sense amplifier of a flash memory device maintains a bit line precharge level before a memory cell is sensed. The sense amplifier maintains the voltage of a bias signal sufficiently high using a second precharging circuit in a precharging operation to stably maintain the bit line precharge level set by a first precharging circuit. Accordingly, the sense amplifier can correctly sense an OFF cell using the stabilized bit line precharge voltage. Related methods and memory devices are also disclosed.
摘要翻译：闪速存储器件的读出放大器在感测存储器单元之前保持位线预充电电平。读出放大器在预充电操作中使用第二预充电电路来保持偏置信号的电压足够高以稳定地维持由第一预充电电路设置的位线预充电电平。因此，读出放大器可以使用稳定的位线预充电电压来正确地感测OFF单元。还公开了相关方法和存储器件。

44. 发明授权

US07372747B2 Flash memory device and voltage generating circuit for the same 有权
标题翻译：闪存器件和电压发生电路相同
公开(公告)号：US07372747B2
公开(公告)日：2008-05-13
申请号：US11482447
申请日：2006-07-07
申请人： Sang-Wan Nam , Dae-Han Kim
发明人： Sang-Wan Nam , Dae-Han Kim
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C16/08 , G11C16/12
摘要： A flash memory device and a voltage generating circuit for the same. The flash memory includes a memory cell array configured with a plurality of memory cells, a voltage generating circuit for generating a plurality of constant voltages to be applied to the memory cell array, and a selection circuit for selecting one constant voltage among the plurality of the constant voltages and applying the selected one constant voltage to the memory cell array. The voltage generating circuit discharges a leakage current input by the selection circuit through a voltage division path, which generates the constant voltages.
摘要翻译：一种闪存器件及其电压产生电路。闪存包括配置有多个存储单元的存储单元阵列，用于产生施加到存储单元阵列的多个恒定电压的电压产生电路，以及用于选择多个存储单元中的一个恒定电压的选择电路将所选择的一个恒定电压施加到存储单元阵列。电压产生电路通过分压路径对由选择电路输入的漏电流进行放电，产生恒定电压。

45. 发明申请

US20070201277A1 NOR flash memory device with a serial sensing operation and method of sensing data bits in a NOR flash memory device 审中-公开
公开(公告)号：US20070201277A1
公开(公告)日：2007-08-30
申请号：US11789624
申请日：2007-04-25
申请人： Sang-Wan Nam , Young-Ho Lim , Dae-Han Kim
发明人： Sang-Wan Nam , Young-Ho Lim , Dae-Han Kim
IPC分类号： G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C16/26
摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

46. 发明申请

US20060215449A1 NOR flash memory device with a serial sensing operation and method of sensing data bits in a NOR flash memory device 失效
标题翻译：具有串行感测操作的NOR闪存器件和用于检测NOR闪存器件中的数据位的方法
公开(公告)号：US20060215449A1
公开(公告)日：2006-09-28
申请号：US11263716
申请日：2005-11-01
申请人： Sang-Wan Nam , Young-Ho Lim , Dae-Han Kim
发明人： Sang-Wan Nam , Young-Ho Lim , Dae-Han Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/26
摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.
摘要翻译：在具有串行感测操作的NOR闪存器件中，以及在NOR闪存器件中检测数据位的方法，该器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑电路。感测放大电路串行地检测存储在多电平单元中的多个数据位。提供数据缓冲器以缓冲由读出放大器检测到的数据位。数据锁存电路一次存储数据缓冲器的输出值。控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。

47. 发明申请

US20060092716A1 Memory devices using tri-state buffers to discharge data lines, and methods of operating same 失效
标题翻译：使用三态缓冲器来释放数据线的存储器件，以及操作方法
公开(公告)号：US20060092716A1
公开(公告)日：2006-05-04
申请号：US11153508
申请日：2005-06-15
申请人： Sang-Wan Nam , Seung-Keun Lee
发明人： Sang-Wan Nam , Seung-Keun Lee
IPC分类号： G11C7/10
CPC分类号： G11C16/26 , G11C7/1051 , G11C7/1057 , G11C7/106
摘要： A memory device includes a sense amplifier circuit, a tri-state buffer, a data latch circuit and a data line. The sense amplifier circuit senses and amplifies a current of a memory cell. The tri-state buffer receives an output of the sense amplifier circuit. The data latch circuit latches an output of the tri-state buffer. The data line connects the tri-state buffer and the data latch circuit. The memory device removes charge on the data line using a latch enable signal, which is applied to the tri-state buffer before a read operation.
摘要翻译：存储器件包括读出放大器电路，三态缓冲器，数据锁存电路和数据线。感测放大器电路感测并放大存储器单元的电流。三态缓冲器接收读出放大器电路的输出。数据锁存电路锁存三态缓冲器的输出。数据线连接三态缓冲器和数据锁存电路。存储器件使用锁存使能信号去除数据线上的电荷，该信号在读取操作之前被施加到三态缓冲器。

48. 发明授权

US09870825B2 Nonvolatile memory device and method of programming the same 有权
公开(公告)号：US09870825B2
公开(公告)日：2018-01-16
申请号：US14733239
申请日：2015-06-08
申请人： Sang-Wan Nam , Wandong Kim
发明人： Sang-Wan Nam , Wandong Kim
IPC分类号： G11C16/10 , G11C16/24 , G11C16/08 , G11C16/04 , G11C11/56
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/24
摘要： A nonvolatile memory device includes a memory cell array, an address decoder, a read & write circuit and control logic. The memory cell array includes a plurality of memory blocks including a plurality of cell strings, each cell string including a plurality of memory cells stacked in a direction perpendicular to a substrate. The control logic controls operations so that in a program operation, when the selected word line satisfies a precharge condition, a program voltage to be applied to the selected word line is applied before a pass voltage to be applied to an unselected word line.

49. 发明授权

US09666283B2 Nonvolatile memory devices and driving methods thereof 有权
公开(公告)号：US09666283B2
公开(公告)日：2017-05-30
申请号：US15152692
申请日：2016-05-12
申请人： Kyung-Hwa Kang , Sang-Wan Nam , Donghyuk Chae , ChiWeon Yoon
发明人： Kyung-Hwa Kang , Sang-Wan Nam , Donghyuk Chae , ChiWeon Yoon
IPC分类号： G11C16/04 , G11C16/08 , H01L27/1157 , H01L27/11582 , G11C16/24 , H01L23/528 , H01L27/11565
CPC分类号： G11C16/0483 , G11C16/0466 , G11C16/08 , G11C16/24 , H01L23/528 , H01L27/11565 , H01L27/1157 , H01L27/11582
摘要： Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.

50. 发明授权

US09418753B2 Method of operating memory controller and data storage device including memory controller 有权
标题翻译：操作存储器控制器和包括存储器控制器的数据存储设备的方法
公开(公告)号：US09418753B2
公开(公告)日：2016-08-16
申请号：US14073155
申请日：2013-11-06
申请人： Sang-Wan Nam , Kitae Park
发明人： Sang-Wan Nam , Kitae Park
IPC分类号： G06F11/00 , G11C16/34 , G11C11/56 , G06F11/14
CPC分类号： G06F3/0653 , G06F3/0604 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F11/1068 , G06F11/1402 , G11C11/5628 , G11C16/3445 , G11C16/3495 , G11C29/52
摘要： In one embodiment, the method includes determining, at the memory controller, a status of a selected page of memory based on a program/erase cycle count for a block of the memory. The block of the memory includes the selected page. The program/erase cycle count indicates a number of times the block has been erased. The status is selected from a plurality of status states. The status states include a normal state, a weak state and a bad state.
摘要翻译：在一个实施例中，该方法包括基于存储器块的编程/擦除周期计数在存储器控制器处确定所选择的存储器页的状态。存储器的块包括所选择的页面。程序/擦除周期计数指示块已被擦除的次数。该状态是从多个状态中选择的。状态包括正常状态，弱状态和坏状态。

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