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41. 发明授权

US06699790B2 Semiconductor device fabrication method for filling high aspect ratio openings in insulators with aluminum 有权
标题翻译：用于在铝绝缘体中填充高纵横比开口的半导体器件制造方法
公开(公告)号：US06699790B2
公开(公告)日：2004-03-02
申请号：US10035807
申请日：2002-01-04
申请人： Byung-Hee Kim , Jong-Myeong Lee , Myoung-Bum Lee , Gil-Heyun Choi
发明人： Byung-Hee Kim , Jong-Myeong Lee , Myoung-Bum Lee , Gil-Heyun Choi
IPC分类号： H01L21443
CPC分类号： H01L21/76876 , H01L21/76843 , H01L21/76879 , H01L21/76882
摘要： A semiconductor device fabrication method having a recess region in an insulation layer on a silicon substrate, includes the steps of depositing a barrier metal on an entire surface of the insulation layer, filling the recess region with an oxide layer, removing the barrier metal on an upper side of the insulation layer, removing the oxide layer in the recess region and exposing the barrier metal of the recess region, depositing a CVD-Al layer on the barrier metal, and depositing a PVD-Al layer on the CVD-Al layer and re-flowing the PVD-Al layer. The fabrication method of a semiconductor integrated circuit according to the present invention selectively removes a barrier metal in the outside of the recess region to expose the insulation layer to the air, and deposits the CVD-Al layer and the PVD-Al layer, which results in controlling abnormal growth of the CVD-Al metal.
摘要翻译：一种在硅衬底上的绝缘层中具有凹陷区域的半导体器件制造方法，包括以下步骤：在绝缘层的整个表面上沉积阻挡金属，用氧化物层填充该凹陷区域，去除所述凹陷区域中的氧化物层并暴露所述凹陷区域的阻挡金属，在所述阻挡金属上沉积CVD-Al层，以及在所述CVD-Al层上沉积PVD-Al层，以及重新流动PVD-Al层。根据本发明的半导体集成电路的制造方法选择性地去除凹陷区域的外部的阻挡金属以将绝缘层暴露于空气，并沉积CVD-Al层和PVD-Al层，这导致控制CVD-Al金属的异常生长。

42. 发明授权

US08546162B2 Method for forming light guide layer in semiconductor substrate 有权
标题翻译：在半导体衬底中形成导光层的方法
公开(公告)号：US08546162B2
公开(公告)日：2013-10-01
申请号：US13243763
申请日：2011-09-23
申请人： Dae-Lok Bae , Byung-Lyul Park , Pil-Kyu Kang , Gil-Heyun Choi , Kwang-Jin Moon
发明人： Dae-Lok Bae , Byung-Lyul Park , Pil-Kyu Kang , Gil-Heyun Choi , Kwang-Jin Moon
IPC分类号： H01L21/00
CPC分类号： G02B6/138 , G02B6/136
摘要： A method for forming a light guide layer with improved transmission reliability in a semiconductor substrate, the method including forming a trench in the semiconductor substrate, forming a cladding layer and a preliminary light guide layer in the trench such that only one of opposite side end portions of the preliminary light guide layer is in contact with an inner sidewall of the trench, and performing a thermal treatment on the substrate to change the preliminary light guide layer into the light guide layer.
摘要翻译：一种在半导体衬底中形成具有改善的透射可靠性的导光层的方法，所述方法包括在所述半导体衬底中形成沟槽，在所述沟槽中形成包覆层和预备导光层，使得只有一个相对侧端部所述预备光导层与所述沟槽的内侧壁接触，并对所述基板进行热处理，以将所述初步导光层改变为所述导光层。

43. 发明申请

US20120314991A1 SEMICONDUCTOR DEVICES HAVING OPTICAL TRANSCEIVER 有权
标题翻译：具有光学收发器的半导体器件
公开(公告)号：US20120314991A1
公开(公告)日：2012-12-13
申请号：US13412210
申请日：2012-03-05
申请人： Pil-Kyu Kang , Dae-Lok Bae , Byung-Lyul Park , Gil-Heyun Choi
发明人： Pil-Kyu Kang , Dae-Lok Bae , Byung-Lyul Park , Gil-Heyun Choi
IPC分类号： G02B6/12 , H01L29/06
CPC分类号： G02B6/124 , G02B6/136 , G02B6/4206 , G02B6/43
摘要： Semiconductor devices having an optical transceiver include a cladding on a substrate, a protrusion vertically extending trough the cladding and materially in continuity with the substrate, and a coupler on the cladding and the protrusion.
摘要翻译：具有光收发器的半导体器件包括在衬底上的包层，垂直延伸穿过覆层并与衬底物理连续的突起，以及在包层和突起上的耦合器。

44. 发明授权

US08304343B2 Method of manufacturing a metal wiring structure 有权
标题翻译：制造金属布线结构的方法
公开(公告)号：US08304343B2
公开(公告)日：2012-11-06
申请号：US13240109
申请日：2011-09-22
申请人： Kyung-In Choi , Hyeon-Deok Lee , Gil-Heyun Choi , Jong-Myeong Lee
发明人： Kyung-In Choi , Hyeon-Deok Lee , Gil-Heyun Choi , Jong-Myeong Lee
IPC分类号： H01L21/768
CPC分类号： H01L21/76814 , H01L21/76843 , H01L21/76852 , H01L21/76856 , H01L27/11526 , H01L27/11543 , H01L27/11546 , H01L27/11548
摘要： In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitridation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole.
摘要翻译：在制造金属布线结构的方法中，在基板上形成第一金属布线和第一阻挡层，并且对第一阻挡层进行氮化。绝缘中间层形成在基板上，以便延伸越过第一金属布线和第一阻挡层。去除部分绝缘中间层以形成露出第一金属布线和第一阻挡层的一部分的至少一部分的孔。在第一阻挡层的暴露部分上进行氮化等离子体处理。沿着孔的底部和侧面形成第二阻挡层。在第二阻挡层上形成插塞以填充孔。

45. 发明授权

US08278207B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08278207B2
公开(公告)日：2012-10-02
申请号：US12688557
申请日：2010-01-15
申请人： Jin-Ho Park , Gil-Heyun Choi , Byung-Lyul Park , Jong-Myeong Lee , Zung-Sun Choi , Hye-Kyung Jung
发明人： Jin-Ho Park , Gil-Heyun Choi , Byung-Lyul Park , Jong-Myeong Lee , Zung-Sun Choi , Hye-Kyung Jung
IPC分类号： H01L21/4763
CPC分类号： H01L21/76846 , H01L21/28562 , H01L21/76856 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L27/10855 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.
摘要翻译：半导体器件可以包括在其上形成有多个下导电结构的基板上的绝缘层，其中绝缘层具有开口。阻挡层位于绝缘层的开口的侧壁和底部上，其中阻挡层包括第一阻挡层，第一脱氧材料的成分比第一阻挡层中的金属材料更富，第二阻隔层阻挡层，其中第二阻挡层中的金属材料比第二脱氧材料的成分更富。互连在其开口中，侧壁和底部被阻挡层覆盖，互连电连接到下导电结构。

46. 发明申请

US20110318923A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME INCLUDING A CONDUCTIVE STRUCTURE IS FORMED THROUGH AT LEAST ONE DIELECTRIC LAYER AFTER FORMING A VIA STRUCTURE 有权
标题翻译：半导体器件及其制造方法，包括导电结构在形成一个结构之后通过至少一个介电层形成
公开(公告)号：US20110318923A1
公开(公告)日：2011-12-29
申请号：US12913753
申请日：2010-10-27
申请人： Byung-Lyul Park , Gil-Heyun Choi , Suk-Chul Bang , Kwang-Jin Moon , Dong-Chan Lim , Deok-Young Jung
发明人： Byung-Lyul Park , Gil-Heyun Choi , Suk-Chul Bang , Kwang-Jin Moon , Dong-Chan Lim , Deok-Young Jung
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L21/76801 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06513 , H01L2225/06541
摘要： For forming a semiconductor device, a via structure is formed through at least one dielectric layer and at least a portion of a substrate. In addition, a protective buffer layer is formed onto the via structure. Furthermore, a conductive structure for an integrated circuit is formed over the substrate after forming the via structure and the protective buffer layer, with the conductive structure not being formed over the via structure. Thus, deterioration of the conductive and via structures is minimized.
摘要翻译：为了形成半导体器件，通过至少一个电介质层和至少一部分衬底形成通孔结构。此外，在通孔结构上形成保护缓冲层。此外，在形成通孔结构和保护缓冲层之后，在衬底上形成用于集成电路的导电结构，其中导电结构不在过孔结构上形成。因此，导电和通孔结构的劣化被最小化。

47. 发明授权

US07875939B2 Semiconductor device including an ohmic layer 有权
标题翻译：包括欧姆层的半导体器件
公开(公告)号：US07875939B2
公开(公告)日：2011-01-25
申请号：US12453198
申请日：2009-05-01
申请人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Sun-Pil Youn , Dong-Chan Lim , Jae-Hwa Park , Jang-Hee Lee , Woong-Hee Sohn
发明人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Sun-Pil Youn , Dong-Chan Lim , Jae-Hwa Park , Jang-Hee Lee , Woong-Hee Sohn
IPC分类号： H01L23/532
CPC分类号： H01L29/4933 , C23C16/42 , H01L21/28061 , H01L21/28194 , H01L21/28556 , H01L21/76846 , H01L29/517
摘要： In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.
摘要翻译：在欧姆层和形成欧姆层的方法中，包括欧姆层的栅极结构和具有欧姆层的金属布线，欧姆层使用包含钨和硅的硅化钨形成，原子比在约 1:5至约1:15。可以在室内使用包含钨源气体和硅源气体的反应气体，在约1.0:25.0至约1.0:16.0.0的范围内的分压比获得硅化钨。反应气体可以具有在室的总内部压力的约2.05％至约30.0％的范围内的分压。当欧姆层用于诸如栅极结构或金属布线的导电结构时，导电结构可以具有降低的电阻。

48. 发明授权

US07833847B2 Method of forming semiconductor device having stacked transistors 有权
标题翻译：形成具有堆叠晶体管的半导体器件的方法
公开(公告)号：US07833847B2
公开(公告)日：2010-11-16
申请号：US12503556
申请日：2009-07-15
申请人： Hyun-Su Kim , Gil-Heyun Choi , Jong-Ho Yun , Sug-Woo Jung , Eun-Ji Jung
发明人： Hyun-Su Kim , Gil-Heyun Choi , Jong-Ho Yun , Sug-Woo Jung , Eun-Ji Jung
IPC分类号： H01L21/84 , H01L21/00 , H01L21/44 , H01L21/4763 , H01L21/762
CPC分类号： H01L21/28518 , H01L21/76898 , H01L21/8221 , H01L27/0688 , H01L27/11 , H01L27/1108
摘要： There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are optimally formed to meet requirements or conditions. Accordingly, the contact resistance of the common contact may be minimized so that it is possible to enhance the speed of the semiconductor device.
摘要翻译：提供了一种形成具有堆叠晶体管的半导体器件的方法。当形成用于将堆叠的晶体管彼此连接的接触孔时，共同接触孔的底部和侧壁上的欧姆层分开形成。结果，各个欧姆层被最佳地形成以满足要求或条件。因此，公共接点的接触电阻可以最小化，从而可以提高半导体器件的速度。

49. 发明授权

US07772637B2 Semiconductor devices including gate structures and leakage barrier oxides 有权
标题翻译：包括栅极结构和漏电阻氧化物的半导体器件
公开(公告)号：US07772637B2
公开(公告)日：2010-08-10
申请号：US12401087
申请日：2009-03-10
申请人： Woong-Hee Sohn , Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Jong-Ryeol Yoo , Hee-Sook Park
发明人： Woong-Hee Sohn , Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Jong-Ryeol Yoo , Hee-Sook Park
IPC分类号： H01L21/00
CPC分类号： H01L21/28273 , H01L29/42324
摘要： Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.
摘要翻译：形成半导体器件的方法可以包括在半导体衬底上形成隧道氧化物层，在隧道氧化物层上形成栅极结构，形成漏电阻氧化物，并形成绝缘衬垫。更具体地，隧道氧化物层可以在栅极结构和衬底之间，并且栅极结构可以包括隧道氧化物层上的第一栅极电极，第一栅电极上的栅极间电介质和第二栅电极所述栅极间电介质与所述第一和第二栅电极之间的栅极间电介质。漏电阻氧化物可以形成在第二栅电极的侧壁上。绝缘间隔物可以在绝缘隔离物和第二栅电极的侧壁之间的泄漏阻挡氧化物形成在漏电阻氧化物上。此外，绝缘间隔物和漏电阻氧化物可以包括不同的材料。还讨论了相关结构。

50. 发明申请

US20100120211A1 Methods of manufacturing Semiconductor Devices Including PMOS and NMOS Transistors Having Different Gate Structures 审中-公开
标题翻译：包括具有不同栅极结构的PMOS和NMOS晶体管的半导体器件的制造方法
公开(公告)号：US20100120211A1
公开(公告)日：2010-05-13
申请号：US12613746
申请日：2009-11-06
申请人： Jae-Hwa Park , Gil-Heyun Choi , Hee-Sook Park , Jong-Min Baek
发明人： Jae-Hwa Park , Gil-Heyun Choi , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823821 , H01L21/823842 , H01L21/82385 , H01L27/105 , H01L27/1052
摘要： A semiconductor device may include a semiconductor substrate having first and second regions. A first gate structure on the first region of the semiconductor substrate may include a metal oxide dielectric layer on the first region of the semiconductor substrate and a first conductive layer on the metal oxide dielectric layer. First and second source/drain regions of a first conductivity type may be provided in the first region of the semiconductor substrate on opposite sides of the first gate structure. A second gate structure on the second region of the semiconductor substrate may include a silicon oxide based dielectric layer and a second conductive layer on the silicon oxide based dielectric layer. First and second source/drain regions of a second conductivity type may be provided in the second region of the semiconductor substrate on opposite sides of the second gate structure, wherein the first and second conductivity types are different. Related methods are also discussed.
摘要翻译：半导体器件可以包括具有第一和第二区域的半导体衬底。半导体衬底的第一区域上的第一栅极结构可以包括在半导体衬底的第一区域上的金属氧化物电介质层和金属氧化物电介质层上的第一导电层。可以在第一栅极结构的相对侧的半导体衬底的第一区域中设置第一导电类型的第一和第二源极/漏极区域。半导体衬底的第二区域上的第二栅极结构可以包括基于氧化硅的电介质层和在氧化硅基介电层上的第二导电层。可以在第二栅极结构的相对侧的半导体衬底的第二区域中提供第二导电类型的第一和第二源极/漏极区域，其中第一和第二导电类型不同。还讨论了相关方法。

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