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41. 发明授权

US06753239B1 Bond and back side etchback transistor fabrication process 有权
标题翻译：键合和背面回蚀晶体管制造工艺
公开(公告)号：US06753239B1
公开(公告)日：2004-06-22
申请号：US10407746
申请日：2003-04-04
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L2130
CPC分类号： H01L27/1203 , H01L21/76256 , H01L21/84 , Y10S438/928
摘要： A supporting structure is wafer-bonded to the upper face side of a partially or fully processed device wafer. The device wafer includes a transistor having a well region that extends into the substrate material of the device wafer. The source and drain regions of the transistor extend into the well region. After attachment of the supporting structure, the device wafer is thinned from the back side until the bottom of the well region is reached. To reduce source and drain junction capacitances, etching can continue until the source and drain regions are reached. In one embodiment, all of the well-to-substrate junction is removed in a subsequent etching step, thereby reducing or eliminating the well-to-substrate junction capacitance of the resulting transistor. Resistance between the well electrode and the transistor channel is reduced because the well contact is disposed on the back side of the device wafer directly under the gate of the transistor.
摘要翻译：将支撑结构晶片结合到部分或完全处理的器件晶片的上表面侧。器件晶片包括具有延伸到器件晶片的衬底材料中的阱区的晶体管。晶体管的源区和漏极区延伸到阱区。在安装支撑结构之后，装置晶片从后侧变薄直到达到井区的底部。为了减少源极和漏极结电容，可以继续蚀刻直到达到源极和漏极区域。在一个实施例中，在随后的蚀刻步骤中除去所有的阱到衬底结，从而减少或消除所得晶体管的阱到衬底结电容。阱电极和晶体管沟道之间的电阻降低，因为阱触点直接设置在晶体管的栅极正下方的器件晶片的背面。

42. 发明授权

US06271795B1 Increased propagation speed across integrated circuits 有权
公开(公告)号：US06271795B1
公开(公告)日：2001-08-07
申请号：US09652383
申请日：2000-08-31
申请人： Austin H. Lesea , Robert O. Conn
发明人： Austin H. Lesea , Robert O. Conn
IPC分类号： H01Q138
CPC分类号： H01Q21/0037 , H01Q1/38
摘要： The maximum propagation speed of an electrical signal travelling on a conductor in an integrated circuit is limited by the dielectric constant of the dielectric material surrounding the conductor. Rather than transmitting an electrical signal through a conductor that is surrounded with a dielectric material having a dielectric constant of two or more, the signal is propagated as an electromagnetic wave through air at a much higher speed across the surface of the integrated circuit. In one embodiment, a radio frequency (RF) signal is passed into an integrated circuit package via a transmission line. The transmission line supplies the RF signal to a waveguide-like structure disposed above the integrated circuit inside the package. The RF signal propagates as an electromagnetic wave through air in the waveguide structure across the upper surface of the integrated circuit. Antenna/receiver circuit pairs are disposed at various locations across the surface of the integrated circuit where the signal is to be received and used. Other methods and embodiments are disclosed.

43. 发明授权

US6005829A Method for characterizing interconnect timing characteristics 失效
标题翻译：表征互连时序特征的方法
公开(公告)号：US6005829A
公开(公告)日：1999-12-21
申请号：US83892
申请日：1998-05-21
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： G01R27/04 , G01R31/28 , G01R31/30 , G01R31/317 , G01R31/3185 , G04F8/00 , G01R15/12 , G01R27/26
CPC分类号： G01R31/31725 , G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/3016 , G01R31/318516
摘要： A reference ring oscillator circuit (RROC) is used to determine timing characteristics of a test interconnect structure in an integrated circuit. The RROC includes an odd number of inverters coupled together in a ring manner and has defined test segments at which a test interconnect can be loaded. Reference timing characteristics of the unloaded RROC are determined according to a calibration method including the steps of: (a) directly measuring signal propagation delay through each segment of the RROC; (b) modeling each test segment using an RC tree type reference circuit model having reference elements; (c) simulating the reference circuit model to provide a functional relationship between two reference capacitors; (d) defining upper and lower bounds for propagation delay through the test segment in terms of the reference elements; (e) determining values for the reference capacitor elements; and (f) measuring a reference frequency of oscillation of the unloaded RROC. After calibration, a test frequency of oscillation of the RROC is measured while a test interconnect structure is loaded onto a test segment. The period of the reference frequency is subtracted from the period of the test frequency. A time difference between the two periods is attributed to increased signal propagation delay through the RROC as a result of loading the test interconnect structure onto the test segment. Based on the measured time difference and determined reference timing characteristics of the test segment, timing characteristics of the test interconnect structure are determined.
摘要翻译：参考环形振荡器电路（RROC）用于确定集成电路中的测试互连结构的定时特性。 RROC包括以环形方式耦合在一起的奇数个反相器，并具有可以加载测试互连的定义的测试段。根据校准方法确定无负载RROC的参考定时特性，包括以下步骤：（a）直接测量RROC的每个段的信号传播延迟; （b）使用具有参考元素的RC树型参考电路模型对每个测试段进行建模; （c）模拟参考电路模型以提供两个参考电容器之间的功能关系; （d）根据参考元素定义通过测试段的传播延迟的上限和下限; （e）确定参考电容器元件的值; 和（f）测量无负载RROC的参考振荡频率。在校准之后，测量RROC的测试频率，同时将测试互连结构加载到测试段上。从测试频率的周期中减去参考频率的周期。两个周期之间的时间差归因于作为将测试互连结构加载到测试段上的结果，通过RROC增加的信号传播延迟。基于所测量的时间差和测试段的确定的参考定时特性，确定测试互连结构的定时特性。

44. 发明授权

US5790479A Method for characterizing interconnect timing characteristics using reference ring oscillator circuit 失效
标题翻译：使用参考环形振荡器电路来表征互连定时特性的方法
公开(公告)号：US5790479A
公开(公告)日：1998-08-04
申请号：US710465
申请日：1996-09-17
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： G01R27/04 , G01R31/28 , G01R31/30 , G01R31/317 , G01R31/3185 , G04F8/00 , G01R15/12
CPC分类号： G01R31/31725 , G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/3016 , G01R31/318516
摘要： A reference ring oscillator circuit (RROC) is used to determine timing characteristics of a test interconnect structure in an integrated circuit. The RROC includes an odd number of inverters coupled together in a ring manner and has defined test segments at which a test interconnect can be loaded. Reference timing characteristics of the unloaded RROC are determined according to a calibration method including the steps of: (a) directly measuring signal propagation delay through each segment of the RROC; (b) modeling each test segment using an RC tree type reference circuit model having reference elements; (c) simulating the reference circuit model to provide a functional relationship between two reference capacitors; (d) defining upper and lower bounds for propagation delay through the test segment in terms of the reference elements; (e) determining values for the reference capacitor elements; and (f) measuring a reference frequency of oscillation of the unloaded RROC.
摘要翻译：参考环形振荡器电路（RROC）用于确定集成电路中的测试互连结构的定时特性。 RROC包括以环形方式耦合在一起的奇数个反相器，并具有可以加载测试互连的定义的测试段。根据校准方法确定无负载RROC的参考定时特性，包括以下步骤：（a）直接测量RROC的每个段的信号传播延迟; （b）使用具有参考元素的RC树型参考电路模型对每个测试段进行建模; （c）模拟参考电路模型以提供两个参考电容器之间的功能关系; （d）根据参考元素定义通过测试段的传播延迟的上限和下限; （e）确定参考电容器元件的值; 和（f）测量无负载RROC的参考振荡频率。

45. 发明授权

US08564225B1 Accelerator on a chip having a grid and plate cell 有权
标题翻译：具有栅格和板单元的芯片上的加速器
公开(公告)号：US08564225B1
公开(公告)日：2013-10-22
申请号：US13585832
申请日：2012-08-15
申请人： Kim L. Hailey , Robert O. Conn
发明人： Kim L. Hailey , Robert O. Conn
IPC分类号： H05H7/00
CPC分类号： H01J37/302 , B82Y10/00 , B82Y40/00 , H01J37/045 , H01J37/08 , H01J37/3007 , H01J37/3177 , H01J2237/002 , H01J2237/0432 , H01J2237/0437 , H01J2237/04735 , H01J2237/061 , H01J2237/0802 , H01J2237/0815 , H01J2237/20228 , H01J2237/30416 , H01J2237/31749 , H01J2237/31755 , H01J2237/31766 , H05H9/042
摘要： An accelerator assembly includes an acceleration channel that passes in a straight line through a plurality of accelerator cells. Each cell includes an acceleration region and a drift region. The drift region includes a high voltage plate and a grid electrode, where the grid electrode is disposed between the high voltage plate and the channel. In each cell, a large DC voltage is present on the high voltage plate. A voltage on the grid electrode is controlled such that at a first time an ion in the channel is attracted toward the high voltage plate, and such that at a second time the ion is shielded and is not attracted toward the high voltage plate. In one specific example, the assembly is part of a Direct Write On Wafer (DWOW) printing system that can direct write an image onto a 300 mm diameter wafer in one minute.
摘要翻译：加速器组件包括加速通道，其以直线通过多个加速器单元。每个单元包括加速区和漂移区。漂移区域包括高压板和栅格电极，其中格栅电极设置在高压板和通道之间。在每个电池中，在高压板上存在大的直流电压。控制栅电极上的电压，使得第一次将通道中的离子吸引到高压板，并且在第二时间离子被屏蔽并且不被吸引到高压板。在一个具体的示例中，组件是直接写入晶圆（DWOW）打印系统的一部分，可以在一分钟内直接将图像写入到300mm直径的晶片上。

46. 发明授权

US08541884B2 Through-substrate via having a strip-shaped through-hole signal conductor 失效
标题翻译：通孔具有带状通孔信号导体
公开(公告)号：US08541884B2
公开(公告)日：2013-09-24
申请号：US13535377
申请日：2012-06-28
申请人： Robert O. Conn , David F. Myers , Daniel S. Stevenson
发明人： Robert O. Conn , David F. Myers , Daniel S. Stevenson
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L23/5384 , H01L25/0655 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311 , H01L2924/157
摘要： A TSV structure suitable for high speed signal transmission includes a metal strip portion that extends through a long and small diameter hole in a substrate. In one example, the metal strip portion is formed by laser ablating away portions of a metal sheath that lines a cylindrical sidewall of the hole, thereby leaving a longitudinal section of metal that is the metal strip portion. A second metal strip portion, that extends in a direction perpendicular to the hole axis, is contiguous with the metal strip portion that extends through the hole such that the two metal strip portions together form a single metal strip. Throughout its length, the single metal strip has a uniform width and thickness and therefore can have a controlled and uniform impedance. In some embodiments, multiple metal strips pass through the same TSV hole. In some embodiments, the structure is a coaxial TSV.
摘要翻译：适用于高速信号传输的TSV结构包括延伸穿过衬底中长而小直径的孔的金属条部分。在一个实例中，金属带部分通过激光烧蚀来形成，该金属护套的一部分沿着孔的圆柱形侧壁排列，从而留下作为金属条部分的金属的纵向截面。沿与孔轴垂直的方向延伸的第二金属带部分与延伸穿过孔的金属条部分邻接，使得两个金属带部分一起形成单个金属带。在其整个长度上，单个金属条具有均匀的宽度和厚度，因此可以具有受控且均匀的阻抗。在一些实施例中，多个金属条通过相同的TSV孔。在一些实施例中，该结构是同轴TSV。

47. 发明授权

US08541757B1 Accelerator on a chip having a cold ion source 有权
标题翻译：具有冷离子源的芯片上的加速器
公开(公告)号：US08541757B1
公开(公告)日：2013-09-24
申请号：US13585829
申请日：2012-08-14
申请人： Kim L. Hailey , Robert O. Conn
发明人： Kim L. Hailey , Robert O. Conn
IPC分类号： H01H1/54
CPC分类号： H01J37/3174 , B82Y10/00 , B82Y40/00 , H01J37/08 , H01J37/09 , H01J37/3177 , H01J2237/0437 , H01J2237/0802 , H01J2237/31755
摘要： An assembly includes a cold ion source and a chip. The cold ion source is fixed to the chip so that ions from the ion source can enter an acceleration channel in the chip. In one specific example, the ion source includes an ion exchange membrane that produces cold ions in that the ions as produced have an energy of less than 30 eV. The chip includes a substrate (such as a semiconductor substrate or a glass substrate) and a dielectric layer disposed on substrate, where the acceleration channel is a channel formed into the dielectric layer. In one specific example, the assembly is part of a Direct Write On Wafer (DWOW) printing system. The DWOW printing system is useful in semiconductor processing in that it can direct write an image onto a 300 mm diameter wafer in one minute.
摘要翻译：组件包括冷离子源和芯片。冷离子源固定在芯片上，使得离子源的离子能够进入芯片中的加速通道。在一个具体实例中，离子源包括产生冷离子的离子交换膜，因为产生的离子具有小于30eV的能量。该芯片包括衬底（诸如半导体衬底或玻璃衬底）以及设置在衬底上的电介质层，其中加速通道是形成在电介质层中的通道。在一个具体示例中，组件是直接写入晶圆（DWOW）打印系统的一部分。 DWOW打印系统在半导体处理中是有用的，因为它可以在一分钟内直接将图像写入到300mm直径的晶片上。

48. 发明授权

US08519644B1 Accelerator having acceleration channels formed between covalently bonded chips 有权
标题翻译：具有在共价键合芯片之间形成加速通道的加速器
公开(公告)号：US08519644B1
公开(公告)日：2013-08-27
申请号：US13585833
申请日：2012-08-15
申请人： Kim L. Hailey , Robert O. Conn
发明人： Kim L. Hailey , Robert O. Conn
IPC分类号： H04H7/00
CPC分类号： H05H7/00 , H01L24/01 , H01L2924/12042 , H01L2924/1306 , H01L2924/15787 , H01L2924/15788 , H05H7/06 , H05H9/00 , H05H15/00 , H01L2924/00
摘要： An accelerator assembly includes a first chip and a second chip. An acceleration channel is formed into a surface of a first side of the first chip. The first side of the first chip is covalently bonded to a first side of the second chip such that the channel is a tubular void between the first and second chips. The channel has a tubular inside sidewall surface, substantially no portion of which is a metal surface. The channel has length-to-width ratio greater than five, and a channel width less than one micron. There are many substantially identical channels that extend in parallel between the first and second chips. In one specific example, the assembly is part of a Direct Write On Wafer (DWOW) printing system. The DWOW printing system is useful in semiconductor processing in that it can direct write an image onto a 300 mm diameter wafer in one minute.
摘要翻译：加速器组件包括第一芯片和第二芯片。加速通道形成在第一芯片的第一侧的表面上。第一芯片的第一侧共价键合到第二芯片的第一侧，使得通道是第一和第二芯片之间的管状空隙。通道具有管状内侧壁表面，其基本上没有其一部分是金属表面。通道的长宽比大于5，通道宽度小于1微米。在第一和第二芯片之间并行延伸有许多基本相同的通道。在一个具体示例中，组件是直接写入晶圆（DWOW）打印系统的一部分。 DWOW打印系统在半导体处理中是有用的，因为它可以在一分钟内直接将图像写入到300mm直径的晶片上。

49. 发明授权

US08062968B1 Interposer for redistributing signals 有权
标题翻译：用于重新分配信号的插件
公开(公告)号：US08062968B1
公开(公告)日：2011-11-22
申请号：US12487855
申请日：2009-06-19
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L21/00
CPC分类号： H01L23/055 , H01L23/49822 , H01L23/49827 , H01L23/50 , H01L23/642 , H01L24/16 , H01L24/81 , H01L2224/16227 , H01L2224/16235 , H01L2224/1624 , H01L2224/16265 , H01L2224/73257 , H01L2224/81191 , H01L2224/81192 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/12036 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H01L2924/15787 , H01L2924/16152 , H01L2924/19041 , H01L2924/19043 , H01L2924/19103 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , Y10S257/924 , H01L2924/00
摘要： A capacitive interposer (caposer) is disposed inside an integrated circuit package between a die and an inside surface of the package. Conductive layers within the caposer constitute a bypass capacitor. In a through-hole caposer, micro-bumps on the die pass through through-holes in the caposer and contact corresponding landing pads on the package. As they pass through the caposer, power and ground micro-bumps make contact with the plates of the bypass capacitor. In a via caposer, power and ground micro-bumps on the die are coupled to power and ground landing pads on the package as well as to the plates of the bypass capacitor by power and ground vias that extend through the caposer. In signal redistribution caposer, conductors within the caposer redistribute signals between die micro-bumps and package landing pads. In an impedance matching caposer, termination structures within the caposer provide impedance matching to a printed circuit board trace.
摘要翻译：电容插入器（caposer）设置在芯片与封装的内表面之间的集成电路封装内。钳口内的导电层构成旁路电容器。在通孔捕获器中，裸片上的微型凸块通过钳口中的通孔并与封装上相应的着陆焊盘接触。当电容和接地微型突起通过电容器时，接触旁路电容器的电极。在通孔容量中，芯片上的电源和接地微型突起通过电源和接地通孔连接到封装上的电源和接地焊盘以及旁路电容器的板。在信号再分配电容器中，钳位器内的导体在管芯微突起和封装着陆焊盘之间重新分配信号。在阻抗匹配钳位器中，钳位器内的端接结构为印刷电路板迹线提供阻抗匹配。

50. 发明申请

US20110266034A1 Preventing breakage of long metal signal conductors on semiconductor substrates 有权
标题翻译：防止半导体基板上的长金属信号导体断裂
公开(公告)号：US20110266034A1
公开(公告)日：2011-11-03
申请号：US13135510
申请日：2011-07-07
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H05K1/02 , H01L21/28
CPC分类号： H05K7/20927 , H01L23/473 , H01L23/481 , H01L24/05 , H01L24/29 , H01L24/32 , H01L25/0652 , H01L2224/0557 , H01L2224/29101 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/00 , H01L2224/05552
摘要： An apparatus includes a volume of insulator disposed over a top surface of a semiconductor substrate, a tube of soft dielectric, and a metal conductor. The insulator has a hardness of more than approximately three gigaPascals (gPa) and the soft dielectric has a hardness of less than three gPa. The tube of soft dielectric and the metal conductor are both embedded within the volume of insulator. The tube defines a central volume and the metal conductor extends in a direction through the central volume for a distance of at least one inch. The metal conductor is encircled by the soft dielectric when the apparatus is viewed in a cross-sectional plane perpendicular to the direction. The metal conductor may include a plurality of bend portions. The metal conductor does not break when the apparatus is temperature cycled over a range from zero to eighty five degrees Celsius.
摘要翻译：一种装置包括设置在半导体衬底的顶表面上的绝缘体体积，软电介质管和金属导体。绝缘体具有大于约3千兆帕（gPa）的硬度，软电介质具有小于3gPa的硬度。软电介质管和金属导体都嵌入在绝缘体的体积内。管限定中心体积，并且金属导体沿着穿过中心体积的方向延伸至少一英寸的距离。当在垂直于该方向的横截面中观察装置时，金属导体被软电介质环绕。金属导体可以包括多个弯曲部分。当设备在零度至摄氏度摄氏八十度的范围内温度循环时，金属导体不会断裂。

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