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41. 发明申请

US20090045836A1 ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE ENGINEERING CHANGE 审中-公开
标题翻译：柔性逻辑块的ASIC逻辑库和使用工程变更的方法
公开(公告)号：US20090045836A1
公开(公告)日：2009-02-19
申请号：US11838929
申请日：2007-08-15
申请人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
发明人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
IPC分类号： H03K19/173 , G06F17/50
CPC分类号： G06F17/505
摘要： A chip design methodology and an integrated circuit chip. The methodology includes providing a plurality of logic gates in a net list, wherein each of the logic gates comprises at least one spare input, synthesizing the net list, and connecting the spare inputs for performing an engineering change late in the design process.
摘要翻译：芯片设计方法和集成电路芯片。该方法包括在网络列表中提供多个逻辑门，其中每个逻辑门包括至少一个备用输入，合成网络列表，以及在设计过程的后期连接用于执行工程变更的备用输入。

42. 发明授权

US07065602B2 Circuit and method for pipelined insertion 失效
标题翻译：流水线插入的电路和方法
公开(公告)号：US07065602B2
公开(公告)日：2006-06-20
申请号：US10604205
申请日：2003-07-01
申请人： Robert S. Horton , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Sebastian T. Ventrone
发明人： Robert S. Horton , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Sebastian T. Ventrone
IPC分类号： G06F13/14
CPC分类号： G06F13/4247 , H04L25/14
摘要： The invention transmits data on an integrated circuit chip by first propagating a first data portion along a first segment of a segmented data line and then propagating the first data portion along a second segment of the segmented data line and simultaneously propagating a second data portion along the first segment of the segmented data line. The invention breaks a single data transmission into such different data portions and later reassembles the different data portions back into the single data transmission after all of the different data portions have been individually transmitted along all portions of the segmented data line
摘要翻译：本发明通过首先沿着分段数据线的第一段传播第一数据部分，然后沿着分段数据线的第二段传播第一数据部分并同时沿第二数据部分传播第二数据部分分段数据线的第一段。本发明将单个数据传输中断到这样的不同数据部分，并且随后将所有不同数据部分已经沿着分段数据线的所有部分单独发送，将不同的数据部分重新组合成单个数据传输

43. 发明授权

US06075415A Digital frequency multiplier 失效
标题翻译：数字倍频器
公开(公告)号：US06075415A
公开(公告)日：2000-06-13
申请号：US224761
申请日：1999-01-04
申请人： David W. Milton , Marc R. Turcotte , Charles B. Winn
发明人： David W. Milton , Marc R. Turcotte , Charles B. Winn
IPC分类号： H03L7/099 , H03L7/181
CPC分类号： H03L7/0995 , H03L7/0997 , H03L7/181
摘要： A digital frequency multiplier is provided that continues to adjust its multiplied frequency after the desired multiplied frequency is reached, that can be tested during operation and that is easily scalable. The digital frequency multiplier comprises a frequency detector, a frequency adjuster and a ring oscillator (RO). The frequency detector is configured for receiving a reference frequency and an RO output frequency, and for continuously monitoring a difference between the reference frequency and the RO output frequency. Based on the continuously monitored difference, the frequency detector continuously outputs an adjusting signal to the frequency adjuster. In response thereto, the frequency adjuster outputs selection data to the RO that adjusts the oscillation frequency of the RO, and thus the multiplied frequency of the digital frequency multiplier. Testable and growable logic circuitry are provided within the RO that allow the digital frequency multiplier to be tested during operation and easily scaled.
摘要翻译：提供数字倍频器，在达到期望的倍频之后继续调整其倍频，可在操作期间进行测试，并且易于扩展。数字倍频器包括频率检测器，频率调节器和环形振荡器（RO）。频率检测器被配置为用于接收参考频率和RO输出频率，并且用于连续监视参考频率和RO输出频率之间的差。基于持续监测的差异，频率检测器连续向频率调节器输出调整信号。响应于此，频率调节器将选择数据输出到RO，该RO调整RO的振荡频率，从而输出数字倍频器的倍频。在RO内提供可测试和可生长的逻辑电路，允许在运行期间测试数字倍频器并轻松缩放。

44. 发明授权

US08754696B2 Ring oscillator 有权
标题翻译：环形振荡器
公开(公告)号：US08754696B2
公开(公告)日：2014-06-17
申请号：US13558498
申请日：2012-07-26
申请人： Margaret R. Charlebois , Rashmi D. Chatty , Christopher D. Hanudel , Robert D. Herzl , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Matthew P. Szafir , Tad J. Wilder
发明人： Margaret R. Charlebois , Rashmi D. Chatty , Christopher D. Hanudel , Robert D. Herzl , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Matthew P. Szafir , Tad J. Wilder
IPC分类号： H03H11/26
CPC分类号： H03K3/0315
摘要： Aspects of the invention provide a circuit structure that automatically monitors a plurality of ring oscillators and dynamically selects the fastest or the slowest ring oscillator for feedback into the plurality of ring oscillators. In one embodiment, a circuit includes: a plurality of delay elements, each delay element associated with a ring oscillator; a first logic gate for receiving outputs of each of the delay elements; a second logic gate for receiving outputs of each of the delay elements; and a multiplexer for receiving an output of the first logic gate and an output of the second logic gate and choosing one of the outputs, wherein a selection for the multiplexer is based on an output of the multiplexer. To select the fastest ring oscillator, a second multiplexer is provided.
摘要翻译：本发明的方面提供了一种电路结构，其自动监测多个环形振荡器并且动态地选择最快或最慢的环形振荡器用于反馈到多个环形振荡器中。在一个实施例中，电路包括：多个延迟元件，每个延迟元件与环形振荡器相关联; 用于接收每个延迟元件的输出的第一逻辑门; 第二逻辑门，用于接收每个延迟元件的输出; 以及多路复用器，用于接收第一逻辑门的输出和第二逻辑门的输出并选择输出之一，其中多路复用器的选择基于多路复用器的输出。为了选择最快的环形振荡器，提供了第二个多路复用器。

45. 发明授权

US08464199B1 Circuit design using design variable function slope sensitivity 失效
标题翻译：电路设计采用设计变量函数斜率灵敏度
公开(公告)号：US08464199B1
公开(公告)日：2013-06-11
申请号：US13472814
申请日：2012-05-16
申请人： Margaret R. Charlebois , Christopher D. Hanudel , Robert D. Herzl , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Tad J. Wilder
发明人： Margaret R. Charlebois , Christopher D. Hanudel , Robert D. Herzl , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Tad J. Wilder
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/84
摘要： A method for designing an integrated circuit. A computer determines, for one or more paths in a circuit design, for a value of a design variable at which timing closure of the circuit design is achieved, an approximate slope of a function representing path delay as a function of the design variable. When the computer determines that one of the approximate slopes is not within a defined slope range, the computer determines an adjustment direction and an adjustment value based in part on the magnitude by which the slope is not within the defined slope range. The computer changes the circuit design of the path associated with the out-of-range slope, based in part on the adjustment direction and the adjustment value, so as to bring the slope within the defined slope range.
摘要翻译：一种集成电路设计方法。计算机为电路设计中的一个或多个路径确定实现电路设计的定时闭合的设计变量的值，表示作为设计变量的函数的路径延迟的函数的近似斜率。当计算机确定大致斜率中的一个不在限定的斜率范围内时，计算机部分地基于斜率不在所定义的斜率范围内的幅度来确定调整方向和调整值。部分基于调整方向和调整值，计算机改变与超出范围斜率相关联的路径的电路设计，以使斜率在规定的斜率范围内。

46. 发明授权

US08300752B2 Method, circuit, and design structure for capturing data across a pseudo-synchronous interface 有权
标题翻译：用于通过伪同步接口捕获数据的方法，电路和设计结构
公开(公告)号：US08300752B2
公开(公告)日：2012-10-30
申请号：US12192586
申请日：2008-08-15
申请人： Malede W. Berhanu , Christopher D. Hanudel , Mark W. Kuemerle , David W. Milton , Clarence R. Ogilvie , Jack R. Smith
发明人： Malede W. Berhanu , Christopher D. Hanudel , Mark W. Kuemerle , David W. Milton , Clarence R. Ogilvie , Jack R. Smith
IPC分类号： H04L7/00
CPC分类号： H04L7/0012
摘要： A structure for performing cross-chip communication with mesochronous clocks. The structure includes: a data delay line; a remote clock delay line; a structure that captures at least one value of a state of a delayed remote clock signal on the remote clock delay line; and a control that influences a delay associated with the data delay line and the remote clock delay line.
摘要翻译：用于与中间时钟执行跨芯片通信的结构。该结构包括：数据延迟线; 一个远程时钟延时线; 在远程时钟延迟线上捕获延迟的远程时钟信号的状态的至少一个值的结构; 以及影响与数据延迟线和远程时钟延迟线相关联的延迟的控制。

47. 发明申请

US20100194459A1 CIRCUIT AND DESIGN STRUCTURE FOR SYNCHRONIZING MULTIPLE DIGITAL SIGNALS 有权
标题翻译：用于同步多个数字信号的电路和设计结构
公开(公告)号：US20100194459A1
公开(公告)日：2010-08-05
申请号：US12759015
申请日：2010-04-13
申请人： David W. Milton
发明人： David W. Milton
IPC分类号： H03L7/00 , G06F17/50
CPC分类号： H03L7/00 , G06F5/06 , H04L7/033
摘要： Disclosed is a circuit configured to synchronize multiple signals received by one clock domain from a different asynchronous clock domain, when simultaneous movement of the signals between the clock domains is intended. In the circuit multiple essentially identical pipelined signal paths receive digital input signals. XOR gates are associated with each of the signal paths. Each XOR gate monitors activity in a given signal path and controls, directly or indirectly (depending upon the embodiment), advancement of signal processing in the other signal path(s) to ensure that, if warranted, output signals at the circuit output nodes are synchronized. In a two-signal path embodiment, advancement of signal processing in one signal path is triggered, whenever transitioning digital signals are detected within the other signal path. In an n-signal path advancement of signal processing is triggered in all signal paths, whenever transitioning digital signals are detected on at least one signal path.
摘要翻译：公开了一种电路，被配置为当希望在时钟域之间同时移动信号时，将来自不同异步时钟域的一个时钟域接收的多个信号同步。在电路中，多个基本相同的流水线信号路径接收数字输入信号。 XOR门与每个信号路径相关联。每个XOR门监视给定信号路径中的活动并且直接或间接地控制（取决于实施例），在另一个信号路径中提高信号处理，以确保如果有必要，在电路输出节点处的输出信号是同步在双信号路径实施例中，每当在另一个信号路径内检测到转换的数字信号时，触发一个信号路径中的信号处理的提前。无论何时在至少一个信号路径上检测到转换数字信号，在所有信号路径中触发信号处理的n信号通路。

48. 发明申请

US20100040183A1 METHOD, CIRCUIT, AND DESIGN STRUCTURE FOR CAPTURING DATA ACROSS A PSEUDO-SYNCHRONOUS INTERFACE 有权
标题翻译：用于通过PSEUDO-SYNCHRONOUS接口捕获数据的方法，电路和设计结构
公开(公告)号：US20100040183A1
公开(公告)日：2010-02-18
申请号：US12192586
申请日：2008-08-15
申请人： Malede W. Berhanu , Christopher D. Hanudel , Mark W. Kuemerle , David W. Milton , Clarence R. Ogilvie , Jack R. Smith
发明人： Malede W. Berhanu , Christopher D. Hanudel , Mark W. Kuemerle , David W. Milton , Clarence R. Ogilvie , Jack R. Smith
IPC分类号： H04L7/00
CPC分类号： H04L7/0012
摘要： A structure for performing cross-chip communication with mesochronous clocks. The structure includes: a data delay line; a remote clock delay line; a structure that captures at least one value of a state of a delayed remote clock signal on the remote clock delay line; and a control that influences a delay associated with the data delay line and the remote clock delay line.
摘要翻译：用于与中间时钟执行跨芯片通信的结构。该结构包括：数据延迟线; 一个远程时钟延时线; 在远程时钟延迟线上捕获延迟的远程时钟信号的状态的至少一个值的结构; 以及影响与数据延迟线和远程时钟延迟线相关联的延迟的控制。

49. 发明申请

US20100017773A1 Method for Minimizing Impact of Design Changes For Integrated Circuit Designs 有权
标题翻译：集成电路设计中设计变更影响最小化的方法
公开(公告)号：US20100017773A1
公开(公告)日：2010-01-21
申请号：US12173222
申请日：2008-07-15
申请人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
发明人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method is provided for updating an existing netlist to reflect a design change. A design incorporating the design change and the existing netlist are provided to a synthesis tool. The design and the existing netlist are processed with the synthesis tool reusing logic structures from the existing netlist. A result is generated by the synthesis tool including the existing netlist and a new portion of a netlist reflecting the design change.
摘要翻译：提供了一种用于更新现有网表以反映设计变更的方法。将设计更改和现有网表的设计提供给综合工具。设计和现有的网表通过从现有网表重用逻辑结构的综合工具进行处理。综合工具产生的结果包括现有网表和反映设计变更的网表的新部分。

50. 发明申请

US20090183134A1 DESIGN STRUCTURE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC BLOCK LOGIC FOR EASY ENGINEERING CHANGES 有权
标题翻译：用于识别和实现灵活逻辑块逻辑的设计结构，易于工程改造
公开(公告)号：US20090183134A1
公开(公告)日：2009-07-16
申请号：US12054835
申请日：2008-03-25
申请人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
发明人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A design structure for identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.
摘要翻译：用于识别工程可变逻辑的设计结构，以及用灵活的逻辑块（FLB）替换所识别的工程可变逻辑。该设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。

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