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    • 41. 发明申请
    • Wafer scale integration of electroplate 3D structures using successive lithography, electroplated sacrifical layers, and flip-chip bonding
    • 使用连续光刻,电镀牺牲层和倒装芯片接合的电镀三维结构的晶圆级整合
    • US20060134829A1
    • 2006-06-22
    • US11012597
    • 2004-12-16
    • Michel RosaEric Peeters
    • Michel RosaEric Peeters
    • H01L21/48H01L21/50
    • B41J2/161B41J2/1625B41J2/1628B41J2/164
    • Wafer scale fabrication of three dimentional substantially enclosed structures on a MEMS/IC die use a combination of electrodeposition of structural and sacrificial layers and flip-chip alignment and bonding technology. A first wafer contains a die with MEMS and/or IC structures. On this MEMS/IC processed die, a first three dimensional structural component is formed using standard lithographic processes and electrodeposition of a structural layer. A second sacrificial wafer is separately processed using similar lithographic and electrodeposition processes to form a corresponding second three dimensional structural component. The wafers are placed in a flip-chip bonder and aligned. Once aligned, the structural components are bonded together. The bonded wafers are then removed from the bonder and the second sacrificial wafer substrate removed. The resultant die includes a three dimensional structural component with a substantially enclosed cavity as well as MEMS and IC elements.
    • 在MEMS / IC芯片上的三维基本封闭结构的晶片尺寸制造使用结合和牺牲层的电沉积和倒装芯片对准和结合技术的组合。 第一晶片包含具有MEMS和/或IC结构的管芯。 在该MEMS / IC处理的模具上,使用标准光刻工艺和结构层的电沉积形成第一三维结构部件。 使用类似的光刻和电沉积工艺分别处理第二牺牲晶片以形成对应的第二三维结构部件。 将晶片放置在倒装芯片接合器中并对齐。 一旦对准,结构部件结合在一起。 然后将粘合的晶片从粘合剂上除去,并且去除第二牺牲晶片衬底。 所得模具包括具有基本上封闭的空腔以及MEMS和IC元件的三维结构部件。