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41. 发明申请

US20090327641A1 Dynamic Allocation of a Buffer Across Multiple Clients in a Threaded Processor 有权
标题翻译：螺纹处理器中多个客户端的缓冲区的动态分配
公开(公告)号：US20090327641A1
公开(公告)日：2009-12-31
申请号：US12553216
申请日：2009-09-03
申请人： Thomas A. Piazza
发明人： Thomas A. Piazza
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F9/5016 , G06F12/023
摘要： A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory may be redistributed among a second set of functions in a second pipeline without waiting for the first set of functions to be flushed of data.
摘要翻译：一种方法可以包括在第一流水线中的第一组函数中分配存储器中的地址范围。第一管道中的第一组功能可以使用地址范围对数据进行操作。可以在第二流水线中的第二组功能中重新分配存储器中的不同范围的地址，而不等待第一组功能被刷新数据。

42. 发明授权

US07614054B2 Behavioral model based multi-threaded architecture 失效
标题翻译：基于行为模型的多线程架构
公开(公告)号：US07614054B2
公开(公告)日：2009-11-03
申请号：US10750090
申请日：2003-12-31
申请人： Hong Jiang , Thomas A. Piazza
发明人： Hong Jiang , Thomas A. Piazza
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087 , G06F9/4843
摘要： Multiple parallel passive threads of instructions coordinate access to shared resources using “active” and “proactive” semaphores. The active semaphores send messages to execution and/or control circuitry to cause the state of a thread to change. A thread can be placed in an inactive state by a thread scheduler in response to an unresolved dependency, which can be indicated by a semaphore. A thread state variable corresponding to the dependency is used to indicate that the thread is in inactive mode. When the dependency is resolved a message is passed to control circuitry causing the dependency variable to be cleared. In response to the cleared dependency variable the thread is placed in an active state. Execution can proceed on the threads in the active state. A proactive semaphore operates in a similar manner except that the semaphore is configured by the thread dispatcher before or after the thread is dispatched to the execution circuitry for execution.
摘要翻译：指令的多个并行被动线程使用“主动”和“主动”信号量协调对共享资源的访问。主动信号量将消息发送到执行和/或控制电路，以使线程的状态发生变化。线程调度程序可以响应未解决的依赖关系将线程置于无效状态，这可以由信号量指示。与依赖关系对应的线程状态变量用于指示线程处于非活动模式。当依赖关系被解析时，消息被传递给控制电路，导致依赖变量被清除。响应于清除的依赖变量，线程处于活动状态。处于活动状态的线程可执行。主动信号量以类似的方式运行，除了信号量由线程分派器在线程发送到执行电路执行之前或之后配置。

43. 发明授权

US07526124B2 Match MSB digital image compression 有权
标题翻译：匹配MSB数字图像压缩
公开(公告)号：US07526124B2
公开(公告)日：2009-04-28
申请号：US11712046
申请日：2007-02-27
申请人： Michael K. Dwyer , Thomas A. Piazza
发明人： Michael K. Dwyer , Thomas A. Piazza
IPC分类号： G06K9/36 , G06K9/46 , G06K9/00
CPC分类号： H04N19/184 , H04N19/124 , H04N19/156 , H04N19/186 , H04N19/50
摘要： Methods, apparatus and computer readable medium are described that compress and/or decompress a digital image in a lossless or a lossy manner. In some embodiments, a display controller may compress a digital image by generating a symbol for each pel of the digital image. In particular, the symbol may represent a pel via a match vector and a channel error vector. The match vector may indicate which quantized channels of the pel matched quantized channels of a previous pel. Further, the channel error vector may comprise a lossless or lossy channel for each quantized channel of the pel that did not match a corresponding quantized channel of the previous pel. The channel error may also comprise a lossless or lossy channel error for each quantized channel of the pel that matched a corresponding quantized channel of the previous pel.
摘要翻译：描述了以无损或有损的方式对数字图像进行压缩和/或解压缩的方法，装置和计算机可读介质。在一些实施例中，显示控制器可以通过为数字图像的每个像素生成符号来压缩数字图像。特别地，符号可以经由匹配向量和信道误差向量来表示像素。匹配向量可以指示先前像素的像素匹配量化通道的哪个量化通道。此外，信道误差向量可以包括与先前像素的对应量化信道不匹配的像素的每个量化信道的无损或有损信道。信道误差还可以包括与先前像素的相应量化信道匹配的像素的每个量化信道的无损或有损信道误差。

44. 发明申请

US20080162522A1 Methods and apparatuses for compaction and/or decompaction 审中-公开
标题翻译：用于压实和/或解压缩的方法和装置
公开(公告)号：US20080162522A1
公开(公告)日：2008-07-03
申请号：US11648260
申请日：2006-12-29
申请人： Guei-Yuan Lueh , Hong Jiang , Andrew T. Riffel , Bixia Zheng , Chu-Cheow Lim , Milind Girkar , David C. Sehr , Thomas A. Piazza
发明人： Guei-Yuan Lueh , Hong Jiang , Andrew T. Riffel , Bixia Zheng , Chu-Cheow Lim , Milind Girkar , David C. Sehr , Thomas A. Piazza
IPC分类号： G06F17/30
CPC分类号： G06F8/4434 , G06F8/447 , G06F9/30036 , G06F9/30156 , G06F9/30167 , G06F9/30178 , G06F9/3853
摘要： In some embodiments, a data structure may be received in a first processing system. The data structure may represent a plurality of instructions for a second processing system. For at least one instruction of the plurality of instructions, a determination may be made as to whether the instruction can be replaced by a compact instruction for the second processing system. A compact instruction may be generated if the instruction can be replaced by a compact instruction. In some embodiments, an instruction may be received in a processing system. A determination may be made as to whether the instruction is a compact instruction. A decompacted instruction may be generated if the instruction is a compact instruction.
摘要翻译：在一些实施例中，可以在第一处理系统中接收数据结构。数据结构可以表示用于第二处理系统的多个指令。对于多个指令中的至少一个指令，可以确定该指令是否可以由第二处理系统的紧凑指令代替。如果可以用紧凑指令代替指令，则可能会产生紧凑指令。在一些实施例中，可以在处理系统中接收指令。可以确定该指令是否是紧凑指令。如果指令是紧凑指令，则可能会生成解压缩指令。

45. 发明授权

US06710784B1 Method and apparatus for performing a vertical scale filter function in a graphics device using a single line buffer 有权
标题翻译：在使用单行缓冲器的图形装置中执行垂直刻度滤波功能的方法和装置
公开(公告)号：US06710784B1
公开(公告)日：2004-03-23
申请号：US09470101
申请日：1999-12-21
申请人： Thomas A. Piazza
发明人： Thomas A. Piazza
IPC分类号： G09G500
CPC分类号： G09G5/373 , G09G2340/0407
摘要： An embodiment of a graphics device that performs a vertical scale filter function using a single line buffer is disclosed. The graphics device includes a line buffer and a vertical scale filter function unit that produces an output of blended data. The line buffer stores the output of blended data and the vertical scale filter uses a next line of display data and a line of blended data stored in the line buffer to produce the output of blended data.
摘要翻译：公开了使用单行缓冲器执行垂直缩放滤波功能的图形装置的实施例。图形装置包括线缓冲器和产生混合数据输出的垂直刻度滤波器功能单元。行缓冲器存储混合数据的输出，垂直比例滤波器使用下一行显示数据和存储在行缓冲器中的一行混合数据来产生混合数据的输出。

46. 发明授权

US06639598B2 Method and apparatus for effective level of detail selection 失效
标题翻译：有效的细节选择水平的方法和装置
公开(公告)号：US06639598B2
公开(公告)日：2003-10-28
申请号：US09735037
申请日：2000-12-12
申请人： Thomas A. Piazza , Michael Mantor , Ralph Clayton Taylor , Val Gene Cook
发明人： Thomas A. Piazza , Michael Mantor , Ralph Clayton Taylor , Val Gene Cook
IPC分类号： G06T1700
CPC分类号： G06T15/04
摘要： Method and apparatus for rendering texture to an object to be displayed on a pixel screen display. This technique makes use of linear interpolation between perspectively correct texture address to calculate rates of change of individual texture addresses components to determine a selection of the correct LOD map to use and intermediate texture addresses for pixels of the object between the perspectively correct addresses. The method first determines perspectively correct texture address values associated with four corners of a predefined span or grid of pixels. Then, a linear interpolation technique is implemented to calculate a rate of change of texture address components in the screen x and y directions for pixels between the perspectively bound span corners. This linear interpolation technique is performed in both screen directions to thereby create a potentially unique level of detail value for each pixel, which is then used as an index to select the correct pre-filtered LOD texture map. When mapping an individually determined LOD value per pixel, the effect of producing undesirable artifacts that may appear if a single LOD for an entire span or polygon is used, is obviated.
摘要翻译：用于将纹理渲染到要在像素屏幕显示上显示的对象的方法和装置。该技术利用透视正确的纹理地址之间的线性内插来计算单个纹理地址分量的变化率，以确定正确的LOD图的使用选择，以及在透视正确的地址之间对象的像素的中间纹理地址。该方法首先确定与预定义跨度或像素网格的四个角相关联的透视正确的纹理地址值。然后，实现线性插值技术，以计算在透视边界角之间的像素的屏幕x和y方向上的纹理地址分量的变化率。这种线性插值技术在两个屏幕方向上执行，从而为每个像素创建潜在唯一的细节值级，然后将其用作选择正确的预滤波LOD纹理图的索引。当映射每个像素的单独确定的LOD值时，如果使用整个跨度或多边形的单个LOD，则可能出现产生不期望的伪影的效果。

47. 发明授权

US06191793B1 Method and apparatus for texture level of detail dithering 失效
标题翻译：细节抖动纹理水平的方法和装置
公开(公告)号：US06191793B1
公开(公告)日：2001-02-20
申请号：US09053591
申请日：1998-04-01
申请人： Thomas A. Piazza , Michael Mantor , Ralph Clayton Taylor , Steven Manno
发明人： Thomas A. Piazza , Michael Mantor , Ralph Clayton Taylor , Steven Manno
IPC分类号： G06T1140
CPC分类号： G06T15/04
摘要： A computationally efficient method for minimizing the visible effects of texture LOD transitions across a polygon. The minimization is accomplished by adding a dithering offset value to the LOD value computed for each pixel covered by a graphics primitive to produce a dithered pixel LOD value. The dithering offsets mat be generated from a table look-up based on the location of the pixel within a span of pixels. The dithered pixel LOD value is used to as an index in the selection of a single LOD texture map from which a textured pixel value is retrieved. The range of dithering offset values can be adjusted by modulating the values in the table look-up.
摘要翻译：一种用于最小化跨多边形的纹理LOD转换的可见效果的计算有效的方法。通过向由图形基元覆盖的每个像素计算的LOD值添加抖动偏移值以产生抖动像素LOD值来实现最小化。基于像素跨度内的像素的位置，从表查找生成抖动偏移量。抖动像素LOD值用于选择单个LOD纹理图的索引，从其中检索纹理像素值。可以通过调整表查找中的值来调整抖动偏移值的范围。

48. 发明授权

US6072505A Method and apparatus to efficiently interpolate polygon attributes in two dimensions at a prescribed clock rate 失效
标题翻译：以规定的时钟速率有效地在多维属性中插入多边形属性的方法和装置
公开(公告)号：US6072505A
公开(公告)日：2000-06-06
申请号：US53589
申请日：1998-04-01
申请人： Thomas A. Piazza , R. Scott Hartog , Michael Mantor , Jeffrey D. Potter , Ralph Clayton Taylor , Michael A. Mang
发明人： Thomas A. Piazza , R. Scott Hartog , Michael Mantor , Jeffrey D. Potter , Ralph Clayton Taylor , Michael A. Mang
IPC分类号： G06T3/40 , G06T1/00 , G06F15/00
CPC分类号： G06T3/403
摘要： A rasterizer comprised of a bounding box calculator, a plane converter, a windower, and incrementers. For each polygon to be processed, a bounding box calculation is performed which determines the display screen area, in spans, that totally encloses the polygon and passes the data to the plane converter. The plane converter also receives as input attribute values for each vertex of the polygon. The plane converter computes planar coefficients for each attribute of the polygon, for each of the edges of the polygon. The plane converter unit computes the start pixel center location at a start span and a starting coefficient value at that pixel center. The computed coefficients also include the rate of change or gradient, for each polygon attribute in the x and y directions, respectively. The plane converter also computes line coefficients for each of the edges of the polygon. Line equation values are passed through to the windower where further calculations allow the windower to determine which spans are either covered or intersected by the polygon. The incrementers receive the span coverage data from the windower in addition to receiving planar coefficient values from the plane converter. The incrementers utilize the data from both the windower and plane converter to walk or traverse the polygon in those intersected spans, pixel by pixel. As the incrementer visits each pixel, vertex attribute values are interpolated to each pixel.
摘要翻译：由边界计算器，平面转换器，加窗器和加法器构成的光栅化器。对于要处理的每个多边形，执行边界框计算，其确定完全包围多边形并将数据传递到平面转换器的跨度的显示屏幕区域。平面转换器还接收多边形的每个顶点的输入属性值。平面转换器为多边形的每个边缘计算多边形的每个属性的平面系数。平面转换器单元计算开始跨度处的开始像素中心位置和该像素中心处的起始系数值。所计算的系数也分别包括x和y方向上每个多边形属性的变化率或梯度。平面转换器还为多边形的每个边缘计算线系数。线路方程值被传递到风力发电机，进一步的计算允许风轮确定哪个跨度被多边形覆盖或相交。除了从平面转换器接收平面系数值之外，增量器还接收来自风力发电机的跨距覆盖数据。增量器利用来自两台风力发电机和平面转换器的数据逐行扫描或横穿那些相交的跨度中的多边形。随着增量器访问每个像素，顶点属性值被内插到每个像素。

49. 发明授权

US09035959B2 Technique to share information among different cache coherency domains 有权
标题翻译：在不同的缓存一致性域之间共享信息的技术
公开(公告)号：US09035959B2
公开(公告)日：2015-05-19
申请号：US12057601
申请日：2008-03-28
申请人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
发明人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
IPC分类号： G09G5/36 , G06F12/08 , G06T1/60
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
摘要翻译：一种能够在不同高速缓存一致性域内的代理之间进行信息共享的技术。在一个实施例中，图形设备可以使用由一个或多个处理核心使用的一个或多个高速缓存来存储或读取信息，这些信息可以由一个或多个处理核心以不影响与编程相关的编程和一致性规则的方式来访问图形设备。

50. 发明申请

US20140136797A1 TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS 审中-公开
标题翻译：在不同的高速缓存域中分享信息的技术
公开(公告)号：US20140136797A1
公开(公告)日：2014-05-15
申请号：US14158865
申请日：2014-01-20
申请人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert Farrell , Altug Koker , Opher Kahn
发明人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert Farrell , Altug Koker , Opher Kahn
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
摘要翻译：一种能够在不同高速缓存一致性域内的代理之间进行信息共享的技术。在一个实施例中，图形设备可以使用由一个或多个处理核心使用的一个或多个高速缓存来存储或读取信息，这些信息可以由一个或多个处理核心以不影响与编程相关的编程和一致性规则的方式来访问图形设备。

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