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41. 发明授权

US4617087A Method for differential selective deposition of metal for fabricating metal contacts in integrated semiconductor circuits 失效
标题翻译：用于在集成半导体电路中用于制造金属触点的金属的差分选择性沉积的方法
公开(公告)号：US4617087A
公开(公告)日：1986-10-14
申请号：US780871
申请日：1985-09-27
申请人： Subramanian S. Iyer , Rajiv V. Joshi
发明人： Subramanian S. Iyer , Rajiv V. Joshi
IPC分类号： H01L21/3205 , C23C16/02 , C23C16/04 , C23C16/06 , C23F4/00 , H01L21/28 , H01L21/285 , H01L21/768 , C23F1/02 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/76879 , C23C16/0281 , C23C16/04 , C23C16/06 , C23F4/00 , H01L21/28562
摘要： A deposition technique for forming metal regions on semiconductor substrates, and more particularly to a fabrication method for the differential selective deposition of tungsten for forming tungsten contacts on an integrated circuit chip.Tungsten hexafluoride gas (WF6) is introduced into a deposition chamber containing a silicon substrate with an apertured silicon dioxide mask layer thereon. The exposed Si surfaces on which the selective deposition is to be performed, are first converted to W surfaces by the substitution reaction:2WF6+3Si=2W+3SiF4After the surface has been substituted, the WF.sub.6 is mixed with H.sub.2 as to give deposition of W by partially preferential nucleation on the already converted W surfaces. Then NF.sub.3 is bled into the system and a plasma is struck in the reaction chamber to create a simultaneous etching condition for the tungsten.The amount of NF3 and the plasma power coupled into the chamber are such as to ensure that the SiO.sub.2 surface is kept clean at all times. Thus any nuclei that may be formed on the SiO.sub.2 surface, are immediately cleaned out. Since the deposition rate on the exposed W surfaces is much higher than on the SiO.sub.2 surfaces, there will be net deposition on these areas in spite of the etching action, albeit at a lower rate.
摘要翻译：一种用于在半导体衬底上形成金属区域的沉积技术，更具体地说，涉及用于在集成电路芯片上形成钨触点的钨的差分选择性沉积的制造方法。将六氟化钨气体（WF6）引入到其中具有带孔二氧化硅掩模层的硅衬底的沉积室中。要进行选择性沉积的暴露的Si表面首先通过取代反应转化为W表面：2WF6 + 3Si = 2W + 3SiF4在表面被取代后，将WF6与H 2混合，使沉积 W在已经转化的W表面上部分优先成核。然后将NF3放入系统中，并在反应室中撞击等离子体，以产生钨的同时蚀刻条件。 NF3的量和耦合到腔室中的等离子体功率是确保SiO 2表面始终保持清洁。因此，可以立即清除可能形成在SiO2表面上的任何核。由于暴露的W表面上的沉积速率远高于SiO 2表面上的沉积速率，尽管蚀刻作用仍然存在这些区域上的净沉积，尽管速率较低。

42. 发明授权

US09454629B2 Fet-bounding for fast TCAD-based variation modeling 有权
标题翻译：快速基于TCAD的变异建模
公开(公告)号：US09454629B2
公开(公告)日：2016-09-27
申请号：US13611359
申请日：2012-09-12
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.
摘要翻译：一种用于分析电路的方法包括识别完整设备结构中的一个或多个设备区域。设备区域提供要分析的感兴趣区域。生成代表性地包括一个或多个设备区域的部分设备。通过采用整个装置结构的物理特性来减少部分装置的分析网格。使用处理器来模拟部分设备，以获得代表整个设备结构的感兴趣区域中的设备输出信息。还披露了系统。

43. 发明授权

US08941110B2 E-fuses containing at least one underlying tungsten contact for programming 有权
标题翻译：电子熔丝包含至少一个底层钨触点用于编程
公开(公告)号：US08941110B2
公开(公告)日：2015-01-27
申请号：US13298872
申请日：2011-11-17
申请人： Rajiv V. Joshi , Chih-Chao Yang
发明人： Rajiv V. Joshi , Chih-Chao Yang
IPC分类号： H01L23/525 , H01L23/528 , H01L23/532 , H01L45/00 , H01L27/24 , H01L23/522
CPC分类号： H01L21/768 , H01L23/5226 , H01L23/5256 , H01L23/53257 , H01L27/11206 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1206 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/16 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor structures are provided containing an electronic fuse (E-fuse) that includes a fuse element and at least one underlying tungsten contact that is used for programming the fuse element. In some embodiments, a pair of neighboring tungsten contacts is used for programming the fuse element. In another embodiment, an overlying conductive region can be used in conjunction with one of the underlying tungsten contacts to program the fuse element. In the disclosed structures, the fuse element is in direct contact with upper surfaces of a pair of underlying tungsten contacts. In one embodiment, the semiconductor structures may include an interconnect level located atop the fuse element. The interconnect level has a plurality of conductive regions embedded therein. In other embodiments, the fuse element is located within an interconnect level that is located atop the tungsten contacts.
摘要翻译：提供了包括电子熔丝（E熔丝）的半导体结构，其包括用于编程熔丝元件的熔丝元件和至少一个下层钨触点。在一些实施例中，使用一对相邻的钨触点来编程熔丝元件。在另一个实施例中，覆盖的导电区域可与下面的钨触点中的一个结合使用以对熔丝元件进行编程。在所公开的结构中，熔丝元件与一对底层钨触点的上表面直接接触。在一个实施例中，半导体结构可以包括位于熔丝元件顶部的互连级。互连电平具有嵌入其中的多个导电区域。在其他实施例中，熔丝元件位于位于钨触点顶部的互连级内。

44. 发明授权

US08849643B2 Table-lookup-based models for yield analysis acceleration 有权
标题翻译：基于表查找的产量分析加速模型
公开(公告)号：US08849643B2
公开(公告)日：2014-09-30
申请号：US13107355
申请日：2011-05-13
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim , Tong Li
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim , Tong Li
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： In one embodiment, the invention is a method and apparatus for table-lookup-based models for yield analysis acceleration. One embodiment of a method for statistically evaluating a design of an integrated circuit includes simulating the integrated circuit and generating a lookup table for use in the simulating, the lookup table comprising one or more blocks that specify a device element for an associated bias voltage, wherein the generating comprises generating only those of the one or more blocks that specify the device element for a bias voltage that is required during the simulating.
摘要翻译：在一个实施例中，本发明是用于产量分析加速的基于表查找的模型的方法和装置。用于统计评估集成电路的设计的方法的一个实施例包括模拟集成电路并产生用于模拟的查找表，所述查找表包括指定相关偏置电压的器件元件的一个或多个块，其中该生成包括仅生成在模拟期间所需的偏置电压指定该器件元件的一个或多个块的那些块。

45. 发明申请

US20140025881A1 SELF-RECONFIGURABLE ADDRESS DECODER FOR ASSOCIATIVE INDEX EXTENDED CACHES 有权
标题翻译：自适应地址解码器，用于相关索引扩展的高速缓存
公开(公告)号：US20140025881A1
公开(公告)日：2014-01-23
申请号：US13550762
申请日：2012-07-17
申请人： Rajiv V. Joshi , Ajay N. Bhoj
发明人： Rajiv V. Joshi , Ajay N. Bhoj
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F2212/1021 , G11C15/04
摘要： Associative index extended (AIX) caches can be functionally implemented through a reconfigurable decoder that employs programmable line decoding. The reconfigurable decoder features scalability in the number of lines, the number of index extension bits, and the number of banks. The reconfigurable decoder can switch between pure direct mapped (DM) mode and direct mapped-associative index extended (DM-AIX) mode of operation. For banked configurations, the reconfigurable decoder provides the ability to run some banks in DM mode and some other banks in DM-AIX mode. A cache employing this reconfigurable decoder can provide a comparable level of latency as a DM cache with minimal modifications to a DM cache circuitry of an additional logic circuit on a critical signal path, while providing low power operation at low area overhead with SA cache-like miss rates. Address masking and most-recently-used-save replacement policy can be employed with a single bit overhead per line.
摘要翻译：关联索引扩展（AIX）缓存可以通过采用可编程线解码的可重构解码器进行功能实现。可重配置解码器具有线路数量的可扩展性，索引扩展位的数量和存储体的数量。可重构解码器可以在纯直接映射（DM）模式和直接映射关联索引扩展（DM-AIX）操作模式之间切换。对于组合配置，可重构解码器能够以DM模式运行某些存储区，并以DM-AIX模式运行其他存储区。采用该可重构解码器的高速缓存器可以提供与DM高速缓存相当的延迟水平，对关键信号路径上的附加逻辑电路的DM高速缓存电路进行最小修改，同时在低区域开销提供具有SA缓存类似的低功率操作错过率。地址掩码和最近使用的保存替换策略可以采用每行一个位开销。

46. 发明申请

US20130077415A1 CIRCUIT FOR MEMORY CELL RECOVERY 失效
标题翻译：用于记忆细胞恢复的电路
公开(公告)号：US20130077415A1
公开(公告)日：2013-03-28
申请号：US13247362
申请日：2011-09-28
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Carl J. Radens
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Carl J. Radens
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/02 , G11C7/04 , G11C11/417 , G11C11/419
摘要： An apparatus and method for combating the effects of bias temperature instability (BTI) in a memory cell. Bit lines connecting to a memory cell contain two alternate paths criss-crossing to connect a lower portion of a first bit line to an upper portion of a second bit line, and to connect a lower portion of the second bit line to an upper portion of the first bit line. Alternative to activating transistors on the bit lines to read and write to the memory cell, transistors on the alternative paths may be activated to read and write to the memory cell from the opposite bit lines. The memory cell may be read through the bit lines to a sense amplifier, the transistors on the bit lines are subsequently deactivated and the transistors on the alternate paths are activated to write transposed bit values to the memory cell, thereby reversing the biases.
摘要翻译：一种用于抵抗存储单元中偏置温度不稳定性（BTI）的影响的装置和方法。连接到存储器单元的位线包含两个交替的交替路径，以将第一位线的下部连接到第二位线的上部，并且将第二位线的下部连接到第二位线的上部第一个位线。在位线上激活晶体管以读取和写入存储器单元的替代方案是替代路径上的晶体管可被激活以从相对的位线读取和写入存储器单元。存储器单元可以通过位线读取到读出放大器，位线上的晶体管随后被去激活，并且激活交替路径上的晶体管以将转置的位值写入存储器单元，从而反转偏置。

47. 发明授权

US08346528B2 Equivalent device statistical modeling for bitline leakage modeling 有权
标题翻译：用于位线泄漏建模的等效设备统计建模
公开(公告)号：US08346528B2
公开(公告)日：2013-01-01
申请号：US12551777
申请日：2009-09-01
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device.
摘要翻译：提供了用于将集成电路设计的多个装置建模为单个统计上等同的宽装置的机构。分析集成电路设计以识别具有多个装置的集成电路设计的一部分。对于多个装置，产生统计模型的单个统计学上等效的宽装置，该统计模型具有捕获多个装置中的各个装置的统计工作特性分布的单个统计学等效的宽装置的至少一个操作特性的统计分布。单个统计学等效的宽设备的至少一个统计工作特性是各个设备的统计操作特性的复杂非线性函数。集成电路设计采用单一统计学上等效的宽设备进行建模。

48. 发明授权

US08324102B2 Techniques for impeding reverse engineering 有权
标题翻译：阻止逆向工程的技术
公开(公告)号：US08324102B2
公开(公告)日：2012-12-04
申请号：US13169248
申请日：2011-06-27
申请人： Louis L. Hsu , Rajiv V. Joshi , David W. Kruger
发明人： Louis L. Hsu , Rajiv V. Joshi , David W. Kruger
IPC分类号： H01L21/00
CPC分类号： H01L21/76816 , H01L21/76825 , H01L21/76831 , H01L21/76834 , H01L23/573 , H01L27/02 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.
摘要翻译：提供了反逆向工程技术。一方面，提供了一种在绝缘层中形成至少一个特征的方法。该方法包括以下步骤。离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同在植入区域外侧。空隙填充有至少一种导体材料以在绝缘层中形成特征。

49. 发明授权

US08184475B2 Robust local bit select circuitry to overcome timing mismatch 有权
标题翻译：强大的本地位选择电路，以克服时序不匹配
公开(公告)号：US08184475B2
公开(公告)日：2012-05-22
申请号：US12705780
申请日：2010-02-15
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Antonio R. Pelella , Sudesh Saroop
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Antonio R. Pelella , Sudesh Saroop
IPC分类号： G11C11/41
CPC分类号： G11C7/12 , G11C7/18 , G11C11/413 , G11C2207/002
摘要： An integrated circuit can include an SRAM array having cells arranged in columns, each column being connected to true and complementary read local bitlines RLBLT and RLBLC. A local bit-select circuit can be connected to the cells of a column of the SRAM array, which can include first and second pull-down devices for pulling down a respective one of RLBLT and RLBLC at a timing controlled by a write control signal WRT. The circuit can include cross-coupled p-type field effect transistors (“PFETs”) including a first PFET having a gate connected to RLBLT and having a drain connected to RLBLC, and a second PFET of the pair having a gate connected to RLBLC and having a drain connected to RLBLT. A first device can control a strength of the cross-coupled PFETs. A pair of cross-coupled n-type field effect transistors (“NFETs”) can have gates connected to gates of the first and second pull-down devices. A second device can control a strength of the cross-coupled NFETs. The operation of the first and second devices can be controlled by applying first and second signals having programmed levels thereto. The levels of the first and second signals may selectively activate either the first device or the second device, so as to activate either the cross-coupled PFETs or the cross-coupled NFETs at one time.
摘要翻译：集成电路可以包括具有排列成列的单元的SRAM阵列，每列连接到真实和互补读局部位线RLBLT和RLBLC。局部位选择电路可以连接到SRAM阵列的列的单元，其可以包括用于在由写控制信号WRT控制的定时下拉RLBLT和RLBLC中的相应一个的第一和第二下拉器件。电路可以包括交叉耦合p型场效应晶体管（“PFET”），其包括具有连接到RLBLT并且具有连接到RLBLC的漏极的栅极的第一PFET，并且具有连接到RLBLC的栅极的第二PFET，漏极连接到RLBLT。第一器件可以控制交叉耦合PFET的强度。一对交叉耦合的n型场效应晶体管（“NFET”）可以具有连接到第一和第二下拉器件的栅极的栅极。第二器件可以控制交叉耦合NFET的强度。第一和第二装置的操作可以通过向其施加具有编程电平的第一和第二信号来控制。第一和第二信号的电平可以选择性地激活第一器件或第二器件，以便一次激活交叉耦合的PFET或交叉耦合的NFET。

50. 发明授权

US08170857B2 In-situ design method and system for improved memory yield 有权
标题翻译：提高记忆产量的原位设计方法和系统
公开(公告)号：US08170857B2
公开(公告)日：2012-05-01
申请号：US12324170
申请日：2008-11-26
申请人： Rajiv V. Joshi , Rouwaida Kanj
发明人： Rajiv V. Joshi , Rouwaida Kanj
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/10 , G06F2217/12 , G11C11/412 , Y02P90/265
摘要： A system and method for designing integrated circuits includes determining a target memory module for evaluation and improvement by evaluating performance variables of the memory module. The performance variables are statistically simulated over subset combinations of variables based on pin information for the module. Sensitivities of performance on yield to the variables in the subset combinations are determined. It is then determined whether yield of the target module is acceptable, and if the yield is not acceptable, a design which includes the target module is adjusted in accordance with the sensitivities to adjust the yield.
摘要翻译：用于设计集成电路的系统和方法包括通过评估存储器模块的性能变量来确定用于评估和改进的目标存储器模块。基于模块的引脚信息，对变量的子集组合对性能变量进行统计学模拟。确定在子集合中变量对产量的收益的敏感度。然后确定目标模块的产量是否可接受，并且如果产量不可接受，则根据敏感度调整包括目标模块的设计以调整产量。

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