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1. 发明授权

US08849643B2 Table-lookup-based models for yield analysis acceleration 有权
标题翻译：基于表查找的产量分析加速模型
公开(公告)号：US08849643B2
公开(公告)日：2014-09-30
申请号：US13107355
申请日：2011-05-13
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim , Tong Li
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim , Tong Li
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： In one embodiment, the invention is a method and apparatus for table-lookup-based models for yield analysis acceleration. One embodiment of a method for statistically evaluating a design of an integrated circuit includes simulating the integrated circuit and generating a lookup table for use in the simulating, the lookup table comprising one or more blocks that specify a device element for an associated bias voltage, wherein the generating comprises generating only those of the one or more blocks that specify the device element for a bias voltage that is required during the simulating.
摘要翻译：在一个实施例中，本发明是用于产量分析加速的基于表查找的模型的方法和装置。用于统计评估集成电路的设计的方法的一个实施例包括模拟集成电路并产生用于模拟的查找表，所述查找表包括指定相关偏置电压的器件元件的一个或多个块，其中该生成包括仅生成在模拟期间所需的偏置电压指定该器件元件的一个或多个块的那些块。

2. 发明申请

US20130289965A1 FET-BOUNDING FOR FAST TCAD-BASED VARIATION MODELING 有权
公开(公告)号：US20130289965A1
公开(公告)日：2013-10-31
申请号：US13457722
申请日：2012-04-27
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

3. 发明申请

US20130289948A1 FET-BOUNDING FOR FAST TCAD-BASED VARIATION MODELING 有权
标题翻译：基于快速TCAD变换建模的场效应晶体管
公开(公告)号：US20130289948A1
公开(公告)日：2013-10-31
申请号：US13611359
申请日：2012-09-12
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.
摘要翻译：一种用于分析电路的方法包括识别完整设备结构中的一个或多个设备区域。设备区域提供要分析的感兴趣区域。生成代表性地包括一个或多个设备区域的部分设备。通过采用整个装置结构的物理特性来减少部分装置的分析网格。使用处理器来模拟部分设备，以获得代表整个设备结构的感兴趣区域中的设备输出信息。还披露了系统。

4. 发明授权

US08606557B2 Table lookup method for physics based models for SPICE-like simulators 有权
标题翻译：用于SPICE仿真器的基于物理的模型的表查找方法
公开(公告)号：US08606557B2
公开(公告)日：2013-12-10
申请号：US12698759
申请日：2010-02-02
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/50
摘要： Techniques for electronic circuit design simulation are provided. In one aspect, a method for electronic circuit design simulation includes the following steps. A model (e.g., a physics-based model) of the circuit design is created. Error tables are created containing data related to one or more regions of the circuit design. The model is modified with data from the error tables. The modified model is used to simulate the circuit design.
摘要翻译：提供电子电路设计仿真技术。一方面，电子电路设计仿真的方法包括以下步骤。创建电路设计的模型（例如，基于物理的模型）。创建包含与电路设计的一个或多个区域有关的数据的错误表。该模型使用错误表中的数据进行修改。修改后的模型用于模拟电路设计。

5. 发明授权

US08548788B2 Technology computer-aided design (TCAD)-based virtual fabrication 失效
标题翻译：技术计算机辅助设计（TCAD）的虚拟制造
公开(公告)号：US08548788B2
公开(公告)日：2013-10-01
申请号：US13609542
申请日：2012-09-11
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , G06F2217/10
摘要： A single finite element mesh is generated for predicting performance of an integrated circuit design. A plurality of sample points are identified for conducting a variability study on at least one parameter associated with the integrated circuit design. The sample points are selected to predict performance of the integrated circuit design when subject to variations in the at least one parameter due to variations in manufacturing processes to be used to manufacture the integrated circuit design. A parameterized netlist is generated corresponding to each of the sample points. A technology computer aided design (TCAD) simulation is run for each of the parameterized netlists, using the single finite element mesh for each of the parameterized netlists, until convergence is achieved, to obtain, for each of the parameterized netlists, at least one metric indicative of the performance of the integrated circuit design. A predicted design yield is developed for the integrated circuit design.
摘要翻译：生成单个有限元网格以预测集成电路设计的性能。识别多个采样点用于对与集成电路设计相关联的至少一个参数进行变异性研究。选择采样点以预测由于要用于制造集成电路设计的制造工艺的变化而受到至少一个参数的变化时的集成电路设计的性能。生成对应于每个采样点的参数化网表。对每个参数化网表执行技术计算机辅助设计（TCAD）模拟，使用每个参数化网表的单个有限元网格，直到达到收敛，为每个参数化网表获得至少一个度量指示集成电路设计的性能。为集成电路设计开发了预测的设计产量。

6. 发明申请

US20130060551A1 Technology Computer-Aided Design (TCAD)-Based Virtual Fabrication 失效
标题翻译：技术计算机辅助设计（TCAD）的虚拟制造
公开(公告)号：US20130060551A1
公开(公告)日：2013-03-07
申请号：US13609542
申请日：2012-09-11
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , G06F2217/10
摘要： A single finite element mesh is generated for predicting performance of an integrated circuit design. A plurality of sample points are identified for conducting a variability study on at least one parameter associated with the integrated circuit design. The sample points are selected to predict performance of the integrated circuit design when subject to variations in the at least one parameter due to variations in manufacturing processes to be used to manufacture the integrated circuit design. A parameterized netlist is generated corresponding to each of the sample points. A technology computer aided design (TCAD) simulation is run for each of the parameterized netlists, using the single finite element mesh for each of the parameterized netlists, until convergence is achieved, to obtain, for each of the parameterized netlists, at least one metric indicative of the performance of the integrated circuit design. A predicted design yield is developed for the integrated circuit design.
摘要翻译：生成单个有限元网格以预测集成电路设计的性能。识别多个采样点用于对与集成电路设计相关联的至少一个参数进行变异性研究。选择采样点以预测由于要用于制造集成电路设计的制造工艺的变化而受到至少一个参数的变化时的集成电路设计的性能。生成对应于每个采样点的参数化网表。对每个参数化网表执行技术计算机辅助设计（TCAD）模拟，使用每个参数化网表的单个有限元网格，直到达到收敛，为每个参数化网表获得至少一个度量指示集成电路设计的性能。为集成电路设计开发了预测的设计产量。

7. 发明申请

US20110191091A1 Extremely Compact Table Lookup Method for Fast and Accurate Physics Based Models for SPICE-Like Simulators 有权
标题翻译：用于基于SPICE的模拟器的快速准确的基于物理的模型的非常紧凑的表查找方法
公开(公告)号：US20110191091A1
公开(公告)日：2011-08-04
申请号：US12698759
申请日：2010-02-02
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： Techniques for electronic circuit design simulation are provided. In one aspect, a method for electronic circuit design simulation includes the following steps. A model (e.g., a physics-based model) of the circuit design is created. Error tables are created containing data related to one or more regions of the circuit design. The model is modified with data from the error tables. The modified model is used to simulate the circuit design.
摘要翻译：提供电子电路设计仿真技术。一方面，电子电路设计仿真的方法包括以下步骤。创建电路设计的模型（例如，基于物理的模型）。创建包含与电路设计的一个或多个区域有关的数据的错误表。该模型使用错误表中的数据进行修改。修改后的模型用于模拟电路设计。

8. 发明授权

US08515724B2 Technology computer-aided design (TCAD)-based virtual fabrication 失效
标题翻译：技术计算机辅助设计（TCAD）的虚拟制造
公开(公告)号：US08515724B2
公开(公告)日：2013-08-20
申请号：US12820741
申请日：2010-06-22
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , G06F2217/10
摘要： A single finite element mesh is generated for predicting performance of an integrated circuit design. A plurality of sample points are identified for conducting a variability study on at least one parameter associated with the integrated circuit design. The sample points are selected to predict performance of the integrated circuit design when subject to variations in the at least one parameter due to variations in manufacturing processes to be used to manufacture the integrated circuit design. A parameterized netlist is generated corresponding to each of the sample points. A technology computer aided design (TCAD, e.g., finite element) simulation is run for each of the parameterized netlists, using the single finite element mesh for each of the parameterized netlists, until convergence is achieved, to obtain, for each of the parameterized netlists, at least one metric indicative of the performance of the integrated circuit design. A predicted design yield is developed for the integrated circuit design, based on the at least one metric determined for each of the parameterized netlists. In at least some instances, an importance sampling technique is tightly integrated with the TCAD process.
摘要翻译：生成单个有限元网格以预测集成电路设计的性能。识别多个采样点用于对与集成电路设计相关联的至少一个参数进行变异性研究。选择采样点以预测由于要用于制造集成电路设计的制造工艺的变化而受到至少一个参数的变化时的集成电路设计的性能。生成对应于每个采样点的参数化网表。对于每个参数化的网表，运行技术计算机辅助设计（TCAD，例如有限元）模拟，使用每个参数化网表的单个有限元网格，直到达到收敛，为每个参数化网表，指示集成电路设计的性能的至少一个度量。基于为每个参数化网表确定的至少一个度量，针对集成电路设计开发了预测的设计收益。在至少一些情况下，重要性采样技术与TCAD过程紧密集成。

9. 发明授权

US09411921B2 FET-bounding for fast TCAD-based variation modeling 有权
标题翻译：用于快速基于TCAD的变异建模的FET限制
公开(公告)号：US09411921B2
公开(公告)日：2016-08-09
申请号：US13457722
申请日：2012-04-27
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.
摘要翻译：一种用于分析电路的方法包括识别完整设备结构中的一个或多个设备区域。设备区域提供要分析的感兴趣区域。生成代表性地包括一个或多个设备区域的部分设备。通过采用整个装置结构的物理特性来减少部分装置的分析网格。使用处理器来模拟部分设备，以获得代表整个设备结构的感兴趣区域中的设备输出信息。还披露了系统。

10. 发明申请

US20110313747A1 Technology Computer-Aided Design (TCAD)-Based Virtual Fabrication 失效
标题翻译：技术计算机辅助设计（TCAD）的虚拟制造
公开(公告)号：US20110313747A1
公开(公告)日：2011-12-22
申请号：US12820741
申请日：2010-06-22
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , G06F2217/10
摘要： A single finite element mesh is generated for predicting performance of an integrated circuit design. A plurality of sample points are identified for conducting a variability study on at least one parameter associated with the integrated circuit design. The sample points are selected to predict performance of the integrated circuit design when subject to variations in the at least one parameter due to variations in manufacturing processes to be used to manufacture the integrated circuit design. A parameterized netlist is generated corresponding to each of the sample points. A technology computer aided design (TCAD, e.g., finite element) simulation is run for each of the parameterized netlists, using the single finite element mesh for each of the parameterized netlists, until convergence is achieved, to obtain, for each of the parameterized netlists, at least one metric indicative of the performance of the integrated circuit design. A predicted design yield is developed for the integrated circuit design, based on the at least one metric determined for each of the parameterized netlists. In at least some instances, an importance sampling technique is tightly integrated with the TCAD process.
摘要翻译：生成单个有限元网格以预测集成电路设计的性能。识别多个采样点用于对与集成电路设计相关联的至少一个参数进行变异性研究。选择采样点以预测由于要用于制造集成电路设计的制造工艺的变化而受到至少一个参数的变化时的集成电路设计的性能。生成对应于每个采样点的参数化网表。对于每个参数化的网表，运行技术计算机辅助设计（TCAD，例如有限元）模拟，使用每个参数化网表的单个有限元网格，直到达到收敛，为每个参数化网表，指示集成电路设计的性能的至少一个度量。基于为每个参数化网表确定的至少一个度量，针对集成电路设计开发了预测的设计收益。在至少一些情况下，重要性采样技术与TCAD过程紧密集成。

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