专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20080250284A1 Fault dictionary-based scan chain failure diagnosis 有权
标题翻译：基于故障字典的扫描链故障诊断
公开(公告)号：US20080250284A1
公开(公告)日：2008-10-09
申请号：US11818440
申请日：2007-06-13
申请人： Ruifeng Guo , Yu Huang , Wu-Tung Cheng
发明人： Ruifeng Guo , Yu Huang , Wu-Tung Cheng
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318525 , G01R31/318541
摘要： A dictionary-based scan chain fault detector includes a dictionary with fault signatures computed for scan cells in the scan chain. Entries in the fault dictionary are compared with failures in the failure log to identify a faulty scan cell. In one embodiment a single fault in a scan chain is identified. In another embodiment, a last fault and a first fault in a scan chain are identified.
摘要翻译：基于字典的扫描链故障检测器包括为扫描链中的扫描单元计算的具有故障签名的字典。将故障字典中的条目与故障日志中的故障进行比较，以识别故障扫描单元。在一个实施例中，识别扫描链中的单个故障。在另一个实施例中，识别扫描链中的最后故障和第一故障。

42. 发明申请

US20080040637A1 DIAGNOSING MIXED SCAN CHAIN AND SYSTEM LOGIC DEFECTS 有权
标题翻译：诊断混合扫描链和系统逻辑缺陷
公开(公告)号：US20080040637A1
公开(公告)日：2008-02-14
申请号：US11838858
申请日：2007-08-14
申请人： Yu Huang , Wu-Tung Cheng , Ruifeng Guo
发明人： Yu Huang , Wu-Tung Cheng , Ruifeng Guo
IPC分类号： G06F11/25 , G01R31/3177 , G06F11/26 , G06F11/263 , G06F17/50
CPC分类号： G01R31/318569
摘要： Technologies disclosed herein can be used to diagnose defects on die having both scan chain and system logic defects, including in situations where the presence of one or more faults in the system logic potentially obscures the detectability of one or more faults in the scan chains (or channels) and vice versa. At least some embodiments employ an iterative approach where at least some scan chain faults are identified, these chain faults are used to identify system logic faults, and then additional chain faults are identified using the system logic faults and vice versa. Failing bits can be partitioned into at least two groups: failing bits determined as being caused by system logic failures, and failing bits determined as being possibly caused by chain defects, system logic defects, or the compound effects of both types of defects.
摘要翻译：本文公开的技术可用于诊断具有扫描链和系统逻辑缺陷的裸片上的缺陷，包括在系统逻辑中存在一个或多个故障潜在地掩盖扫描链中的一个或多个故障的可检测性的情况下（或频道），反之亦然。至少一些实施例采用迭代方法，其中识别出至少一些扫描链故障，这些链故障用于识别系统逻辑故障，然后使用系统逻辑故障来识别附加链故障，反之亦然。失败的位可被划分为至少两组：确定为由系统逻辑故障引起的故障位，以及确定为可能由链缺陷，系统逻辑缺陷或两种类型的缺陷的复合效应引起的故障位。

43. 发明申请

US20070283202A1 COMPACTOR INDEPENDENT FAULT DIAGNOSIS 有权
标题翻译：压力计独立故障诊断
公开(公告)号：US20070283202A1
公开(公告)日：2007-12-06
申请号：US11772648
申请日：2007-07-02
申请人： Wu-Tung Cheng , Kun-Han Tsai , Yu Huang , Nagesh Tamarapalli , Janusz Rajski
发明人： Wu-Tung Cheng , Kun-Han Tsai , Yu Huang , Nagesh Tamarapalli , Janusz Rajski
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G06F11/267
摘要： Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In certain disclosed embodiments, methods for diagnosing faults from compressed test responses are provided. For example, in one exemplary embodiment, a circuit description of an at least partially scan-based circuit-under-test and a compactor for compacting test responses captured in the circuit-under-test is received. A transformation function performed by the compactor to the test responses captured in the circuit-under-test is determined. A diagnostic procedure for evaluating uncompressed test responses is modified into a modified diagnostic procedure that incorporates the transformation function therein. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media comprising lists of fault candidates identified by any of the disclosed methods or circuit descriptions created or modified by the disclosed methods are provided.
摘要翻译：本文公开了用于执行故障诊断的方法，装置和系统。在某些公开的实施例中，提供了用于从压缩测试响应诊断故障的方法。例如，在一个示例性实施例中，接收至少部分基于扫描的测试电路和压实器的电路描述，用于压缩在待测电路中捕获的测试响应。确定由压实机对被测电路中捕获的测试响应执行的变换功能。用于评估未压缩测试响应的诊断程序被修改为并入其中的变换功能的修改的诊断过程。还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的计算机可读介质。同样地，提供了包括通过由所公开的方法创建或修改的任何公开的方法或电路描述所识别的故障候选列表的计算机可读介质。

44. 发明申请

US20070220381A1 Enhanced diagnosis with limited failure cycles 有权
标题翻译：增强诊断有限的故障周期
公开(公告)号：US20070220381A1
公开(公告)日：2007-09-20
申请号：US11510079
申请日：2006-08-25
申请人： Yu Huang , Wu-Tung Cheng , Nagesh Tamarapalli , Randy Klingenberg , Janusz Rajski
发明人： Yu Huang , Wu-Tung Cheng , Nagesh Tamarapalli , Randy Klingenberg , Janusz Rajski
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318569
摘要： Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example, pattern sets can be ordered according to a diagnosis coverage figure, which can be used to measure chain or logic diagnosability of the pattern set. Per-pin based diagnosis techniques can also be used to analyze limited failure data.
摘要翻译：使用本文描述的各种方法，系统和装置的实施例，可以在存在有限故障循环的情况下增强链或逻辑诊断分辨率。例如，可以根据诊断覆盖率对图案集进行排序，这可以用于测量图案集的链或逻辑诊断。基于引脚的诊断技术也可用于分析有限的故障数据。

45. 发明申请

US20050222816A1 Compactor independent fault diagnosis 有权
标题翻译：压实机独立故障诊断
公开(公告)号：US20050222816A1
公开(公告)日：2005-10-06
申请号：US10925230
申请日：2004-08-23
申请人： Wu-Tung Cheng , Kun-Han Tsai , Yu Huang , Nagesh Tamarapalli , Janusz Rajski
发明人： Wu-Tung Cheng , Kun-Han Tsai , Yu Huang , Nagesh Tamarapalli , Janusz Rajski
IPC分类号： G06F11/30 , G06F15/00
CPC分类号： G01R31/318547 , G06F11/267
摘要： Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In certain disclosed embodiments, methods for diagnosing faults from compressed test responses are provided. For example, in one exemplary embodiment, a circuit description of an at least partially scan-based circuit-under-test and a compactor for compacting test responses captured in the circuit-under-test is received. A transformation function performed by the compactor to the test responses captured in the circuit-under-test is determined. A diagnostic procedure for evaluating uncompressed test responses is modified into a modified diagnostic procedure that incorporates the transformation function therein. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media comprising lists of fault candidates identified by any of the disclosed methods or circuit descriptions created or modified by the disclosed methods are provided.
摘要翻译：本文公开了用于执行故障诊断的方法，装置和系统。在某些公开的实施例中，提供了用于从压缩测试响应诊断故障的方法。例如，在一个示例性实施例中，接收至少部分基于扫描的测试电路和压实器的电路描述，用于压缩在待测电路中捕获的测试响应。确定由压实机对被测电路中捕获的测试响应执行的变换功能。用于评估未压缩测试响应的诊断程序被修改为并入其中的变换功能的修改的诊断过程。还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的计算机可读介质。同样地，提供了包括通过由所公开的方法创建或修改的任何公开的方法或电路描述所识别的故障候选列表的计算机可读介质。

46. 发明授权

US08209572B2 Testing embedded memories in an integrated circuit 有权
标题翻译：在集成电路中测试嵌入式存储器
公开(公告)号：US08209572B2
公开(公告)日：2012-06-26
申请号：US12941404
申请日：2010-11-08
申请人： Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
发明人： Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
IPC分类号： G06F17/50 , G11C29/00 , G01R31/28
CPC分类号： G11C29/1201 , G11C29/48 , G11C2029/0401 , G11C2029/0405 , G11C2029/3202
摘要： Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller, and at least one scan cell coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool.
摘要翻译：公开了用于在集成电路中测试嵌入式存储器的各种新的和非显而易见的装置和方法。所公开的实施例之一是用于测试集成电路中的嵌入式存储器的装置。该示例性实施例包括输入逻辑，其包括耦合到嵌入式存储器的相应存储器输入的一个或多个存储器输入路径，存储器内置自检（MBIST）控制器，以及耦合在输入逻辑和 MBIST控制器。本实施例的扫描单元可选择性地在存储器测试模式和系统模式下工作。在存储器测试模式下，扫描单元可以将存储器测试数据沿集成电路的存储器输入路径应用于存储器输入。在诸如电子设计自动化（“EDA”）软件工具的计算机执行的应用中，可以设计，模拟和/或验证任何公开的装置（并且可以执行任何公开的方法）。

47. 发明授权

US07840865B2 Built-in self-test of integrated circuits using selectable weighting of test patterns 有权
标题翻译：使用可选择的测试模式加权来集成电路的内置自检
公开(公告)号：US07840865B2
公开(公告)日：2010-11-23
申请号：US11973084
申请日：2007-10-05
申请人： Liyang Lai , Wu-Tung Cheng , Thomas Hans Rinderknecht
发明人： Liyang Lai , Wu-Tung Cheng , Thomas Hans Rinderknecht
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A built-in self-test (BIST) circuit is disclosed that allows high fault coverage. Additionally, a method is disclosed for implementing the BIST circuit. In one aspect, the BIST circuit includes a plurality of scan chains that receive test patterns used in testing the integrated circuit. A pseudo random pattern generator provides test patterns to the scan chains. Weight select logic is positioned between the scan chains and the pseudo random pattern generator and controls the weightings of the test patterns that are loaded in the scan chains. In another aspect, the weight select logic can switch the weightings of the test patterns on a per-scan-cell basis. Thus, as the scan chains are loading, the weight select logic can effectively switch between test patterns being loaded into the scan chains.
摘要翻译：公开了一种内置自检（BIST）电路，可以实现高故障覆盖。另外，公开了一种用于实现BIST电路的方法。在一个方面，BIST电路包括多个扫描链，其接收用于测试集成电路的测试图案。伪随机模式生成器向扫描链提供测试模式。重量选择逻辑位于扫描链和伪随机模式发生器之间，并控制加载到扫描链中的测试图案的权重。在另一方面，权重选择逻辑可以在每个扫描单元的基础上切换测试图案的加权。因此，随着扫描链的加载，权重选择逻辑可以有效地在被加载到扫描链中的测试模式之间切换。

48. 发明授权

US07836366B2 Defect localization based on defective cell diagnosis 有权
标题翻译：基于缺陷细胞诊断的缺陷定位
公开(公告)号：US07836366B2
公开(公告)日：2010-11-16
申请号：US11876430
申请日：2007-10-22
申请人： Manish Sharma , Wu-Tung Cheng
发明人： Manish Sharma , Wu-Tung Cheng
IPC分类号： G01R31/28 , G01R31/14 , G01R31/02 , G01R31/26 , G06F11/00
CPC分类号： G01R31/318569 , G01R31/2846
摘要： Among the various embodiments described is a method of detecting defects in a cell of an integrated circuit that analyzes exercising conditions applied to an input of the cell during a capture phase of testing with failed test patterns that produce an indication of a fault and that analyzes the exercising conditions that are applied during a capture phase of testing with observable passing patterns that do not provide an indication of a fault. From the analysis, true failing excitation conditions and passing excitation conditions can be determined and used to identify whether a defect is in the cell or on an interconnect wire of the integrated circuit.
摘要翻译：所描述的各种实施例中的一种检测集成电路的单元中的缺陷的方法，其分析在测试的捕获阶段期间施加到单元的输入的运行条件，其中产生故障指示的失败的测试图案，并且分析运行在测试捕获阶段期间应用的条件，其中可观察到的通过模式不提供故障指示。从分析可以确定真实故障激励条件和通过激励条件，并用于识别缺陷是在集成电路的单元还是互连线上。

49. 发明申请

US20090172486A1 TESTING EMBEDDED MEMORIES IN AN INTEGRATED CIRCUIT 有权
标题翻译：在一体化电路中测试嵌入式存储器
公开(公告)号：US20090172486A1
公开(公告)日：2009-07-02
申请号：US12400664
申请日：2009-03-09
申请人： Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
发明人： Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
IPC分类号： G01R31/3187 , G06F11/00
CPC分类号： G11C29/1201 , G11C29/48 , G11C2029/0401 , G11C2029/0405 , G11C2029/3202
摘要： Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller, and at least one scan cell coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool.
摘要翻译：公开了用于在集成电路中测试嵌入式存储器的各种新的和非显而易见的装置和方法。所公开的实施例之一是用于测试集成电路中的嵌入式存储器的装置。该示例性实施例包括输入逻辑，其包括耦合到嵌入式存储器的相应存储器输入的一个或多个存储器输入路径，存储器内置自检（MBIST）控制器，以及耦合在输入逻辑和 MBIST控制器。本实施例的扫描单元可选择性地在存储器测试模式和系统模式下工作。在存储器测试模式下，扫描单元可以将存储器测试数据沿集成电路的存储器输入路径应用于存储器输入。在诸如电子设计自动化（“EDA”）软件工具的计算机执行的应用中，可以设计，模拟和/或验证任何公开的装置（并且可以执行任何公开的方法）。

50. 发明申请

US20080235544A1 Built-in self-test of integrated circuits using selectable weighting of test patterns 有权
标题翻译：使用可选择的测试模式加权来集成电路的内置自检
公开(公告)号：US20080235544A1
公开(公告)日：2008-09-25
申请号：US11973084
申请日：2007-10-05
申请人： Liyang Lai , Wu-Tung Cheng , Thomas Hans Rinderknecht
发明人： Liyang Lai , Wu-Tung Cheng , Thomas Hans Rinderknecht
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A built-in self-test (BIST) circuit is disclosed that allows high fault coverage. Additionally, a method is disclosed for implementing the BIST circuit. In one aspect, the BIST circuit includes a plurality of scan chains that receive test patterns used in testing the integrated circuit. A pseudo random pattern generator provides test patterns to the scan chains. Weight select logic is positioned between the scan chains and the pseudo random pattern generator and controls the weightings of the test patterns that are loaded in the scan chains. In another aspect, the weight select logic can switch the weightings of the test patterns on a per-scan-cell basis. Thus, as the scan chains are loading, the weight select logic can effectively switch between test patterns being loaded into the scan chains.
摘要翻译：公开了一种内置自检（BIST）电路，可以实现高故障覆盖。另外，公开了一种用于实现BIST电路的方法。在一个方面，BIST电路包括多个扫描链，其接收用于测试集成电路的测试图案。伪随机模式生成器向扫描链提供测试模式。重量选择逻辑位于扫描链和伪随机模式发生器之间，并控制加载到扫描链中的测试图案的权重。在另一方面，权重选择逻辑可以在每个扫描单元的基础上切换测试图案的加权。因此，随着扫描链的加载，权重选择逻辑可以有效地在被加载到扫描链中的测试模式之间切换。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式