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41. 发明授权

US5621689A Nonvolatile semiconductor memory device having controlled charge pump load 失效
标题翻译：具有受控电荷泵负载的非易失性半导体存储器件
公开(公告)号：US5621689A
公开(公告)日：1997-04-15
申请号：US457708
申请日：1995-06-01
申请人： Kiyohiko Sakakibara , Natsuo Ajika
发明人： Kiyohiko Sakakibara , Natsuo Ajika
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/14 , G11C16/30 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C16/30 , G11C16/10 , G11C16/14 , H01L27/115
摘要： It is postulated that a nonvolatile semiconductor memory device of the present invention includes a charge pump. The nonvolatile semiconductor memory device includes a memory cell array unit having a plurality of memory transistors formed therein to store data. Each memory transistor has a drain region connected to a predetermined bit line BL which is connected to a write circuit. A charge pump is connected to the write circuit. A predetermined potential is applied to a memory transistor via the write circuit by this charge pump in a writing mode. A charge pump load control means for suppressing variation in the charge pump load is connected to a memory transistor or a well region in which the memory transistor is formed. Thus, the charge pump load can be stabilized to allow improvement of the writing or erasing characteristics of the nonvolatile semiconductor memory device.
摘要翻译：假设本发明的非易失性半导体存储器件包括电荷泵。非易失性半导体存储器件包括具有形成在其中以存储数据的多个存储晶体管的存储单元阵列单元。每个存储晶体管具有连接到写入电路的预定位线BL的漏极区域。电荷泵连接到写入电路。通过该电荷泵以写入模式将预定电位经由写入电路施加到存储晶体管。用于抑制电荷泵负载变化的电荷泵负载控制装置连接到其中形成存储晶体管的存储晶体管或阱区。因此，可以稳定电荷泵负载，以提高非易失性半导体存储器件的写入或擦除特性。

42. 发明授权

US5523596A Semiconductor device having capacitor and manufacturing method therefor 失效
标题翻译：具有电容器的半导体器件及其制造方法
公开(公告)号：US5523596A
公开(公告)日：1996-06-04
申请号：US403614
申请日：1995-03-14
申请人： Makoto Ohi , Hideaki Arima , Natsuo Ajika
发明人： Makoto Ohi , Hideaki Arima , Natsuo Ajika
IPC分类号： H01L27/04 , H01L21/318 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808 , Y10S438/954
摘要： A capacitor includes a polycrystalline silicon layer 1 as a lower electrode layer, a dielectric layer 112, and a polycrystalline silicon layer 113 as an upper electrode layer. The dielectric layer 112 is formed by an oxynitride film 2, a silicon nitride film 3 and a top oxide film 4. A film thickness t.sub.3 of the top oxide film 4 is controlled to be less than 20 .ANG.. Capacitance of the capacitor can be increased while improving the duration of life of the dielectric layer, resulting in a highly reliable capacitor.
摘要翻译：电容器包括作为下电极层的多晶硅层1，电介质层112和作为上电极层的多晶硅层113。电介质层112由氧氮化物膜2，氮化硅膜3和顶部氧化物膜4形成。顶部氧化膜4的膜厚度t3被控制为小于20安培。可以增加电容器的电容，同时改善电介质层的寿命，导致高度可靠的电容器。

43. 发明授权

US5355012A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5355012A
公开(公告)日：1994-10-11
申请号：US52858
申请日：1993-04-28
申请人： Yasuo Yamaguchi , Natsuo Ajika , Tsuyoshi Yamano
发明人： Yasuo Yamaguchi , Natsuo Ajika , Tsuyoshi Yamano
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/12 , H01L29/78 , H01L29/786 , H01L33/00
CPC分类号： H01L29/78612
摘要： A semiconductor device is an SOI type field effect transistor in which an active region is isolated and insulated by a transistor for isolation. A contact hole for isolation is formed in a gate dielectric thin film for isolation between a gate electrode of the transistor for isolation and a channel region below the gate electrode. In the semiconductor device thus structured, surplus carriers produced in a channel region below a transfer gate electrode are drawn through channel region and isolation contact hole into isolation gate electrode, thereby preventing such a disadvantageous phenomenon as a kink effect or the like due to a floating-substrate effect.
摘要翻译：半导体器件是SOI型场效应晶体管，其中有源区被隔离的晶体管隔离并绝缘。用于隔离的接触孔形成在用于隔离的晶体管的栅电极和栅电极下方的沟道区之间隔离的栅极电介质薄膜中。在这样构成的半导体装置中，在传输栅电极下方的沟道区域产生的多余载流子通过沟道区域和隔离接触孔被吸入隔离栅电极，从而防止由于浮动而引起的扭结效应等不利现象 - 底物效应。

44. 发明授权

US5233212A Semiconductor device having gate electrode spacing dependent upon gate side wall insulating dimension 失效
标题翻译：具有栅极电极间距的半导体器件与栅极侧壁绝缘尺寸相关
公开(公告)号：US5233212A
公开(公告)日：1993-08-03
申请号：US692395
申请日：1991-04-25
申请人： Makoto Ohi , Hideaki Arima , Natsuo Ajika , Atsushi Hachisuka , Yasushi Matsui
发明人： Makoto Ohi , Hideaki Arima , Natsuo Ajika , Atsushi Hachisuka , Yasushi Matsui
IPC分类号： H01L27/04 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L21/76801 , H01L21/76834 , H01L27/10808 , Y10S257/90
摘要： A semiconductor device includes a plurality of gate electrodes (6a, 6b, 6c, 6d) arranged on the surface of a semiconductor substrate (1) with insulating layers (5, 8) covering the top and the side walls of the gate electrodes. The spaces between the opposing side walls of adjacent gate electrodes on the surface of the element isolation region (2) re smaller than twice the thickness of the thinnest insulating layer (8) among the insulating layers of the side walls of the gate electrodes on the surface of the active regions. The space (14) between the gate electrodes on the element isolation region is filled with the insulating isolation layer (8) so that unevenness in the underlying portion on the element isolation region on which the conductive interconnection layer (10) to be formed is reduced, preventing thinning of the conductive interconnection layer and disconnection due to excessive etching of a resin film in patterning the conductive interconnection layer.
摘要翻译：半导体器件包括布置在半导体衬底（1）的表面上的多个栅电极（6a，6b，6c，6d），绝缘层（5,8）覆盖了栅电极的顶部和侧壁。在元件隔离区域（2）的表面上的相邻栅电极的相对侧壁之间的间隔小于栅电极侧壁的绝缘层中最薄绝缘层（8）的厚度的两倍活性区的表面。元件隔离区域上的栅电极之间的空间（14）填充有绝缘隔离层（8），使得要形成导电互连层（10）的元件隔离区域上的下面部分的不均匀性减小防止导电互连层变薄，并且在图案化导电互连层时由于树脂膜的过度蚀刻而导致的断开。

45. 发明授权

US5162262A Multi-layered interconnection structure for a semiconductor device and manufactured method thereof 失效
标题翻译：半导体器件的多层互连结构及其制造方法
公开(公告)号：US5162262A
公开(公告)日：1992-11-10
申请号：US727032
申请日：1991-07-08
申请人： Natsuo Ajika , Hideaki Arima
发明人： Natsuo Ajika , Hideaki Arima
IPC分类号： H01L21/285 , H01L21/321 , H01L21/768 , H01L23/532 , H01L29/45
CPC分类号： H01L21/76856 , H01L21/28518 , H01L21/3211 , H01L21/76843 , H01L23/53223 , H01L29/456 , H01L2924/0002 , Y10S148/019
摘要： An interconnection layer of a semiconductor device according to the present invention has in a contact portion with a conductor layer a multi-layered structure formed from the bottom, of a refractory metal silicide layer, a first refractory metal nitride layer, and a secondary refractory metal nitride layer. Titanium or tungsten is used as a refractory metal. The second refractory metal nitride is formed by thermally nitriding the refractory metal layer. The second refractory metal nitride layer formed by the thermal process has a close packed crystal structure and has an excellent barrier characteristic.
摘要翻译：根据本发明的半导体器件的互连层具有与难熔金属硅化物层，第一耐火金属氮化物层和第二难熔金属的底部形成的多层结构的导体层的接触部分氮化物层。钛或钨用作难熔金属。通过对耐火金属层进行热氮化而形成第二难熔金属氮化物。通过热处理形成的第二耐火金属氮化物层具有紧密堆积的晶体结构，并且具有优异的阻挡特性。

46. 发明授权

US5093277A Method of device isolation using polysilicon pad LOCOS method 失效
标题翻译：使用多晶硅焊盘的器件隔离方法LOCOS方法
公开(公告)号：US5093277A
公开(公告)日：1992-03-03
申请号：US487322
申请日：1990-03-02
申请人： Hideaki Arima , Natsuo Ajika
发明人： Hideaki Arima , Natsuo Ajika
IPC分类号： H01L21/76 , H01L21/316 , H01L21/32 , H01L21/762
CPC分类号： H01L21/76227 , H01L21/32
摘要： Here is disclosed an improved polysilicon pad LOCOS method. An underlying oxide film is formed on a main surface of a semiconductor substrate. Over the underlying oxide film, polysilicon to be a field oxide film is then deposited. Subsequently, a nitride film is formed on the polysilicon. Thereafter, the nitride film is patterned to leave patterns of a predetermined configuration in an area to be a device region. Using the patterned nitride film as a mask, the polysilicon other than a portion beneath the mask is thermally oxidized to form a field oxide film on the main surface of the semiconductor substrate. The nitride film having served as a mask is then removed to expose the unoxidized polysilicon remaining under the mask. Subsequently, the unoxidized polysilicon is etched away under predetermined conditions which do not allow any etching of the underlying oxide film. According to the present method, it is possible to increase the film thickness of the field oxide film without opening any hole in the surface of the semiconductor substrate. As a result, a highly integrated semiconductor device can be obtained.
摘要翻译：这里公开了改进的多晶硅焊盘LOCOS方法。在半导体衬底的主表面上形成下面的氧化膜。然后在底层氧化物膜上沉积多晶硅作为场氧化物膜。随后，在多晶硅上形成氮化物膜。此后，对氮化膜进行图案化，以便在作为器件区域的区域中留下预定结构的图案。使用图案化的氮化物膜作为掩模，除了掩模下面的部分之外的多晶硅被热氧化以在半导体衬底的主表面上形成场氧化膜。用作掩模的氮化物膜然后被去除以暴露残留在掩模下面的未氧化的多晶硅。随后，在不允许对下面的氧化膜进行任何蚀刻的预定条件下，蚀刻掉未氧化的多晶硅。根据本方法，可以在半导体衬底的表面中没有打开任何孔的情况下增加场氧化膜的膜厚。结果，可以获得高度集成的半导体器件。

47. 发明授权

US5051948A Content addressable memory device 失效
标题翻译：内容可寻址存储设备
公开(公告)号：US5051948A
公开(公告)日：1991-09-24
申请号：US434692
申请日：1989-10-20
申请人： Kiyoto Watabe , Hirofumi Shinohara , Takahisa Eimori , Hideaki Arima , Natsuo Ajika , Yuichi Nakashima , Shinichi Satoh
发明人： Kiyoto Watabe , Hirofumi Shinohara , Takahisa Eimori , Hideaki Arima , Natsuo Ajika , Yuichi Nakashima , Shinichi Satoh
IPC分类号： G11C15/04
CPC分类号： G11C15/046
摘要： In a content addressable memory (CAM) cell according to the present invention, a pair of non-volatile memory transistors hold data, whereby stored data will not disappear even if power is cut. Conducting terminals of these non-volatile transistors are connected to a bit line pair, so that the stored data can be directly read out from the bit line pair. Further, the invention CAM system converts the value of a current flowing in a match line into a voltage value to perform content reference, and hence the same can be employed as an associative memory system.
摘要翻译： PCT No.PCT / JP89 / 00179 Sec。 371日期1989年10月20日第 102（e）日期1989年10月20日PCT提交1989年2月22日PCT公布。出版物WO89 / 08314 日本1989年9月8日。在根据本发明的内容可寻址存储器（CAM）单元中，一对非易失性存储晶体管保持数据，由此即使切断功率，存储的数据也不会消失。这些非易失性晶体管的导通端子连接到位线对，从而可以从位线对直接读出所存储的数据。此外，本发明CAM系统将在匹配线中流动的电流的值转换为电压值以执行内容参考，因此可以将其用作关联存储器系统。

48. 发明授权

US5049975A Multi-layered interconnection structure for a semiconductor device 失效
标题翻译：用于半导体器件的多层互连结构
公开(公告)号：US5049975A
公开(公告)日：1991-09-17
申请号：US492032
申请日：1990-03-12
申请人： Natsuo Ajika , Hideaki Arima
发明人： Natsuo Ajika , Hideaki Arima
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/285 , H01L21/321 , H01L21/768 , H01L23/52 , H01L23/532 , H01L29/43 , H01L29/45
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/3211 , H01L23/53223 , H01L29/456 , H01L2924/0002 , Y10S257/915
摘要： An interconnection layer of a semiconductor device according to the present invention has in a contact portion with a conductor layer a multi-layered structure formed from the bottom, of a refractory metal silicide layer, a first refractory metal nitride layer, and a second refractory metal nitride layer. Titanium or tungsten is used as a refractory metal. The second refractory metal nitride is formed by thermally nitriding the refractory metal layer. The second refractory metal nitride layer formed by the thermal process has a close packed crystal structure and has an excellent barrier characteristic.
摘要翻译：根据本发明的半导体器件的互连层具有与难熔金属硅化物层，第一耐火金属氮化物层和第二难熔金属的底部形成的多层结构的导体层的接触部分氮化物层。钛或钨用作难熔金属。通过对耐火金属层进行热氮化而形成第二难熔金属氮化物。通过热处理形成的第二耐火金属氮化物层具有紧密堆积的晶体结构，并且具有优异的阻挡特性。

49. 发明授权

US08687455B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08687455B2
公开(公告)日：2014-04-01
申请号：US13205900
申请日：2011-08-09
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
IPC分类号： G11C8/00
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译：通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。

50. 发明授权

US07924615B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07924615B2
公开(公告)日：2011-04-12
申请号：US12714750
申请日：2010-03-01
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
IPC分类号： G11C11/34
CPC分类号： G11C16/3436
摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.
摘要翻译：非易失性半导体存储器技术领域本发明涉及一种非易失性半导体存储器，更具体地涉及一种具有增加的程序吞吐量的非易失性半导体存储器。本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

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