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41. 发明授权

US07936016B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07936016B2
公开(公告)日：2011-05-03
申请号：US12413980
申请日：2009-03-30
申请人： Toshiaki Tsutsumi , Tomonori Okudaira , Keiichiro Kashihara , Tadashi Yamaguchi
发明人： Toshiaki Tsutsumi , Tomonori Okudaira , Keiichiro Kashihara , Tadashi Yamaguchi
IPC分类号： H01L29/76
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.
摘要翻译：提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一层间绝缘膜依次层叠在金属硅化物上。在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。

42. 发明申请

US20100230761A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100230761A1
公开(公告)日：2010-09-16
申请号：US12720174
申请日：2010-03-09
申请人： Tadashi Yamaguchi , Toshiaki Tsutsumi , Satoshi Ogino , Kazumasa Yonekura , Kenji Kawai , Yoshihiro Miyagawa , Tomonori Okudaira , Keiichiro Kashihara , Kotaro Kihara
发明人： Tadashi Yamaguchi , Toshiaki Tsutsumi , Satoshi Ogino , Kazumasa Yonekura , Kenji Kawai , Yoshihiro Miyagawa , Tomonori Okudaira , Keiichiro Kashihara , Kotaro Kihara
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823807 , H01L21/823814 , H01L29/7843
摘要： To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.
摘要翻译：提高半导体器件的性能。在用于n沟道型MISFET和第一栅电极的源极/漏极的n +型半导体区域上，以及用于p沟道型MISFET和第二栅电极的源极/漏极的p +型半导体区域上，其中形成在半导体衬底上，通过自对准硅化物工艺形成包括镍铂硅化物的金属硅化物层。之后，在半导体基板的整个面上形成拉伸应力膜，然后通过干法蚀刻去除p沟道型MISFET上的拉伸应力膜，并且在整个压电应力膜形成之后在半导体衬底的表面上，通过干蚀刻去除n沟道型MISFET上的压缩应力膜。金属硅化物层中的Pt浓度在表面处最高，并且随着从表面的深度增加而变低。

43. 发明申请

US20090079007A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090079007A1
公开(公告)日：2009-03-26
申请号：US12211925
申请日：2008-09-17
申请人： TADASHI YAMAGUCHI , Keiichiro Kashihara , Toshiaki Tsutsumi , Tomonori Okudaira
发明人： TADASHI YAMAGUCHI , Keiichiro Kashihara , Toshiaki Tsutsumi , Tomonori Okudaira
IPC分类号： H01L29/00 , H01L21/8238
CPC分类号： H01L29/045 , H01L21/823807 , H01L27/105 , H01L27/11 , H01L29/1054 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： The present invention can prevent occurrence of an off-leak current in the NMISFETs formed over the Si (110) substrate and having a silicided source/drain region. The semiconductor device includes N channel MISFETs (Metal Insulator Semiconductor Field Effect Transistors) which are formed over a semiconductor substrate having a main surface with a (110) plane orientation and have a source region and a drain region at least one of which has thereover nickel silicide or a nickel alloy silicide. Of these NMISFETs, those having a channel width less than 400 nm are laid out so that their channel length direction is parallel to a crystal orientation.
摘要翻译：本发明可以防止在Si（110）衬底上形成的具有硅化源极/漏极区域的NMISFET中产生漏电流。半导体器件包括N沟道MISFET（金属绝缘体半导体场效应晶体管），其形成在具有（110）面取向的主表面的半导体衬底上，并且具有源极区和漏极区，其中至少一个具有镍硅化物或镍合金硅化物。在这些NMISFET中，沟道宽度小于400nm的那些被布置成使得它们的沟道长度方向平行于<100>晶体取向。

44. 发明申请

US20070284671A1 SEMICONDUCTOR DEVICE INCLUDING CMIS TRANSISTOR 审中-公开
标题翻译：包含CMIS晶体管的半导体器件
公开(公告)号：US20070284671A1
公开(公告)日：2007-12-13
申请号：US11759564
申请日：2007-06-07
申请人： Toshiaki TSUTSUMI , Tomonori Okudaira , Keiichiro Kashihara , Tadashi Yamaguchi
发明人： Toshiaki TSUTSUMI , Tomonori Okudaira , Keiichiro Kashihara , Tadashi Yamaguchi
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28097 , H01L21/823871 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L29/66545
摘要： Gate electrodes made of polysilicon film are isolated and face each other by way of a side wall spacer portion that fills a gap formed above an isolation insulating film at the boundary of NMIS region and PMIS region. A first metal film is formed on one of the gate electrodes, and an inhomogeneous second metal film is formed on the other of the gate electrodes. The both gate electrodes become inhomogeneous metal silicide gates through the promotion of silicide reaction by heat treatment. The mutual diffusion of metal atoms from the metal film to the gate electrode is suppressed by the interposition of the side wall spacer portion being an insulating film.
摘要翻译：由多晶硅膜制成的栅电极被隔离并且通过填充在NMIS区域和PMIS区域的边界处的隔离绝缘膜上形成的间隙的侧壁间隔部分相互面对。在一个栅电极上形成第一金属膜，另一个栅电极上形成非均匀的第二金属膜。通过热处理促进硅化物反应，两个栅电极成为不均匀的金属硅化物栅极。通过插入作为绝缘膜的侧壁间隔物部分来抑制金属膜从金属膜到栅电极的相互扩散。

45. 发明申请

US20050153573A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050153573A1
公开(公告)日：2005-07-14
申请号：US11033739
申请日：2005-01-13
申请人： Tomonori Okudaira , Takeshi Hayashi , Hiroshi Fujiwara , Yasushi Fujita , Kiyoteru Kobayashi
发明人： Tomonori Okudaira , Takeshi Hayashi , Hiroshi Fujiwara , Yasushi Fujita , Kiyoteru Kobayashi
IPC分类号： H01L21/20 , C23C16/34 , C23C16/44 , C23C16/56 , H01L21/02 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/423 , H01L29/49 , H01L29/78 , H01L21/31 , H01L21/469
CPC分类号： C23C16/4408 , C23C16/34 , C23C16/56 , H01L21/28088 , H01L21/28556 , H01L27/10811 , H01L27/10894 , H01L28/60
摘要： A manufacturing method of a semiconductor device including a TiN film, including a deposition step of forming a TiN film by the CVD method, an anneal step of performing a heat treatment to the formed TiN film in an atmosphere of NH3 gas, an NH3 gas purge step of purging NH3 gas, and a step of further repeating the deposition step, the anneal step, and the NH3 gas purge step for at least one time. The deposition step is performed using titanium halide gas and NH3 gas as material gases and with a deposition temperature of 300° C.-450° C. to form the TiN film by a thickness of 1 nm-5 nm for each deposition step. Thus, a semiconductor device in which generation of irregularly grown objects in the TiN film is suppressed and a manufacturing method thereof can be provided.
摘要翻译：一种包括TiN膜的半导体器件的制造方法，包括通过CVD法形成TiN膜的沉积步骤，在NH 3气氛中对形成的TiN膜进行热处理的退火步骤，吹扫NH 3气体的NH 3气体吹扫步骤，以及进一步重复沉积步骤，退火步骤和NH 3气体的步骤， 3气体吹扫步骤至少一次。沉积步骤使用卤化钛气体和NH 3气体作为材料气体并且沉积温度为300℃-450℃进行，以形成厚度为1nm的TiN膜，每个沉积步骤为5nm。因此，可以抑制在TiN膜中产生不规则生长的物体的半导体器件及其制造方法。

46. 发明授权

US06764896B2 Semiconductor manufacturing method including patterning a capacitor lower electrode by chemical etching 失效
标题翻译：半导体制造方法包括通过化学蚀刻图案化电容器下电极
公开(公告)号：US06764896B2
公开(公告)日：2004-07-20
申请号：US10246521
申请日：2002-09-19
申请人： Tomonori Okudaira
发明人： Tomonori Okudaira
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L21/02197 , H01L21/31116 , H01L21/31612 , H01L21/3185 , H01L21/32136 , H01L21/32139 , H01L27/11507 , H01L28/55 , H01L28/60
摘要： Sputter etching of silicon oxide films is performed with an etching gas such as C4F8. Since a silicon nitride film is little etched at this time, when the etching is performed under a condition of sufficient overetching for the silicon oxide films, the silicon nitride film serves as an etching stopper, and the silicon oxide film on a platinum film and the silicon oxide film other than a portion below the platinum film are completely removed and the silicon oxide film remains only below the platinum film, to form a protrusion of a layer consisting of the silicon oxide film and the platinum film from a surface of the silicon nitride film. Thus, in patterning, a capacitor lower electrode by chemical etching, a nonuniform etching caused by temperature distribution on a substrate or among a plurality of substrates can be solved.
摘要翻译：用蚀刻气体如C4F8进行氧化硅膜的溅射蚀刻。此时，由于氮化硅膜几乎没被蚀刻，因此在氧化硅膜的过蚀刻条件下进行蚀刻时，作为蚀刻停止层，在铂膜上形成氧化硅膜，除了铂膜下面的部分以外的氧化硅膜被完全去除，并且氧化硅膜仅保留在铂膜的下方，以从氮化硅的表面形成由氧化硅膜和铂膜构成的层的突起电影。因此，在图案化中，可以解决通过化学蚀刻的电容器下电极，由基板或多个基板之间的温度分布引起的不均匀蚀刻。

47. 发明授权

US06278150B1 Conductive layer connecting structure and method of manufacturing the same 失效
标题翻译：导电层连接结构及其制造方法
公开(公告)号：US06278150B1
公开(公告)日：2001-08-21
申请号：US08804530
申请日：1997-02-21
申请人： Tomonori Okudaira , Keiichiro Kashihara , Yoshikazu Tsunemine
发明人： Tomonori Okudaira , Keiichiro Kashihara , Yoshikazu Tsunemine
IPC分类号： H01L27108
CPC分类号： H01L21/76856 , H01L21/76841 , H01L21/76843 , H01L21/7685 , H01L27/10882 , H01L27/10894 , H01L2221/1078
摘要： A conductive layer connecting structure has a barrier layer preventing mutual diffusion between silicon and platinum group elements even when they are heated to a high temperature. The conductive layer connecting structure includes a plug containing doped polycrystalline silicon, a barrier layer formed on the plug and containing titanium, silicon and nitrogen, and a lower electrode layer formed on the barrier layer and containing platinum.
摘要翻译：导电层连接结构具有防止硅和铂族元素之间的相互扩散的阻挡层，即使它们被加热到高温。导电层连接结构包括含有掺杂多晶硅的插塞，形成在插塞上并包含钛，硅和氮的阻挡层，以及形成在阻挡层上并含有铂的下电极层。

48. 发明授权

US5519237A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5519237A
公开(公告)日：1996-05-21
申请号：US264117
申请日：1994-06-22
申请人： Hiromi Itoh , Tomonori Okudaira , Keiichiro Kashihara
发明人： Hiromi Itoh , Tomonori Okudaira , Keiichiro Kashihara
IPC分类号： H01L27/10 , H01L27/108 , H01L29/68
CPC分类号： H01L27/10808
摘要： A first interlayer insulating film having a second contact hole is formed on a main surface of a semiconductor substrate 1 in a peripheral circuitry. A second plug electrode of the same material as a first plug electrode in a memory cell array is formed in the second contact hole. A pad layer is formed over the second plug electrode and a top surface of the first interlayer insulating film. The pad layer and a capacitor lower electrode are made of the same material. The pad layer is covered with the second interlayer insulating film. A third contact hole is formed at a portion of the second interlayer insulating film located above the pad layer. A first aluminum interconnection layer is formed in the third contact hole. Thereby, a contact can be formed easily between the interconnection layer and the main surface of the semiconductor substrate in the peripheral circuitry of a DRAM, and a manufacturing process can be simplified.
摘要翻译：具有第二接触孔的第一层间绝缘膜形成在外围电路中的半导体衬底1的主表面上。在第二接触孔中形成有与存储单元阵列中的第一插头电极相同材料的第二插头电极。在第二插头电极和第一层间绝缘膜的顶表面上形成衬垫层。焊盘层和电容器下电极由相同的材料制成。衬垫层被第二层间绝缘膜覆盖。在位于焊盘层上方的第二层间绝缘膜的一部分处形成第三接触孔。在第三接触孔中形成第一铝互连层。因此，可以在DRAM的外围电路中的互连层和半导体衬底的主表面之间容易地形成接触，并且可以简化制造工艺。

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