专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08338247B2 Semiconductor device and method of manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08338247B2
公开(公告)日：2012-12-25
申请号：US12720174
申请日：2010-03-09
申请人： Tadashi Yamaguchi , Toshiaki Tsutsumi , Satoshi Ogino , Kazumasa Yonekura , Kenji Kawai , Yoshihiro Miyagawa , Tomonori Okudaira , Keiichiro Kashihara , Kotaro Kihara
发明人： Tadashi Yamaguchi , Toshiaki Tsutsumi , Satoshi Ogino , Kazumasa Yonekura , Kenji Kawai , Yoshihiro Miyagawa , Tomonori Okudaira , Keiichiro Kashihara , Kotaro Kihara
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823807 , H01L21/823814 , H01L29/7843
摘要： To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.
摘要翻译：提高半导体器件的性能。在用于n沟道型MISFET和第一栅电极的源极/漏极的n +型半导体区域上，以及用于p沟道型MISFET和第二栅电极的源极/漏极的p +型半导体区域上，其中形成在半导体衬底上，通过自对准硅化物工艺形成包括镍铂硅化物的金属硅化物层。之后，在半导体基板的整个面上形成拉伸应力膜，然后通过干法蚀刻去除p沟道型MISFET上的拉伸应力膜，并且在整个压电应力膜形成之后在半导体衬底的表面上，通过干蚀刻去除n沟道型MISFET上的压缩应力膜。金属硅化物层中的Pt浓度在表面处最高，并且随着从表面的深度增加而变低。

2. 发明申请

US20100230761A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100230761A1
公开(公告)日：2010-09-16
申请号：US12720174
申请日：2010-03-09
申请人： Tadashi Yamaguchi , Toshiaki Tsutsumi , Satoshi Ogino , Kazumasa Yonekura , Kenji Kawai , Yoshihiro Miyagawa , Tomonori Okudaira , Keiichiro Kashihara , Kotaro Kihara
发明人： Tadashi Yamaguchi , Toshiaki Tsutsumi , Satoshi Ogino , Kazumasa Yonekura , Kenji Kawai , Yoshihiro Miyagawa , Tomonori Okudaira , Keiichiro Kashihara , Kotaro Kihara
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823807 , H01L21/823814 , H01L29/7843
摘要： To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.
摘要翻译：提高半导体器件的性能。在用于n沟道型MISFET和第一栅电极的源极/漏极的n +型半导体区域上，以及用于p沟道型MISFET和第二栅电极的源极/漏极的p +型半导体区域上，其中形成在半导体衬底上，通过自对准硅化物工艺形成包括镍铂硅化物的金属硅化物层。之后，在半导体基板的整个面上形成拉伸应力膜，然后通过干法蚀刻去除p沟道型MISFET上的拉伸应力膜，并且在整个压电应力膜形成之后在半导体衬底的表面上，通过干蚀刻去除n沟道型MISFET上的压缩应力膜。金属硅化物层中的Pt浓度在表面处最高，并且随着从表面的深度增加而变低。

3. 发明授权

US6156152A Plasma processing apparatus 失效
标题翻译：等离子体处理装置
公开(公告)号：US6156152A
公开(公告)日：2000-12-05
申请号：US958986
申请日：1997-10-28
申请人： Satoshi Ogino , Kazumasa Yonekura , Hajime Kimura , Shigenori Sakamori
发明人： Satoshi Ogino , Kazumasa Yonekura , Hajime Kimura , Shigenori Sakamori
IPC分类号： H05H1/46 , H01J37/32 , H01L21/302 , H01L21/3065 , C23F1/02
CPC分类号： H01J37/32192 , H01J37/32678
摘要： Provided is a plasma processing apparatus capable of extending an etching parameter to reduce charge-up shape anomalies in dry etching and to enhance etching performance such as selectivity, uniformity, processability or the like. A microwave is controlled to be modulated in frequency and is introduced into a chamber. An ECR face is moved between two positions according to the frequency of the microwave.
摘要翻译：提供了能够延长蚀刻参数以减少干蚀刻中的充电形状异常并提高诸如选择性，均匀性，可加工性等的蚀刻性能的等离子体处理装置。微波被控制为频率调制并被引入腔室。根据微波的频率，ECR面在两个位置之间移动。

4. 发明授权

US06410991B1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06410991B1
公开(公告)日：2002-06-25
申请号：US09196107
申请日：1998-11-20
申请人： Kenji Kawai , Kazumasa Yonekura
发明人： Kenji Kawai , Kazumasa Yonekura
IPC分类号： H01L2976
CPC分类号： H01L27/088 , H01L21/823462 , H01L27/1052
摘要： A relatively thick gate oxide film and a relatively thin gate oxide film are formed on a surface of silicon substrate. In a region exactly under the relatively thick gate oxide film, a halogen is added only within a depth range of no more than 2 nm from the main surface of silicon substrate. Thus, a semiconductor device having a dual gate oxide and a method of manufacturing the same can be obtained capable of reducing damage to the substrate through a simplified process.
摘要翻译：在硅衬底的表面上形成较厚的栅氧化膜和较薄的栅氧化膜。在正好在相对较厚的栅极氧化膜下方的区域中，仅在与硅衬底的主表面不超过2nm的深度范围内添加卤素。因此，可以获得具有双栅极氧化物的半导体器件及其制造方法，其能够通过简化的工艺减少对衬底的损伤。

5. 发明授权

US08288232B2 Manufacturing method of semiconductor device and semiconductor device 有权
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US08288232B2
公开(公告)日：2012-10-16
申请号：US12687110
申请日：2010-01-13
申请人： Yasuhiro Fujii , Kazumasa Yonekura , Tatsunori Kaneoka
发明人： Yasuhiro Fujii , Kazumasa Yonekura , Tatsunori Kaneoka
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462 , H01L21/823418 , H01L21/823456 , H01L21/823481 , H01L29/0653 , H01L29/42364
摘要： An improvement is provided in a manufacturing yield of a semiconductor device including transistors in which gate insulating films have different thicknesses. After a high-breakdown-voltage insulating film is formed over a silicon substrate, a surface of the high-breakdown-voltage insulating film is abraded for a reduction in the thickness thereof so that a middle-breakdown-voltage insulating film is formed to be adjacent to the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed by a thermal oxidation method so as to extend from an inside of the main surface of the silicon substrate to an outside thereof. The middle-breakdown-voltage insulating film is formed so as to be thinner than the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed as the gate insulating film of a high-breakdown-voltage MIS transistor, while the middle-breakdown-voltage insulating film is formed as the gate insulating film of a middle-breakdown-voltage MIS transistor.
摘要翻译：提供一种半导体器件的制造成品率的提高，该半导体器件包括其中栅绝缘膜具有不同厚度的晶体管。在硅衬底上形成高耐压绝缘膜之后，高耐压绝缘膜的表面被磨损以减小其厚度，使得中间击穿电压绝缘膜形成为邻近高耐压绝缘膜。高耐压绝缘膜通过热氧化法形成，以从硅衬底的主表面的内部延伸到其外部。中间击穿电压绝缘膜形成为比高击穿电压绝缘膜薄。高击穿电压绝缘膜形成为高击穿电压MIS晶体管的栅极绝缘膜，而中间击穿电压绝缘膜形成为中间击穿电压MIS晶体管的栅极绝缘膜。

6. 发明授权

US08455348B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08455348B2
公开(公告)日：2013-06-04
申请号：US13074899
申请日：2011-03-29
申请人： Kazumasa Yonekura , Kazuo Tomita
发明人： Kazumasa Yonekura , Kazuo Tomita
IPC分类号： H01L21/00
CPC分类号： H01L21/76835 , H01L21/0332 , H01L21/31144 , H01L21/76808 , H01L21/7681 , H01L21/76829 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method of a semiconductor device is provided which can precisely control the depth of a wiring trench pattern, and which can suppress the damage on the wiring trench pattern. A second low dielectric constant film, a third low dielectric constant film, and a film for serving as a mask layer are laminated over a diffusion preventing film in that order. The film for serving as the mask layer is etched, and a wiring trench pattern is formed which has its bottom made of a surface of the third low dielectric constant film, so that a mask layer is formed. A first resist mask is removed by asking. A wiring trench is formed using the wiring trench pattern of the mask layer such that a bottom of the trench is comprised of the second low dielectric constant film. A layer from a top surface of the copper metal to the third low dielectric constant film is removed by a CMP method. Each low dielectric constant film has a dielectric constant lower than that of FSG, and the second low dielectric constant film has the dielectric constant lower than that of the third low dielectric constant film.
摘要翻译：提供一种半导体器件的制造方法，其可以精确地控制布线沟槽图案的深度，并且可以抑制对布线沟槽图案的损坏。将第二低介电常数膜，第三低介电常数膜和用作掩模层的膜按顺序层叠在扩散防止膜上。蚀刻用作掩模层的膜，并且形成其底部由第三低介电常数膜的表面制成的布线沟槽图案，从而形成掩模层。第一个抗蚀剂掩模通过询问被去除。使用掩模层的布线沟槽图案形成布线沟槽，使得沟槽的底部由第二低介电常数膜构成。通过CMP方法去除从铜金属的顶表面到第三低介电常数膜的层。每个低介电常数膜的介电常数低于FSG，而第二低介电常数膜的介电常数低于第三低介电常数膜。

7. 发明申请

US20070287298A1 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20070287298A1
公开(公告)日：2007-12-13
申请号：US11808650
申请日：2007-06-12
申请人： Takeo Ishibashi , Kazumasa Yonekura , Masahiro Tadokoro , Kazunori Yoshikawa , Yoshiharu Ono
发明人： Takeo Ishibashi , Kazumasa Yonekura , Masahiro Tadokoro , Kazunori Yoshikawa , Yoshiharu Ono
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/0332 , H01L21/0337 , H01L21/31058 , H01L21/31155 , H01L21/76808 , H01L21/76825 , H01L21/76826
摘要： It is an object of the present invention to provide a method of manufacturing a semiconductor device that reduces the deterioration in processed configuration and the pattern roughness of a film to be processed, and is close to the original design and applicable to a dual damascene step and the like. The manufacturing method comprises a processing mask layer forming step of forming a processing mask layer (a lower organic film and a middle layer) comprising at least one film, and hardening treatment for at least one film of the processing mask layer by applying a film and heat hardening treatment; a processing mask layer etching step of applying a resist film for exposure to the processing mask layer, exposing and developing it to form a resist pattern, and etching the processing mask layer using the resist pattern as a mask; and a film to be processed etching step of etching the film to be processed using the pattern of the processing mask layer formed at the processing mask layer etching step as a mask.
摘要翻译：本发明的目的是提供一种制造半导体器件的方法，该半导体器件减少加工结构的劣化和待加工薄膜的图案粗糙度，并且接近原始设计并且可应用于双镶嵌步骤和类似。该制造方法包括：处理掩模层形成步骤，形成包括至少一个膜的处理掩模层（下部有机膜和中间层），以及通过施加膜和至少一层加工掩模层的硬化处理热硬化处理; 处理掩模层蚀刻步骤，将用于曝光的抗蚀剂膜施加到处理掩模层，曝光和显影以形成抗蚀剂图案，并使用抗蚀剂图案作为掩模蚀刻处理掩模层; 以及使用在处理掩模层蚀刻步骤形成的处理掩模层的图案作为掩模来蚀刻待处理的膜的待处理蚀刻步骤的膜。

8. 发明申请

US20080194109A1 Method of fabricating a semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080194109A1
公开(公告)日：2008-08-14
申请号：US12071014
申请日：2008-02-14
申请人： Takeo Ishibashi , Kazumasa Yonekura , Masaaki Shinohara , Mamoru Terai
发明人： Takeo Ishibashi , Kazumasa Yonekura , Masaaki Shinohara , Mamoru Terai
IPC分类号： H01L21/311
CPC分类号： H01L21/32139 , H01L21/02115 , H01L21/02123 , H01L21/022 , H01L21/02271 , H01L21/02282 , H01L21/02304 , H01L21/0273 , H01L21/0337 , H01L21/0338 , H01L21/3146 , H01L21/31612 , H01L21/3185
摘要： A method of fabricating a semiconductor device includes the steps of: depositing on a main surface of a semiconductor substrate a layer to be processed; depositing a base layer on the layer to be processed; depositing a first intermediate layer and then a second intermediate layer on the base layer; patterning the second intermediate layer while the base layer covers the layer to be processed; depositing a first mask pattern on the patterned second intermediate layer; patterning the second intermediate layer with the first mask pattern; patterning the first intermediate layer and the base layer with the patterned second intermediate layer to form a second mask pattern; and patterning the layer to be processed, with the second mask pattern.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底的主表面上沉积待加工的层; 在待处理的层上沉积基层; 在基底层上沉积第一中间层，然后沉积第二中间层; 在形成第二中间层的同时基底层覆盖被加工层; 在图案化的第二中间层上沉积第一掩模图案; 用第一掩模图案图案化第二中间层; 用图案化的第二中间层图案化第一中间层和基底层以形成第二掩模图案; 并利用第二掩模图案来图案化待处理的层。

9. 发明授权

US08372718B2 Manufacturing method of semiconductor device and semiconductor device 有权
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US08372718B2
公开(公告)日：2013-02-12
申请号：US13607804
申请日：2012-09-10
申请人： Yasuhiro Fujii , Kazumasa Yonekura , Tatsunori Kaneoka
发明人： Yasuhiro Fujii , Kazumasa Yonekura , Tatsunori Kaneoka
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462 , H01L21/823418 , H01L21/823456 , H01L21/823481 , H01L29/0653 , H01L29/42364
摘要： An improvement is provided in a manufacturing yield of a semiconductor device including transistors in which gate insulating films have different thicknesses. After a high-breakdown-voltage insulating film is formed over a silicon substrate, a surface of the high-breakdown-voltage insulating film is abraded for a reduction in the thickness thereof so that a middle-breakdown-voltage insulating film is formed to be adjacent to the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed by a thermal oxidation method so as to extend from an inside of the main surface of the silicon substrate to an outside thereof. The middle-breakdown-voltage insulating film is formed so as to be thinner than the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed as the gate insulating film of a high-breakdown-voltage MIS transistor, while the middle-breakdown-voltage insulating film is formed as the gate insulating film of a middle-breakdown-voltage MIS transistor.
摘要翻译：提供一种半导体器件的制造成品率的提高，该半导体器件包括其中栅绝缘膜具有不同厚度的晶体管。在硅衬底上形成高耐压绝缘膜之后，高耐压绝缘膜的表面被磨损以减小其厚度，使得中间击穿电压绝缘膜形成为邻近高耐压绝缘膜。高耐压绝缘膜通过热氧化法形成，以从硅衬底的主表面的内部延伸到其外部。中间击穿电压绝缘膜形成为比高击穿电压绝缘膜薄。高击穿电压绝缘膜形成为高击穿电压MIS晶体管的栅极绝缘膜，而中间击穿电压绝缘膜形成为中间击穿电压MIS晶体管的栅极绝缘膜。

10. 发明授权

US08092703B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08092703B2
公开(公告)日：2012-01-10
申请号：US11808650
申请日：2007-06-12
申请人： Takeo Ishibashi , Kazumasa Yonekura , Masahiro Tadokoro , Kazunori Yoshikawa , Yoshiharu Ono
发明人： Takeo Ishibashi , Kazumasa Yonekura , Masahiro Tadokoro , Kazunori Yoshikawa , Yoshiharu Ono
IPC分类号： C03C15/00 , C03C25/68 , C23F1/00 , H01L21/302 , H01L21/461
CPC分类号： H01L21/31144 , H01L21/0332 , H01L21/0337 , H01L21/31058 , H01L21/31155 , H01L21/76808 , H01L21/76825 , H01L21/76826
摘要： It is an object of the present invention to provide a method of manufacturing a semiconductor device that reduces the deterioration in processed configuration and the pattern roughness of a film to be processed, and is close to the original design and applicable to a dual damascene step and the like. The manufacturing method comprises a processing mask layer forming step of forming a processing mask layer (a lower organic film and a middle layer) comprising at least one film, and hardening treatment for at least one film of the processing mask layer by applying a film and heat hardening treatment; a processing mask layer etching step of applying a resist film for exposure to the processing mask layer, exposing and developing it to form a resist pattern, and etching the processing mask layer using the resist pattern as a mask; and a film to be processed etching step of etching the film to be processed using the pattern of the processing mask layer formed at the processing mask layer etching step as a mask.
摘要翻译：本发明的目的是提供一种制造半导体器件的方法，该半导体器件减少加工结构的劣化和待加工薄膜的图案粗糙度，并且接近原始设计并且可应用于双镶嵌步骤和类似。该制造方法包括：处理掩模层形成步骤，形成包括至少一个膜的处理掩模层（下部有机膜和中间层），以及通过施加膜和至少一层加工掩模层的硬化处理热硬化处理; 处理掩模层蚀刻步骤，将用于曝光的抗蚀剂膜施加到处理掩模层，曝光和显影以形成抗蚀剂图案，并使用抗蚀剂图案作为掩模蚀刻处理掩模层; 以及使用在处理掩模层蚀刻步骤形成的处理掩模层的图案作为掩模来蚀刻待处理的膜的待处理蚀刻步骤的膜。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式